JP2005057860A - Step-up circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a step-up circuit which can reduce a layout area of a MOS transistor concerning a step-up capability and which perform a step-up operation certainly at a starting time. <P>SOLUTION: The step-up circuit includes the MOS transistors M1-M4 connected in series between an output voltage line 13 and a common connecting line 14 to perform a positive step-up operation of an input voltage VDD. The MOS transistors M1-M3 consist of ordinary P-type MOS transistors, and the MOS transistor M4 consists of an ordinary N-type MOS transistor. The MOS transistors M21-M24 are connected in series between the output voltage line 13 and the common connecting line 14 to perform a positive step-up operation of the input voltage VDD in parallel with the MOS transistors M1-M4. The MOS transistor M21 consists of an ordinary P-type MOS transistor, and the MOS transistor M24 consists of an ordinary N-type MOS transistor. On the other hand, the MOS transistors M22, M23 consist of N-type MOS transistors of a triple well structure. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a booster circuit capable of obtaining a desired voltage by a charge pump method, and relates to a booster circuit used in various power supply devices such as a liquid crystal display.

Conventionally, as an example of a power supply device used for a liquid crystal display, the one shown in FIG. 5 is known.
As shown in FIG. 5, this power supply device stabilizes the output voltages of the charge pump type positive booster circuits 1 and 2, the charge pump type negative booster circuit 3, and the booster circuits 1 to 3. Voltage stabilizing circuits 4 to 6 and a timing generator 7 for controlling each boosting operation of the boosting circuits 1 to 3 are provided, and desired positive and negative voltages are extracted from the voltage stabilizing circuits 4 to 6. It has become.

The positive booster circuit 1 boosts the input voltage VDD to a double positive voltage. The positive booster circuit 2 boosts the output voltage of the positive booster circuit 1 to a positive voltage that is a predetermined multiple (for example, twice). The negative booster circuit 3 boosts the output voltage of the booster circuit 1 to a negative voltage that is a predetermined multiple (for example, twice).
Next, a specific configuration of the positive booster circuit 1 will be described with reference to FIG.

As shown in FIG. 6, the booster circuit 1 has MOS transistors M1 to M4 that gradually increase the output voltage at the beginning of boosting, and the output voltage is rapidly increased when a certain boosted voltage is obtained. MOS transistors M11 to M14 to be boosted, a boosting capacitor C1, and an output capacitor C2.
A control signal from the timing generator 7 shown in FIG. 5 is applied to the gates of the MOS transistors M1 to M4 and the MOS transistors M11 to M14, whereby on / off control of the MOS transistors is performed.

  MOS transistors M1 to M4 having a small transistor size are used, and MOS transistors M1 to M3 are P-type (P channel), and MOS transistor M4 is N-type (N channel). MOS transistors M11 to M14 having a large transistor size are used, the MOS transistors M11 to M13 are P-type, and the MOS transistor M14 is N-type.

Next, the boosting operation of the booster circuit 1 having such a configuration will be described.
In the booster circuit 1, when the boosting operation is started, only the MOS transistors M1 to M4 operate at the initial stage. That is, first, the MOS transistors M2 and M4 are turned on, and the capacitor C1 is charged by the input voltage VDD (for example, 3V). Next, the MOS transistors M1 and M3 are turned on, the input voltage VDD is applied to the charging voltage of the capacitor C1, and the applied voltage becomes the output voltage VOUT. By repeating such an operation, the output voltage VOUT gradually rises.

Then, after a predetermined time has elapsed from the start of the boosting operation (or when the output voltage VOUT becomes a predetermined voltage), the MOS transistors M11 to M14 start to operate in parallel with the operations of the MOS transistors M1 to M4.
That is, the MOS transistors M12 and M14 are turned on simultaneously with the turning on of the MOS transistors M2 and M4, and the capacitor C1 is charged by the input voltage VDD. Next, the MOS transistors M11 and M13 are turned on simultaneously with the turning on of the MOS transistors M1 and M3, the input voltage VDD is applied to the charging voltage of the capacitor C1, and the applied voltage becomes the output voltage VOUT. By repeating such an operation, the output voltage VOUT becomes a desired value (for example, 6V).

  Such a series of operations can suppress voltage fluctuations in the power supply of the booster circuit.

  By the way, in this conventional booster circuit, in order to increase the current capability at the time of charging a capacitor or the like to increase the boost capability, it is necessary to increase the transistor size of the MOS transistors M11 to M14, for example. Therefore, in the conventional booster circuit, the transistor sizes of the MOS transistors M11 to M14 are increased in order to increase the boosting capability.

However, in the MOS transistors 11 to M14, the MOS transistors M11 to M13 are P-type, and the MOS transistor M14 is N-type. That is, of the four MOS transistors 11 to M14 that influence the boosting capability, three MOS transistors M11 to M13 are of P type, and P type MOS transistors are frequently used.
Since the P-type MOS transistor has a large layout area, when increasing the boosting capability, it is necessary to increase the layout area of the three MOS transistors, and there is a problem that the layout area becomes large as a whole.

As described above, in the conventional booster circuit, P-type MOS transistors are frequently used as MOS transistors that influence the boosting capability. Therefore, when the boosting capability is increased, the layout area of the MOS transistor related to the boosting capability is as a whole. There is a problem that it gets bigger.
Although it is desired to eliminate such a problem, it is desirable that the voltage boosting operation can be surely performed at the time of start-up.

  In view of the above, an object of the present invention is to provide a booster circuit that can reduce the layout area of a MOS transistor related to boost capability and can reliably perform a boost operation at startup.

In order to solve the above-described problems and achieve the object of the present invention, each invention is configured as follows.
That is, the first invention is a charge pump type booster circuit, which is connected in series between an output voltage line and a common connection line, and comprises at least four first MOS transistors for positively boosting an input voltage. And a group of at least four second MOS transistors connected in series between the output voltage line and the common connection line and performing positive boosting of the input voltage in conjunction with the first MOS transistor. In the first MOS transistor group, the common connection line side is configured by a normal N-type MOS transistor, and the remaining portion is configured by a normal P-type MOS transistor, and the second MOS transistor group is configured as described above. The common connection line side is composed of a normal N-type MOS transistor and the output voltage line side is Constituted by type MOS transistor, and the portion except for the two MOS transistors have the N-type MOS transistor comprising a triple-well structure to include at least one.

  According to a second invention, in the first invention, the first MOS transistor group is composed of four, the common connection line side is constituted by one normal N-type MOS transistor, and the remaining three are set as normal The second MOS transistor group is composed of four P-type MOS transistors, the common connection line side is composed of one ordinary N-type MOS transistor, and the output voltage line side is composed of one ordinary Two P-type MOS transistors, except for both MOS transistors, were made up of N-type MOS transistors having a triple well structure.

According to a third invention, in the first or second invention, the first MOS transistor group is on / off controlled so as to gradually perform a boosting operation at the start of boosting of the input voltage, and after a predetermined time has elapsed from the start of boosting. The second MOS transistor group is controlled to be turned on / off so as to perform a step-up operation in parallel with the first MOS transistor group.
According to the present invention having such a configuration, the layout area of the MOS transistor related to the boosting capability can be reduced, and the boosting operation can be surely performed at the start-up.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
The configuration of the embodiment of the booster circuit of the present invention will be described with reference to FIG.
The booster circuit according to this embodiment is a charge pump type booster circuit, and, as shown in FIG. 1, MOS transistors M1 to M4 (in order to gradually increase the output voltage VOUT at the start of boosting (at the start of startup)). A first MOS transistor group), MOS transistors M21 to M24 (second MOS transistor group) that increase the output voltage VOUT at once after the start of boosting, a boosting capacitor C1, an output capacitor C2, an input terminal 11, And an output terminal 12.

The MOS transistors M1 to M4 are connected in series between the high-potential output voltage line 13 and the low-potential common connection line 14 to perform a positive boost operation of the input voltage VDD. The output voltage line 13 is connected to the output terminal 12, and the common connection line 14 is connected to the ground.
MOS transistors M1 to M4 having a small transistor size are used. Further, the MOS transistors M1 to M3 are composed of ordinary P-type MOS transistors, and the MOS transistor M4 is composed of an ordinary N-type MOS transistor.

Control signals S1 to S4 as shown in FIG. 3 generated by a control circuit (not shown) are applied to the gates of the MOS transistors M1 to M4 so that the MOS transistors M1 to M4 are turned on / off. It has become.
The MOS transistors M21 to M24 are connected in series between the output voltage line 13 and the common connection line 14, and perform a positive boosting operation of the input voltage VDD in parallel (connected) with the MOS transistors M1 to M4. Is.

Since the MOS transistors M21 to M24 have larger transistor sizes, the MOS transistors M21 to M24 have larger transistor sizes than the MOS transistors M21 to M24.
The MOS transistor M21 is a normal P-type MOS transistor, and the MOS transistor M4 is a normal N-type MOS transistor. On the other hand, the MOS transistors M22 and M23 are N-type MOS transistors having a triple well structure, and this embodiment has a feature of this embodiment.

Control signals S5 to S8 shown in FIG. 3 generated by a control circuit (not shown) are applied to the gates of the MOS transistors M21 to M24 so that the MOS transistors M21 to M24 are controlled to be turned on / off. It has become.
Here, the MOS transistors M1 to M4 correspond to the MOS transistors M1 to M4 shown in FIG. MOS transistors M21 to M24 correspond to MOS transistors M11 to M14 shown in FIG.

The input terminal 11 is supplied with an input voltage VDD. The input terminal 11 is connected to a common connection portion between the MOS transistors M2 and M3 and a common connection portion between the MOS transistors M22 and M23.
One end side of the boosting capacitor C1 is connected to a common connection portion between the MOS transistor M1 and the MOS transistor M2 and a common connection portion between the MOS transistor M21 and the MOS transistor M22. The other end of the capacitor C1 is connected to a common connection between the MOS transistors M3 and M4 and a common connection between the MOS transistors M23 and M24.

The output capacitor C <b> 2 has one end connected to the output voltage line 13 and the other end connected to the common connection line 14. An output voltage VOUT is taken out from the output terminal 12.
Next, since the MOS transistors M22 and M23 are N-type MOS transistors having a triple well structure, the structure will be described with reference to FIG.

  This triple well structure N-type MOS transistor is configured using, for example, a P-type semiconductor substrate 21 as shown in FIG. That is, an N-type well 22 is formed in a P-type semiconductor substrate 21, and a P-type well 23 is formed in the N-type well 22. An N-type region 24 is formed in the P-type well 23 and connected to the drain electrode. Further, an N-type region 25 and a P-type region 26 are formed in the well 23, and these are connected in common to connect the common connection portion to the source electrode. Further, a metal film 27 is formed on the top of the well 23 with an insulator interposed therebetween, and this is connected to the gate electrode.

Next, the boosting operation of the embodiment having such a configuration will be described.
In this embodiment, as shown in FIGS. 3 and 4, when the boosting operation is started at time t1, only the MOS transistors M1 to M4 operate at the initial stage.
That is, in the period T1 shown in FIG. 3, since the control signal S2 is L level and the control signal S4 is H level, the MOS transistors M2 and M4 are turned on, and the capacitor C1 is charged by the input voltage VDD (for example, 3V). The

In the period T2 shown in FIG. 3, since the control signal S1 is at L level and the control signal S3 is at L level, the MOS transistors M1 and M3 are turned on, and the input voltage VDD is applied to the charging voltage of the capacitor C1. The voltage becomes the output voltage VOUT. By repeating such an operation, the output voltage VOUT gradually increases as shown in FIG.
Then, at time t2 after elapse of a predetermined time from the start time t1 of the boost operation, the MOS transistors M21 to M24 start to operate in parallel with the operation of the MOS transistors M1 to M4.

That is, in the period T3 shown in FIG. 3, the control signal S2 is at L level, the control signal S4 is at H level, the control signal S6 is at H level, and the control signal S8 is at H level, so that the MOS transistors M2, M4, M22, M24 is turned on, and the capacitor C1 is rapidly charged by the input voltage VDD.
In the period T4 shown in FIG. 3, the control signal S1 is L level, the control signal S3 is L level, the control signal S5 is L level, and the control signal S7 is H level, so that the MOS transistors M1, M3, M21, and M23 are The input voltage VDD is applied to the charging voltage of the capacitor C1, and the applied voltage becomes the output voltage VOUT. By repeating such an operation, the output voltage VOUT is boosted to a desired value of 6V as shown in FIG.

As described above, in this embodiment, since the MOS transistors M22 and M23 are configured by triple well N-type MOS transistors, the layout area can be reduced. For example, in the case of the same boosting capability as in the prior art, the layout area of the portion of the MOS transistor related to the boosting capability can be reduced to 60% to 70%.
In this embodiment, the MOS transistors M22 and M23 are N-type MOS transistors having a triple well structure, and an ON operation is performed by applying an H level control signal to the gate.

However, in this embodiment, since the positive boosted voltage is obtained by the MOS transistors M1 to M4 at the time of startup and the MOS transistors M21 to M24 are operated thereafter, the on / off operation of the MOS transistors M22 and M23 is ensured. Thus, the boosting operation at the time of start-up can be performed reliably.
In the above embodiment, both MOS transistors M22 and M23 are triple-well N-type MOS transistors, but only one of them may be used. In one case, the MOS transistor M23 is preferable.

In the above embodiment, the case of double boosting has been described as the boosting circuit. However, the present invention can be applied to a boosting circuit such as triple boosting instead. In this case, there are four or more MOS transistors M1 to M4 and MOS transistors M21 to M24 shown in FIG.
In the above embodiment, the MOS transistors M1 to M4 and the MOS transistors M21 to M24 are provided. However, instead of this, four MOS transistor groups may be added between the MOS transistors M1 to M4 and the MOS transistors M21 to M24. In this case, the added four MOS transistor groups are connected in series between the output voltage line 13 and the common connection line 14 shown in FIG.

It is a circuit diagram which shows the structure of embodiment of this invention. FIG. 2 is a cross-sectional view showing a structure of an N-type MOS transistor having a triple well structure shown in FIG. 1. FIG. 2 is a waveform diagram showing an example of a control signal applied to each gate of the MOS transistor shown in FIG. 1. It is a figure which shows an example of the output voltage at the time of a pressure | voltage rise operation. It is a block diagram which shows the structural example of the conventional power supply device. It is a circuit diagram which shows the structural example of the conventional booster circuit.

Explanation of symbols

  M22, M23... Triple-well N-type MOS transistor, VDD... Input voltage, VOUT... Output voltage, 11... Input terminal, 12. ... Output voltage line, 14 ... Common connection line.

Claims (3)

A charge pump type booster circuit,
A first MOS transistor group comprising at least four transistors connected in series between the output voltage line and the common connection line, and performing positive boosting of the input voltage;
A second MOS transistor group consisting of at least four connected in series between the output voltage line and the common connection line and performing positive boosting of the input voltage in conjunction with the first MOS transistor;
In the first MOS transistor group, the common connection line side is configured by a normal N-type MOS transistor, and the remaining portion is configured by a normal P-type MOS transistor,
In the second MOS transistor group, the common connection line side is constituted by a normal N-type MOS transistor, the output voltage line side is constituted by a normal P-type MOS transistor, and the portions excluding both MOS transistors are as follows: A booster circuit comprising at least one N-type MOS transistor having a triple well structure. The first MOS transistor group is composed of four, and the common connection line side is configured by one normal N-type MOS transistor, and the remaining three are configured by normal P-type MOS transistors.
The second MOS transistor group is composed of four, the common connection line side is constituted by one normal N-type MOS transistor, the output voltage line side is constituted by one normal P-type MOS transistor, and 2. The booster circuit according to claim 1, wherein the two except for both MOS transistors are constituted by N-type MOS transistors having a triple well structure. The first MOS transistor group is ON / OFF controlled so as to gradually perform a boosting operation at the start of boosting of the input voltage,
2. The on-off control of the second MOS transistor group is performed so as to perform a boost operation at once in parallel with the first MOS transistor group after a predetermined time has elapsed since the boost start. Alternatively, the booster circuit according to claim 2.

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