JP2005057451A - Programmable logic circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a low-cost programmable logic circuit having a high area efficiency and for realizing a large scale and high speed logic circuit. <P>SOLUTION: Each of a plurality of unit logic circuits is provided with a processor element 101 and a memory device 102. The processor element 101 includes a logic cell 300 the function of which can be changed on the basis of first setting information and applying prescribed logic arithmetic operation processing to an input signal to produce data and a cross connect switch 301 for carrying out arrangement, copying and inversion processing of the data from the logic arithmetic means on the basis of second setting information to generate data. Each of the plurality of unit logic circuits sequentially changes part or all of functions of the logic cell 300 and the cross connect switch 301 on the basis of the first and second setting information sequentially read from the memory device 102 and carries out operations of a prescribed sequence circuit. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a programmable logic circuit capable of realizing a predetermined logic operation function by programming, and more particularly to a dynamic programmable logic circuit that performs processing while dynamically changing an internal configuration.

  There exists a thing of patent document 1 as a conventional programmable logic circuit. This conventional programmable logic circuit is a dynamically reconfigurable field programmable logic device that uses a dynamic interconnect array, a latch circuit, and a dynamic logic core to execute the circuit to be implemented in stages. In the conventional programmable logic circuit, when a large-scale logic circuit is realized, a plurality of the programmable logic circuits are connected in series so that each level of logic processing is executed in order.

In this case, in the conventional programmable logic circuit, when the internal level of the first chip reaches a prescribed level using the circuit level counter indicating the circuit level and the internal counter indicating the internal level, the next chip is It is controlled to operate. That is, in the conventional programmable logic circuit, the circuit level is divided and embodied on a chip basis.
Japanese translation of PCT publication No. 8-51085

  However, in the conventional programmable logic circuit, there is a problem that the processing time increases because it is necessary to suppress the processing parallelism to a single chip in order to realize a larger-scale logic circuit. Also, in conventional programmable logic circuits, in order to shorten the processing time, increasing the number of dynamic logic modules contained in a single chip to increase the processing parallelism, the dynamic interconnection is proportional to this. Since the number of array connection points increases and the necessary setting information increases, there is a problem that the mounting circuit area increases.

  The present invention has been made in view of this point, and an object of the present invention is to provide a low-cost programmable logic circuit having high area efficiency and capable of realizing a large-scale logic circuit at high speed.

  The invention according to claim 1 includes a plurality of unit logic circuits connected in parallel, input signal control means for supplying an input signal received from the outside to the plurality of unit logic circuits, and a plurality of unit logic circuits. Output signal control means for supplying an output signal to the outside, each of the plurality of unit logic circuits can be changed in function based on the first setting information, and the input signal has a predetermined logic Logical operation means for generating data by performing arithmetic processing, and generating data by performing alignment, duplication and inversion processing of the data from the logical operation means based on second setting information, and generating the output signal as the output signal A data processing means for providing to the output signal control means; and a storage means for storing the first and second setting information, wherein each of the plurality of unit logic circuits sequentially reads from the storage means. And a configuration for performing the operation of some or all of the functions are sequentially changed predetermined sequential circuit of the data processing means and said logical operation means based on second setting information.

  According to this configuration, some or all of the functions of the logic operation circuit and the data processing unit are sequentially changed based on the first and second setting information that each of the plurality of unit logic circuits sequentially reads from the storage unit. Since a predetermined sequential circuit is operated, a low-cost programmable logic circuit having high area efficiency and capable of realizing a large-scale logic circuit at high speed can be provided.

  According to a second aspect of the present invention, in the first aspect of the present invention, the logical operation means can change a function based on the first setting information, and a predetermined logical operation process is performed on the input signal. And adopting a configuration including a logic cell for generating the data.

  According to this configuration, some or all of the functions of the logic operation circuit and the data processing unit are sequentially changed based on the first and second setting information that each of the plurality of unit logic circuits sequentially reads from the storage unit. Since a predetermined sequential circuit is operated, a low-cost programmable logic circuit having high area efficiency and capable of realizing a large-scale logic circuit at high speed can be provided.

  According to a third aspect of the present invention, in the first or second aspect of the present invention, the data processing unit is configured to arrange and copy the data from the logical operation unit based on the second setting information. A configuration including a cross-connect switch that performs inversion processing and generates the data is adopted.

  According to this configuration, some or all of the functions of the logic operation circuit and the data processing unit are sequentially changed based on the first and second setting information that each of the plurality of unit logic circuits sequentially reads from the storage unit. Since a predetermined sequential circuit is operated, a low-cost programmable logic circuit having high area efficiency and capable of realizing a large-scale logic circuit at high speed can be provided.

  According to a fourth aspect of the invention, there is provided the flip-flop according to the third aspect, wherein the data processing means holds the data from the cross-connect switch and supplies the data to the output signal control means as the output signal. The structure to do is taken.

  According to this configuration, some or all of the functions of the logic operation circuit and the data processing unit are sequentially changed based on the first and second setting information that each of the plurality of unit logic circuits sequentially reads from the storage unit. Since a predetermined sequential circuit is operated, a low-cost programmable logic circuit having high area efficiency and capable of realizing a large-scale logic circuit at high speed can be provided.

  According to a fifth aspect of the present invention, a plurality of unit logic circuits connected in parallel, one unit logic circuit in the plurality of unit logic circuits, and a physical arrangement with respect to the one unit logic circuit are provided. Connecting means for connecting the other adjacent unit logic circuits, input signal control means for supplying input signals received from the outside to the plurality of unit logic circuits, and output signals of the plurality of unit logic circuits to the outside Output signal control means for supplying each of the plurality of unit logic circuits, the function of which can be changed based on the first setting information, the input signal or the other unit logic circuit adjacent thereto Logic operation means for generating data by performing predetermined logic operation processing on the data from the data, and generating data by performing alignment, duplication and inversion processing of the data from the logic operation means based on second setting information Shi A data processing unit that supplies the output signal control unit as the output signal; and a storage unit that stores the first and second setting information. Each of the plurality of unit logic circuits includes: Based on the first and second setting information read out sequentially, a configuration is adopted in which some or all of the functions of the logical operation means and the data processing means are sequentially changed to operate a predetermined sequential circuit.

  According to this configuration, some or all of the functions of the logic operation circuit and the data processing unit are sequentially changed based on the first and second setting information that each of the plurality of unit logic circuits sequentially reads from the storage unit. Since a predetermined sequential circuit is operated, a low-cost programmable logic circuit having high area efficiency and capable of realizing a large-scale logic circuit at high speed can be provided.

  According to a sixth aspect of the present invention, in the fifth aspect of the present invention, the logical operation means can change a function based on the first setting information, and the input signal or the other of the adjacent signals can be changed. A configuration is adopted in which a logic cell for generating the data by performing a predetermined logical operation process on the data from the unit logic circuit is adopted.

  According to this configuration, some or all of the functions of the logic operation circuit and the data processing unit are sequentially changed based on the first and second setting information that each of the plurality of unit logic circuits sequentially reads from the storage unit. Since a predetermined sequential circuit is operated, a low-cost programmable logic circuit having high area efficiency and capable of realizing a large-scale logic circuit at high speed can be provided.

  According to a seventh aspect of the invention, in the invention of the fifth or sixth aspect, the data processing means performs alignment and duplication of the data from the logical operation means based on the second setting information. A configuration including a cross-connect switch that performs inversion processing and generates the data is adopted.

  According to this configuration, some or all of the functions of the logic operation circuit and the data processing unit are sequentially changed based on the first and second setting information that each of the plurality of unit logic circuits sequentially reads from the storage unit. Since a predetermined sequential circuit is operated, a low-cost programmable logic circuit having high area efficiency and capable of realizing a large-scale logic circuit at high speed can be provided.

  The invention according to claim 8 is the invention according to claim 7, wherein the data processing means includes a flip-flop that holds the data from the cross-connect switch and supplies the data to the output signal control means as the output signal. The structure to do is taken.

  According to this configuration, some or all of the functions of the logic operation circuit and the data processing unit are sequentially changed based on the first and second setting information that each of the plurality of unit logic circuits sequentially reads from the storage unit. Since a predetermined sequential circuit is operated, a low-cost programmable logic circuit having high area efficiency and capable of realizing a large-scale logic circuit at high speed can be provided.

  As described above, according to the present invention, some or all of the logic operation means and the data processing means are based on the first and second setting information that each of the plurality of unit logic circuits sequentially reads from the storage means. Since the functions of these are sequentially changed to operate a predetermined sequential circuit, it is possible to provide a low-cost programmable logic circuit having high area efficiency and capable of realizing a large-scale logic circuit at high speed.

  The essence of the present invention is that a part or all of the functions of the logic operation means and the data processing means are sequentially changed based on the first and second setting information that each of the plurality of unit logic circuits sequentially reads from the storage means. Thus, the operation of a predetermined sequential circuit is performed.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

(Embodiment 1)
FIG. 1 is a block diagram showing a configuration of a programmable logic circuit according to Embodiment 1 of the present invention.

  As shown in FIG. 1, the programmable logic circuit 100 according to the first embodiment of the present invention includes a plurality of processor elements 101, a plurality of memory devices 102, an input / output control unit 103, a control bus 104, an input bus 105, and an output bus. 106. A clock generation circuit 107 and a user circuit 108 are connected to the programmable logic circuit 100.

  The plurality of processor elements 101 and the plurality of memory devices 102 are connected on a one-to-one basis. The processor elements 101 and the memory devices 102 connected in a one-to-one manner constitute a unit logic circuit. The plurality of unit logic circuits are connected in parallel.

  Each of the plurality of processor elements 101 is arranged one-dimensionally in a row, and is connected to two other processor elements 101 adjacent to each other on the physical arrangement by a connection line 101a. In other words, the plurality of unit logic circuits are arranged one-dimensionally in a single column, and one unit logic circuit in the plurality of unit logic circuits and the one unit logic circuit are physically arranged. The other adjacent unit logic circuits are connected by a connection line 101a.

  The processor element 101 exchanges data with two other adjacent processor elements 101 using a connection line.

  The input / output control unit 103 is an interface circuit with the outside, and is connected to the user circuit 108. The control bus 104 is connected to the input / output control unit 103 and the processor element 101. The control bus 104 receives control signals such as initialization and activation from the input / output control unit 103 and transfers them to each processor element 101. The input bus 105 is connected to the input / output control unit 103 and the processor element 101. The input bus 105 receives data used for logical operations from the input / output control unit 103 and transfers the data to each processor element 101.

  The output bus 106 is connected to the input / output control unit 103 and the processor element 101. The output bus 106 receives operation result data from the processor element 101 and transfers it to the input / output control unit 103. The clock generation circuit 107 generates an internal clock signal 109 and a user clock signal 110. The user clock signal 110 is used by the user circuit 108 and the input / output control unit 103. The internal clock signal 109 has a frequency multiplied by the user clock signal 110 and is used inside the programmable logic circuit 100.

  Next, functions of the programmable logic circuit 100 will be described with reference to the drawings.

  In FIG. 1, the contents of the logical operation processing performed by the programmable logic circuit 100 are held as setting information in the memory device 102. Each processor element 101 sequentially reads setting information of the memory device 102 and performs a corresponding logical operation process. The programmable logic circuit 100 receives a start signal and data used for logic operation in synchronization with the user clock signal 110 from the user circuit 108. After a predetermined time has elapsed, the programmable logic circuit 100 gives the data after the logical operation processing to the user circuit 108 in synchronization with the user clock signal 110.

  Next, functions of internal blocks of the programmable logic circuit 100 will be described with reference to the drawings.

  In FIG. 1, each memory device 102 stores setting information of the adjacent processor element 101. When a control signal and a memory address are input from the processor element 101, the memory device 102 provides setting information specified by the address to the processor element 101. The processor element 101 determines the processing content to be executed based on this setting information.

  When an initialization signal is input from the control bus 104, the processor element 101 reads a specific address of the memory device 102, extracts the storage location address of the setting information from the input read data, and holds it. This storage position address is an address indicating the head position of the setting information.

  Further, when an activation signal is input from the control bus 104, the processor element 101 sequentially reads setting information from the stored storage location address of the memory device 102. Furthermore, the processor element 101 receives data for logical processing from the input bus 105 and the adjacent processor element 101, performs logical processing on the data based on the setting information, performs data alignment, duplication, and inversion processing, and The data after processing is retained. Further, the processor element 101 outputs the held processed data to the output bus 106 and the adjacent processor element 101.

  In this way, the plurality of processor elements 101 exchange data. The input / output control unit 103 receives the activation signal and logic processing data synchronized with the user clock signal 110 from the user circuit 108, and supplies this data to the input bus 105 in synchronization with the internal clock signal 109. The input / output control unit 103 receives an initialization signal synchronized with the user clock signal 110 from the user circuit 108 and outputs the data to the input bus 105 in synchronization with the internal clock signal 109. The input / output control unit 103 receives data after logical processing synchronized with the internal clock signal 109 from the output bus 106 and outputs this data to the user circuit 108 in synchronization with the user clock signal 110. In this manner, the input / output control unit 103 exchanges control signals with the user circuit 108, data for logical processing, and processing result data.

  Next, the configuration of the processor element 101 in the programmable logic circuit 100 will be described with reference to the drawings.

  FIG. 2 shows the configuration of the processor element 101. As shown in FIG. 2, the processor element 101 includes a logic element 200 and a memory control unit 201. The processor element 101 is connected to the memory device 102, the control bus 104, the input bus 105, and the output bus 106. The memory control unit 201 is connected to the memory device 102, the logic element 200, and the control bus 104. The logic element 200 is connected to the logic element 200, the memory control unit 201, the input bus 105, and the output bus 106 of the adjacent processor selection 101.

  Next, functions of the processor element 101 will be described with reference to the drawings. In FIG. 2, when the memory control unit 201 receives the initialization signal from the control bus 104, the memory control unit 201 performs the above-described storage location address extraction and holding processing. When an activation signal is input from the control bus 104, the memory control unit 201 sequentially reads setting information from the stored storage location address of the memory device 102 and transfers it to the logic element 200.

  The logic element 200 receives data from the input bus 105 and the adjacent processor element 101, performs logical processing on the data based on the setting information transferred from the memory control unit 201, and then performs data alignment, duplication, and inversion processing. In addition, the data after processing is retained. The logic element 200 outputs the processed data to the output bus 106 and the adjacent processor element 101 based on the setting information transferred from the memory control unit 201.

  Next, the configuration of the logic element 200 inside the processor element 101 and the configuration of setting information will be described with reference to the drawings.

  FIG. 3 shows the configuration of the logic element 200. FIG. 4 shows the configuration of the setting information and the memory device 102.

  In FIG. 3, the logic element 200 includes a logic cell (logic operation circuit) 300, a cross-connect switch (data processing device) 301, and a flip-flop 302. The logic element 200 is connected to the memory control unit 201, the input bus 105, and the output bus 106. The logic cell 300 is connected to the memory control unit 201, the flip-flop 302, and the cross-connect switch 301. The cross-connect switch 301 is connected to the memory control unit 201, the logic cell 300, the flip-flop 302, the input bus 105, and the logic cell 300 inside the adjacent logic element 200. The flip-flop 302 is connected to the logic cell 300, the cross-connect switch 301, and the output bus 106.

  The logic cell 300 constitutes a logic operation circuit. The cross-connect switch 301 constitutes a data processing device. The cross connect switch 301 and the flip-flop 302 constitute a data processing device.

  FIG. 4 shows the configuration of the memory device. In FIG. 4, the storage address information of the setting information is stored at the top portion inside the memory device 102. Setting information is stored in a specific area inside the memory device 102 other than the head portion.

  In FIG. 4, bits 25 to 28 are setting information of the logic cell 300, and bits 0 to 24 are connection information of the cross-connect switch 301. Bits 0 to 24 are composed of 4-bit connection information and 1-bit inversion control information corresponding to the five outputs of the cross-connect switch 301 in 5-bit units.

  Next, the function of the logic element 200 will be described with reference to the drawings. In FIG. 3, the logic cell 300 performs specific logic processing specified by the setting information transferred from the memory control unit 201 on the data input from the flip-flop 302, and performs cross-connect switch 301 and adjacent processor elements. The processed data is output to the logic element 200 of 101. The cross-connect switch 301 aligns specific data specified by setting information transferred from the memory control unit 201 with respect to data input from the logic cell 300, the input bus 105, and the logic element 200 of the adjacent processor element 101. , Duplication and inversion processing are performed, and the processed data is output to the flip-flop 302. The flip-flop 302 holds the data input from the cross-connect switch 301 at the timing of the internal clock signal 109. The flip-flop 302 outputs the held data to the logic cell 300 and the output bus 106.

  Next, functions and operations of the logic cell 300 will be described using specific examples.

  In FIG. 5, 2 bits of setting information and 2 bits of input data are input to the logic cell 300, and the logic cell 300 outputs 1 bit of output data. FIG. 6 shows an example of the function and operation of the logic cell 300 in this case. In FIG. 6, when the setting information is 00, the logic cell 300 outputs a logical sum (OR) of input data. When the setting information is 01, the logic cell 300 outputs a logical product (AND) of input data. When the setting information is 10, the logic cell 300 outputs an exclusive OR (XOR) of the input data. When the setting information is 11, the logic cell 300 outputs inverted data (NOR) of the logical sum of the input data. Thus, the logic cell 300 is a circuit capable of realizing a plurality of different logic functions based on the setting information.

  Next, the function of the cross-connect switch 301 will be described using a specific example.

  FIG. 7 shows an example of internal blocks and functions of the cross-connect switch 301. In FIG. 7, 4 bits of setting information and 3 bits of input data A, B, and C and a low level are input to the interconnection unit 700 inside the cross-connect switch 301, and output data OUT <b> 1 and OUT <b> 2 are input from the interconnection unit 700. Two bits are output. Further, each output data of the interconnection unit 700 is subjected to exclusive OR (XOR) with 1 bit of the setting information and output to the outside. This XOR is for inverting the output data from the cross-connect switch 301 in bit units based on the setting information. In this case, since the number of outputs is 2, 2 bits of setting information is used in the XOR portion, so the setting information used in the entire cross-connect switch 301 is 6 bits in total.

  FIG. 8 shows an example of the function of the interconnection unit 700 in this case. In FIG. 8, the interconnection unit 700 selects data in which 2 bits of MSB of the setting information are output to OUT1, and selects data in which 2 bits of LSB are output to OUT2. The interconnection unit 700 outputs the input data A when the setting information is 00, and outputs the input data B when the setting information is 01. The interconnection unit 700 outputs the input data C when the setting information is 10, and outputs the low level when the setting information is 11.

  As described above, the cross-connect switch 301 is a circuit that can perform alignment, duplication, and inversion processing of a plurality of input data based on setting information, and can also output a fixed value set in the setting information. is there.

  Next, the operation of the programmable logic circuit 100 will be described with reference to the drawings. 9 and 10 show examples of operation timings of the programmable logic circuit 100. FIG. FIG. 9 shows an initialization operation from the outside. FIG. 10 shows the external activation and actual logic processing operations.

  First, in the T1 period, the input / output control unit 103 receives an initialization signal 900 synchronized with the user clock signal 110 from the user circuit 108 and holds it as an internal initialization signal 901. In the period T 2, the input / output control unit 103 outputs the held internal initialization signal 901 to the control bus 104 in synchronization with the internal clock signal 109. The internal initialization signal 902 of the control bus 104 is input to the memory control unit 201 of all the processor elements 101.

  In the T3 period, the memory control unit 201 of the processor element 101 outputs a read signal 903 to a specific address 904 of the memory device 102 using the input internal initialization signal 902 as a trigger. After that, the memory control unit 201 once holds the input read data 905 as held data 906, and extracts the setting information storage location address 907 from the held data 906 and holds it. By the operation from T1 to T3, the storage position address 907 of the setting information is stored in each processor element 101, and the process can be executed at any time.

  In the period T4, the programmable logic circuit 100 is in a startup waiting state. In the period T5, the input / output control unit 103 receives the activation signal 1000 and internal processing data 1001 synchronized with the user clock signal 110 from the user circuit 108, and holds them as the internal activation signal 1002 and the internal processing data 1003. In the period T 6, the input / output control unit 103 outputs the held internal activation signal 1002 to the control bus 104 in synchronization with the internal clock signal 109. The input / output control unit 103 outputs the held internal processing data 1003 to the input bus 105 in synchronization with the internal clock signal 109.

  The internal activation signal 1004 of the control bus 104 is input to the memory control unit 201 of all the processor elements 101. The logic processing data 1005 on the input bus 105 is input to the logic elements 200 of all the processor elements 101. In the T7 period, the memory control unit 201 of each processor element 101 outputs a read signal 903 to the storage location address 1007 held in the T3 period of the memory device 102 using the input internal activation signal 1004 as a trigger. In the T8 period, each memory control unit 201 holds read data 905 output from the memory device 102 as held data 906. At the same time, the memory control unit 201 outputs a read signal 903 to the next address of the memory device 102.

  In the T9 period, each memory control unit 201 outputs the retained data 906 to the logic element 200. Each memory control unit 201 holds read data 905 output from the memory device 102. At the same time, each memory control unit 201 outputs a read signal to the next address of the memory device 102. Each logic element 200 performs alignment, duplication, and inversion processing of the logic processing data 1005 from the input bus 105 based on the held data (setting information) 906 that is input, and the processed data is transferred to the internal flip-flop 302. Hold on.

  In the T10 period, each memory control unit 201 outputs the retained data 906 to the logic element 200. In addition, each memory control unit 201 holds read data 905 output from the memory device 102 therein. At the same time, each memory control unit 201 outputs a read signal to the next address of the memory device 102.

  Each logic element 200 performs logic processing on the logic processing data 1005 from the flip-flop 302, the input bus 105, and the adjacent processor element 101 based on the input retained data (setting information) 906, and performs post-processing Data is held in the flip-flop 302. Hereinafter, one logical process is realized by repeating the process of the T10 period.

  In all periods, the data of the flip-flop 302 is output to the output bus 106, and the input / output control unit 103 always holds this data in synchronization with the internal clock signal 109. The input / output control unit 103 outputs the retained data to the user circuit 108 in synchronization with the user clock signal 110. The user circuit 108 refers to a flag of input data and holds output data (data after logical processing) or holds data after a predetermined period.

  Next, an example in which a specific logic processing function is mapped to the programmable logic circuit 100 will be described with reference to the drawings. For the sake of brevity, only the operation of the logic element 200 in the T9 and T10 periods shown in the operation example will be described.

  FIG. 11 shows the function of the logic cell 300 with two inputs and two outputs. FIG. 12 shows an example in which a 4-bit comparison circuit is mapped to the programmable logic circuit 100 having the logic cell 300. In FIG. 12, four processor elements 101 which are physically different are shown in the vertical direction, and what kind of processing the same processor element 101 performs in each cycle is shown in the horizontal direction.

  FIG. 13 shows a 4-bit comparison circuit. As shown in FIG. 13, there are 8-bit data of IN0 to IN7 as input data, and the comparison result of IN0 to 3 and IN4 to 7 is output as 1-bit data.

  In FIG. 12, the input and output of the logic cell (LC) 300 are LSB on the upper side and MSB on the lower side. The data described in the lower part of the logic cell (LC) 300 is setting information for the logic cell (LC) 300. The plurality of logic cells (LC) 300 operate as shown in FIG. First, in cycles 1 and 2, the plurality of logic cells (LC) 300 align input data in bit units. In cycle 3, the plurality of logic cells (LC) 300 perform XNOR processing for each bit. In cycle 4, the plurality of logic cells (LC) 300 perform AND processing on the result of cycle 3. In cycle 5, the plurality of logic cells (LC) 300 perform AND processing on the result of cycle 4. In cycle 6, the plurality of logic cells (LC) 300 output a comparison result. As a result, the output is determined in 6 cycles of the internal clock signal 109. When the number of clocks of the internal clock signal 109 is six times the number of clocks of the user clock signal 110, it appears to the user circuit 108 that the comparison process has been completed in one clock.

  As described above, the programmable logic circuit 100 is an aggregate of processor elements 101 that perform a single operation, and each processor element 101 mainly performs a joint operation with an adjacent processor element 101. A plurality of adjacent processor elements 101 can perform one logical processing as one group.

  As described above, the programmable logic circuit 100 according to the first embodiment of the present invention can operate a plurality of processor elements 101 independently or jointly, and simultaneously perform a plurality of types of logic processing in parallel. In addition, it is possible to perform a single logical process jointly.

  In addition, the programmable logic circuit 100 according to the first embodiment of the present invention has the same elements arranged one-dimensionally in a single column, so that it can be flexibly handled according to the mounting scale, and has expandability. high. In addition, the programmable logic circuit 100 according to the first embodiment of the present invention can greatly reduce setting information by limiting data transmission / reception between adjacent processor elements 101, thereby reducing the circuit area. In addition, the cost and power consumption of the LSI to be mounted can be reduced.

  In addition, the programmable logic circuit 100 according to Embodiment 1 of the present invention has a minimum wiring distance from a flip-flop of an arbitrary processor element 101 to a flip-flop of another adjacent processor element 101, regardless of the number of mounted elements. And since it is constant, it becomes possible to raise an operating frequency to the limit, and high-speed operation | movement is attained compared with the conventional programmable logic.

  In addition, since the programmable logic circuit 100 according to Embodiment 1 of the present invention performs processing while changing the function repeatedly on the same circuit, the circuit area can be reduced, and the cost and power consumption of the mounted LSI can be reduced. Can be reduced.

  In the first embodiment of the present invention, the internal clock signal 109 does not necessarily have to be multiplied by the user clock signal 110. For example, by using an appropriate clock changing circuit for the input / output control unit 103, the user can A clock signal that is not synchronized with the clock signal 110 may be used as the internal clock signal.

  In the first embodiment of the present invention, the memory device 102 does not need to exist inside the programmable logic circuit 100 and may be configured to exist outside the programmable logic circuit 101. In the first embodiment of the present invention, the clock generation circuit 107 may be disposed inside the programmable logic circuit 100.

  In the first embodiment of the present invention, a selection circuit such as a multiplexer is inserted between the memory device 102 and the processor element 101 so that the connection between the memory device 102 and each processor element 101 can be changed by setting. Also good. However, in this case, the amount of delay in data processing increases, and in order to maintain the frequency, it is necessary to increase the speed by using a pipeline or the like.

  Further, in the first embodiment of the present invention, each block inside the logic element 200 shown in FIG. 3, the connection between the logic cell 300, the cross-connect switch 301 and the flip-flop 302, and each block and the input bus 105, the output The connection between the bus 106 and the adjacent logic element 200 is not limited to that shown in FIG. 3. For example, a flip-flop is provided between the logic cell 300 and the cross-connect switch 301 to further increase the operating frequency. Also good. In the first embodiment of the present invention, data from the input bus 105 may be input to the logic cell 300 or the flip-flop 302 instead of the cross-connect switch 301. The same applies to the examples shown in FIGS. 15, 19 and 25 described later.

  In the first embodiment of the present invention, each of the plurality of processor elements 101 may not be connected to another processor element 101.

(Embodiment 2)
Next, a second embodiment of the present invention will be described in detail with reference to the drawings. FIG. 14 is a block diagram showing a configuration of a programmable logic circuit according to Embodiment 2 of the present invention. In the second embodiment of the present invention, the same components as those in the first embodiment of the present invention are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 14, the programmable logic circuit 1400 according to the second embodiment of the present invention includes a plurality of processor elements 1401 instead of the plurality of processor elements 101 in the first embodiment of the present invention, and a data bus. 1402 and a data holding memory cell 1403 are added. That is, the programmable logic circuit 1400 according to the second embodiment of the present invention includes a plurality of processor elements 1401, an input / output control unit 103, a plurality of memory devices 102, a control bus 104, an input bus 105, an output bus 106, and a data bus 1402. And a data holding memory cell 1403.

  As shown in FIG. 15, the processor element 1401 has a logic element 1410 instead of the logic element 200 in the first embodiment of the present invention. As shown in FIG. 16, the logic element 1410 is obtained by adding a data bus output control unit 1411 to the logic element 200 according to the first embodiment of the present invention.

  As shown in FIG. 14, a clock generation circuit 107 and a user circuit 108 are connected to the programmable logic circuit 1400. The plurality of processor elements 1401 and the plurality of memory devices 102 are connected on a one-to-one basis. The processor elements 1401 and the memory device 102 connected in one-to-one form a unit logic circuit. The plurality of unit logic circuits are connected in parallel.

  Each of the plurality of processor elements 1401 is arranged one-dimensionally in a row, and is connected to two other processor elements 1401 adjacent in the physical arrangement by a connection line 1401a. That is, the plurality of unit logic circuits having the processor elements 1401 are arranged one-dimensionally in one column, and one unit logic circuit and one unit logic circuit in the plurality of unit logic circuits are arranged. The other unit logic circuits adjacent in physical arrangement are connected by a connection line 1401a.

  The processor element 1401 exchanges data with two other adjacent processor elements 101 using a connection line. The data holding memory cell 1403 is connected to the data bus 1402.

  As illustrated in FIG. 15, the processor element 1401 includes a logic element 1410 and a memory control unit 201.

  As shown in FIG. 16, the logic element 1410 is obtained by adding a data bus output control unit 1411 to the logic element 200 according to the first embodiment of the present invention. That is, the logic element 1410 includes a logic cell 300, a cross-connect switch 301, a flip-flop 302, and a data bus output control unit 1411. The data bus output control unit 1411 is connected to the flip-flop 302, the memory control unit 201, and the data bus 1402. The cross connect switch 301 is connected to the data bus 1402.

  Next, functions of the programmable logic circuit 1400 according to the second embodiment of the present invention will be described in detail with reference to the drawings.

  In FIG. 14, the data bus 1402 receives data being logically processed from the processor element 1401 and holds it in the data holding memory cell 1403. The data held in the data holding memory cell 1403 is input to all the processor elements 1401.

  In FIG. 16, the data bus output control unit 1411 outputs the data from the flip-flop 302 or the high impedance level to the data bus 1402 based on the setting information transferred from the memory control unit 201. Data transmitted to the data bus 1402 is input to the cross-connect switch 301. In the cross-connect switch 301, data input from the data bus 1402 is used for data alignment, duplication, and inversion processing together with other data.

  In this way, each of the plurality of processor elements 1401 can transfer processing data to the processor elements 1401 at a long distance from each other in a short time, so that the processor elements at a long distance are jointly operated. It becomes possible.

  Next, the operation of the programmable logic circuit 1400 according to the second embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 17 shows an example of operation timing of the programmable logic circuit 1400. In the T10 period, the data bus output control unit 1411 outputs part or all of the data from the flip-flop 302 as data 1420 to the data bus 1402 based on the setting information transferred from the memory control unit 201. In the period T11, the data (level) 1421 of the data bus 1402 at the position of the processor element 1401 away from the processor element 1401 that has output the data 1420 is indeterminate. Since the data 1421 of the data bus 1402 at the position has been determined in the period T12, the logic element 200 uses the data 1421 of the data bus 1402 for logical processing from the input bus 105, the internal flip-flop 302 and the adjacent processor element 1401. A logical process is performed based on the setting information input together with the data, and the processed data is held in the flip-flop 302.

  As described above, the logic element 1410 outputs the data being logically processed to the data bus 1402 at an arbitrary timing, and the plurality of logic elements 1410 that operate jointly with the logic element 1410 may use this data for the logical processing. Is possible. Therefore, the programmable logic circuit 1400 uses the data bus 1402 and the data holding memory cell 1403, so that each of the plurality of logic elements 1410 can operate the processor element 1401 at a long distance jointly. Can increase the sex.

  However, it is necessary to set the output timing to the data bus 1402 in each memory device 102 so that data collision on the data bus 1402 does not occur. Further, since the data bus 1402 is a line that spans the plurality of processor elements 1401 as described above, the value may not be determined in one cycle period. For this reason, the data reference timing of the data bus 1402 set in each memory device 102 is set to be, for example, two clocks after a predetermined cycle has elapsed after a certain processor element 1401 outputs to the data bus 1402. There is a need. The setting information is set in each memory device 102 by a user device using the present invention directly or indirectly using a logic synthesis and mapping tool according to the present invention. When the user device performs direct setting, since the user device knows the joint operation method of each processor element 1401, it is set in consideration of the use timing of the data bus 1402 so as to avoid the data collision. It will be. When the synthesis and mapping tool performs the setting, the avoidance of the data collision is normally incorporated in the algorithm of the tool, so that the user apparatus is not aware of it. In this way, depending on the operating frequency, the data bus 1402 can be a bus on the premise that a plurality of cycles are required to determine the value, and thus the operating frequency is not affected.

  The programmable logic circuit 1400 according to the second embodiment of the present invention is not limited to the illustrated example. For example, all the processor elements 1401 may not be connected to the same data bus 1402, for example, It is also possible to connect only every fourth processor element 1401 to the same data bus. Further, in the second embodiment of the present invention, the data holding memory cell 1403 may be configured by other than the memory cell as long as the same function can be realized.

(Embodiment 3)
Next, Embodiment 3 of the present invention will be described in detail with reference to the drawings. FIG. 18 is a block diagram showing a configuration of a main part of the programmable logic circuit according to Embodiment 3 of the present invention. In the third embodiment of the present invention, the same components as those in the second embodiment of the present invention are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 18, the programmable logic circuit 1800 according to the third embodiment of the present invention is the same as the programmable logic circuit 1400 according to the second embodiment of the present invention except that the data bus 1402 is deleted and a wired logic bus circuit is provided. 1810 is added.

  The wired logic bus circuit 1810 includes a wired logic input bus 1811, a wired logic output bus 1812, a data holding memory cell 1403, an inverter 1813, a plurality of transistors 1814, and a discharge controller 1815. The wired logic bus circuit 1810 is arranged on the side of a plurality of processor elements 1401 arranged in a one-dimensional row.

  The drain of transistor 1814 is connected to wired logic input bus 1811. A gate electrode of the transistor 1814 is connected to the processor element 1401. The data holding memory cell 1403 is connected to the wired logic input bus 1811. The data holding memory cell 1403 is connected to the wired logic output bus 1812 via an inverter 1813.

  FIG. 19 shows the configuration of the logic element 1410 of the processor element 1401. The data bus output control unit 1411 is connected to the flip-flop 302, the gate electrode of the transistor 1814, and the discharge control unit 1815. The wired logic output bus 1812 is connected to the cross connect switch 301.

  Next, functions of the programmable logic circuit 1800 according to the third embodiment of the present invention will be described in detail with reference to the drawings.

  In FIG. 18, the discharge control unit 1815 receives discharge control signals from the plurality of processor elements 1401, and outputs a signal obtained by taking a non-OR (NOR) of these discharge control signals to the wired logic input bus 1811. The holding memory cell 1403 is discharged. The wired logic input bus 1811 receives data from the plurality of processor elements 1401 through the transistor 1814. When the data from the processor element 1401 is at a high level, the transistor 1814 is cut off and a high impedance level is output to the wired logic input bus 1811. When the data from the processor element 1401 is at a low level, the transistor 1814 is turned on and a high level is output to the wired logic input bus 1811.

  Data on the wired logic input bus 1811 is held in the data holding memory cell 1403. The data held in the data holding memory cell 1403 is inverted by the inverter 1813 and output to the wired logic output bus 1812. The value of the wired logic output bus 1812 is input to the plurality of processor elements 1401.

  When all the outputs from the processor element 1401 to the wired logic input bus 1811 are at a high level, the wired logic output bus 1812 is at a high level. In this way, data obtained by ANDing the data from the plurality of processor elements 1401 is input to each processor element 1401.

  In FIG. 19, the data bus output control unit 1411 outputs the data from the flip-flop 302 to the transistor 1814 based on the setting information transferred from the memory control unit 201. Similarly, the data bus output control unit 1411 outputs a discharge control signal to the discharge control unit 1815 based on the setting information transferred from the memory control unit 201. The data bus output control unit 1411 outputs data from the flip-flop 302 when performing logical product processing, and outputs a fixed high level when not performing logical product processing.

  Input data from the wired logic output bus 1812 is input to the cross-connect switch 301 and used for data alignment, duplication, and inversion processing together with other data.

  As described above, the programmable logic circuit 1800 uses the wired logic bus circuit 1810 to perform logical operation on information independently processed by the plurality of processor elements 1401 and transfer the information to the processor element 1401 at a long distance. Is possible. Therefore, the programmable logic circuit 1800 can process the information at the time of the joint operation collectively, and can improve the overall processing performance.

  In the data bus 1402 and the wired logic bus circuit 1810, there are always memory cells that hold the bus level. In the wired logic bus circuit 1810, when the output data from all the processor elements 1401 is at a high level, the level of the wired logic output bus 1812 becomes the level of the data held last time. When the wired logic bus circuit 1810 is used, it is necessary to discharge the data holding memory cell 1403 before using it. There are several methods for discharging the data holding memory cell 1403. The first method is a method of periodically discharging. As shown in FIG. 18, the second method is a method in which the processor element 1401 using the wired logic bus circuit 1810 outputs a discharge signal based on the setting information, and thereby discharges. Details will be described in the operation of the wired logic bus circuit 1810.

  The operation of the programmable logic circuit 1800 according to the third embodiment of the present invention will be described in detail with reference to the drawings.

  FIG. 20 shows an example of timing for explaining the operation of the programmable logic circuit 1800 according to the third embodiment of the present invention.

  In the period T10, the level 2006 of the wired logic output bus 1812 is held at the level when the previous wired logic output bus 1812 was used. In the period T11, the processor element 1401 outputs the discharge control signal 2000 to the discharge control unit 1815 based on the setting information transferred from the memory control unit 201. As a result, a low level is output from the discharge control unit 1815 to the wired logic input bus 1811.

  In the period T12, the data holding memory cell 1403 is transitioning to the low level, and the level 2006 of the wired logic output bus 1812 is indeterminate. In the period T13, the data holding memory cell 1403 is completely discharged, and the level 2006 of the wired logic output bus 1812 is at a high level. In the T14 period, the data bus output control unit 1411 of each processor element 1401 outputs the data from the flip-flop 302 to the wired logic input bus 1811 based on the setting information transferred from the memory control unit 201. Here, one of the four processor elements (PE) 1401 outputs a low level.

  In the T15 period, the level 2006 of the wired logic output bus 1812 is indeterminate. In T16 period, since the level 2006 of the wired logic output bus 1812 is determined, the logic element 1410 uses the data of the wired logic output bus 1812 for logic processing from the input bus 105, the internal flip-flop 302, and the adjacent processor element 1401. Logical processing is performed based on setting information input together with the data, and the processed data is held in the internal flip-flop 302.

  In this manner, a plurality of logic elements 1410 that operate jointly can output data being logically processed to the wired logic bus circuit 1810 at the same timing, and the wired logic bus circuit 1800 can perform a batch operation process on specific logic. It is.

  At the same time, all logic elements 1410 can use this data for logic processing. However, in each memory device 102, it is necessary to set the output timing to the wired logic input bus 1811 so that the calculation timings of the processor elements 1401 that operate jointly coincide. In addition, since the wired logic bus circuit 1810 is a line that spans a plurality of processor elements 1401 like the data bus 1402, the value may not be determined in one cycle period. Therefore, the timing of data reference of the wired logic output bus 1812 set in each memory device 102 is, for example, two clocks after a certain cycle elapses after a certain processor element 1401 outputs to the wired logic input bus 1811. It is necessary to be.

  Note that in the third embodiment of the present invention, the data holding memory cell 1403 may be formed of a memory cell other than the memory cell as long as the same function can be realized. In the third embodiment of the present invention, the transistor 1814 may exist inside the processor element 1401, and the inverter 1404 is not necessarily required.

  In Embodiment 3 of the present invention, as long as it can be realized as wired logic, applied logic is not limited to logical product, and for example, logical sum may be applied. Further, in the third embodiment of the present invention, the discharge control unit 1815 may not operate under the control from the processor element 1401, for example, it may be controlled by counting the number of clocks of the clock signal with an internal counter. Good.

(Embodiment 4)
Next, a fourth embodiment of the present invention will be described in detail with reference to the drawings. FIG. 21 is a block diagram showing the configuration of the main part of the programmable logic circuit according to Embodiment 4 of the present invention. In the fourth embodiment of the present invention, the same components as those in the first embodiment of the present invention are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 21, the programmable logic circuit 2100 according to the fourth embodiment of the present invention includes a multiport memory device 2101 instead of the memory device 102 in the first embodiment of the present invention.

  The multi-port memory device 2101 is a memory device having a single or a plurality of write ports and a plurality of read ports. The multi-port memory device 2101 in FIG. 21 has one write port and four read ports. In the example shown in FIG. 21, four processor elements 101-1 to 101-4 are connected to one multiport memory device 2101. Each of the processor elements 101-1 to 101-4 has the same configuration as the processor element 101.

  Next, a programmable logic circuit 2100 according to Embodiment 4 of the present invention will be described in detail with reference to the drawings. In the multi-port memory device 2101, each read port can read different address spaces at the same time, and can read the same address at the same timing.

  In the example shown in FIG. 21, the four processor elements 101-1 to 101-4 can simultaneously read the setting information of the multiport memory device 2101. In addition, as described above, each of the processor elements 101-1 to 101-4 acquires the storage location address of its own setting information at the time of initialization. Therefore, even when the multiport memory device 2101 is applied, Can be recognized.

  As described above, the programmable logic circuit 2100 can use the multiport memory device 2101 to hold the setting information of the processor element with a small amount of setting information and the processor element with a large amount of setting information in the same multiport memory device 2101. Therefore, since the free space of the multi-port memory device 2101 can be used effectively, the mounting efficiency is improved.

  Next, the function of the programmable logic circuit 2100 according to the fourth embodiment of the present invention will be described using a specific example.

  In FIG. 22, it is assumed that the processor elements 101-1 to 101-4 perform independent processing. In FIG. 22, the setting information amount of the processor element 101-1 is 5 kbit (kilobit), the setting information amount of the processor element 101-2 is 10 kbit (kilobit), and the setting information amount of the processor element 101-3 is 100 kbit (kilobit). And the setting information amount of the processor element 101-4 is 200 kbits (kilobits). In this case, if the multi-port memory device 2101 is not applied, each memory device 102 needs to have a capacity of at least 200 kbit (kilobit). Therefore, a total capacity of 900 kbit (kilobit) is required for the four processor elements 101-1 to 101-4. On the other hand, when the multiport memory device 2101 is used, the minimum required capacity of the multiport memory device 2101 is 315 kbits (kilobits), so that the memory space can be used effectively. Each of the processor elements 101-1 to 101-4 acquires and holds addresses A, B, C, and D at the time of initialization, and reads setting information from the respective addresses at the time of activation. As described above, the programmable logic circuit 2100 according to the fourth embodiment of the present invention can effectively use the free space of the memory device by applying the multi-port memory device 2101.

  In the fourth embodiment of the present invention, the multi-port memory device 2101 does not have to be four ports, and a multi-port memory device and a single-port memory device may be combined.

(Embodiment 5)
Next, a fifth embodiment of the present invention will be described in detail with reference to the drawings. FIG. 23 is a block diagram showing a configuration of a main part of the programmable logic circuit according to the fifth embodiment of the present invention. In the fifth embodiment of the present invention, the same components as those in the first embodiment of the present invention are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 23, the programmable logic circuit 2300 according to the fifth embodiment of the present invention includes a plurality of processor elements 101-1 to 101-M and a plurality of multiport memory devices 2101-1 connected thereto. ˜2101-N, and the plurality of processor elements 101-1 to 101-M (M> N) are divided into a plurality of groups and perform independent operations for each of the plurality of groups.

  Next, functions of the programmable logic circuit 2300 according to the fifth embodiment of the present invention will be described with reference to the drawings.

  In FIG. 23, the processor elements 101-1, 101-3, 101-6, 101-8 can read the setting information of the multiport memory device 2101-1. The processor elements 101-2, 101-4, 101-5, and 101-7 can read the setting information of the multiport memory device 2101-2. The setting information of the processor elements 101-1, 101-3, 101-6, and 101-8 is stored in the multiport memory device 2101-1. The setting information of the processor elements 101-2, 101-4, 101-5, and 101-7 is stored in the multiport memory device 2101-2.

  As described above, in the programmable logic circuit 2300 according to the fifth embodiment of the present invention, the setting information of the processor element existing at a longer distance is held in the same multiport memory device. Since adjacent processor elements often operate jointly, the amount of memory devices used is often the same. As described above, in the programmable logic circuit 2300 according to the fifth embodiment of the present invention, the wiring between the plurality of processor elements 101-1 to 101-M and the plurality of multiport memory devices 2101-1 to 2101-N is devised. By elaborating, it is possible to hold the setting information of the processor elements that operate independently in the same memory.

  Next, a specific example of the function of the programmable logic circuit 2300 according to the fifth embodiment of the present invention will be described with reference to the drawings.

  In FIG. 23, processor elements 101-1 to 101-3 are group A, processor elements 101-4 to 6 are group B, processor elements 101-7 to 9 are group C, and each of the plurality of groups performs independent processing. Suppose you do.

  At this time, since the processor elements in the same group operate in unison, the same amount of setting information is required. The capacity of each of the multi-port memory devices 2101-1 to 2101 -N is 150 kbit (kilobits), the setting information amount of each of the group A processor elements 101-1 to 10-3 is 5 kbit (kilobits), and the processor element 101- The setting information amount of each of 4 to 6 is 10 kbit (kilobit), and the setting information amount of each of the group C processor elements 101-7 to 9 is 100 kbit (kilobit).

  In this case, if the wiring between the processor elements 101-1 to 9-9 and the multi-port memory devices 2101-1 and 2101-2 is not as shown in FIG. The capacity required for the multi-port memory device 2101-2 is 220 kbit (kilobits). For this reason, in the multiport memory device 2101-2, although the setting information does not fit in the multiport memory device 2101-2, the memory space of 125 kbit (kilobit) becomes empty in the multiport memory device 2101-1.

  On the other hand, when the wiring between the processor elements 101-1 to 9-9 and the multi-port memory devices 2101-1 and 2101-2 is as shown in FIG. 23, the capacity required for the multi-port memory device 2101-1. Is 120 kbit (kilobit), and the capacity required for the multi-port memory device 2101-2 is 125 kbit (kilobit), so that the memory space can be used effectively.

  As described above, the programmable logic circuit 2300 according to the fifth embodiment of the present invention stores the setting information of the processor elements located at a longer distance in the same multi-port memory device, thereby improving the use efficiency of the memory area. be able to.

  In the fifth embodiment of the present invention, the wiring between the plurality of processor elements 101-1 to 101-M and the multiport memory devices 2101-1 to 210-N is not limited to the example shown in FIG. Any configuration is possible as long as the distance processor elements are connected to the same multi-port memory device.

  In the fifth embodiment of the present invention, a selection circuit such as a multiplexer is inserted between a number of processor elements 101-1 to 101-M and multi-port memory devices 2101-1 to 210-N, and a plurality of processor elements are set by setting. The connections between the 101-1 to 101 -M and the multiport memory devices 2101-1 to 210 -N may be changeable. However, in this case, the amount of delay in data processing increases, and in order to maintain the frequency, it is necessary to increase the speed by using a pipeline or the like.

(Embodiment 6)
Next, a sixth embodiment of the present invention will be described in detail with reference to the drawings. FIG. 24 is a block diagram showing the configuration of the main part of the programmable logic circuit according to Embodiment 6 of the present invention. In the sixth embodiment of the present invention, the same components as those in the first embodiment of the present invention are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 24, the programmable logic circuit 2400 according to the sixth embodiment of the present invention includes a plurality of processor elements 2401 instead of the plurality of processor elements 101 in the programmable logic circuit 100 according to the first embodiment of the present invention. And having a static input bus 2402 and a dynamic input bus 2403 instead of the input bus 105. As shown in FIG. 25, each of the logic elements 2411 of the plurality of processor elements 2401 according to the sixth embodiment of the present invention has an input control unit 2412 added to the plurality of processor elements 200 according to the first embodiment of the present invention. Do it.

  In FIG. 24, the static input bus 2402 is connected to the input / output control unit 103 and the processor element 2401. The dynamic input bus 2403 is connected to the input / output control unit 103 and the processor element 2401. In FIG. 25, the static input bus 2402 and the dynamic input bus 2403 are connected to the input control unit 2412. The input control unit 2412 is connected to the logic cell 300, the cross connect switch 301, and the memory control unit 201.

  Next, functions of the programmable logic circuit 2400 according to the sixth embodiment of the present invention will be described with reference to the drawings.

  In FIG. 24, the input / output control unit 103 receives a start signal synchronized with the user clock signal 110 and data for logic processing from the user circuit 108, and holds this data therein. The input / output control unit 103 holds data until the next activation signal is input. The input / output control unit 103 outputs the held data to the static input bus 2402 in synchronization with the internal clock signal 109. The input / output control unit 103 receives only data for logical processing synchronized with the user clock signal 110 from the user circuit 108 and outputs the data to the dynamic input bus 2403 in synchronization with the internal clock signal 109. The input / output control unit 103 holds data for each user clock signal 110. The static input bus 2402 and the dynamic input bus 2403 output data received from the input / output control unit 103 to the processor element 2401.

  In FIG. 25, the input control unit 2412 sends either input data from the static input bus 2402 or the dynamic input bus 2403 to the cross-connect switch 301 based on the setting information transferred from the memory control unit 201. Output.

  As described above, each of the processor elements 2401 can selectively sample data, and thus can correspond to a plurality of processing forms. For example, the programmable logic circuit 2400 can be realized by appropriately intermingling two controls, and the versatility of processing can be improved.

  In the sixth embodiment of the present invention, the static input bus 2402 and the dynamic input bus 2403 may not be connected to all the processor elements 2401. In the sixth embodiment of the present invention, the static input bus 2402 and the dynamic input bus 2403 may be directly connected to the cross-connect switch 301 without using the input control unit 2412.

(Embodiment 7)
Next, a seventh embodiment of the present invention will be described in detail with reference to the drawings. FIG. 26 is a block diagram showing the configuration of the main part of the programmable logic circuit according to Embodiment 7 of the present invention. In the seventh embodiment of the present invention, the same components as those in the first embodiment of the present invention are denoted by the same reference numerals, and the description thereof is omitted.

  As shown in FIG. 26, the programmable logic circuit 2600 according to the seventh embodiment of the present invention is different from the input / output control unit 103 in the programmable logic circuit 100 according to the first embodiment of the present invention. Have

  The input / output control unit 2601 includes a first group of flip-flops (FF) 2611 connected to each of the plurality of processor elements 101, and a second group connected to the first group of flip-flops 2611 and the user circuit 108. Flip-flop (FF) 2612.

  In FIG. 26, the processor element 101 supplies the logic processing result data 2621 and the enable signal 2622 to the flip-flop 2611 of the input / output control unit 2610.

  Next, functions of the programmable logic circuit 2600 according to Embodiment 7 of the present invention will be described with reference to the drawings.

  In FIG. 26, each of the processor elements 101 outputs logical operation processing result data 2621 and an enable signal 2622 to the flip-flop 2611 based on the setting information of the memory device 102. The flip-flop 2611 holds logical processing result data 2621 at the input timing of the enable signal 2622. The flip-flop 2611 holds data in synchronization with the internal clock signal 109.

  The flip-flop 2612 holds data for each cycle in synchronization with the data from the flip-flop 2611 in synchronization with the user clock signal 110. In this configuration, the internal clock signal 109 is a half-phase shifted clock signal of the clock signal obtained by multiplying the user clock signal 110. In FIG. 27, the enable signal 2622 is output by the memory control unit 201 based on the setting information. The logic processing result data 2621 is an output of a flip-flop inside the logic element 200.

  Next, an example of improving processing performance using the programmable logic circuit 2600 according to Embodiment 7 of the present invention will be described with reference to the drawings.

  FIG. 28 is a diagram for explaining an example of improving the processing performance using the programmable logic circuit 2600 according to the seventh embodiment of the present invention.

  In FIG. 28, there are circuits A, B, C, D, and E, and each of the circuits A, B, C, D, and E is a circuit that can be realized by using one processor element 101. The number of processor elements 101 mounted on the LSI is five.

  In FIG. 28, circuits A, B, and C are circuits that receive processing data at the beginning of clock cycle 1 and require externally processed data at a timing 7 clocks after internal clock signal 109. To do. The circuits D and E are circuits that start processing from clock cycle 3. When processing is performed by the single processor element 101, the circuits A and B require 2 clocks, the circuit C requires 7 clocks, and the circuits D and E require 10 clocks.

  FIG. 28 (a) shows processing operations when the input / output control unit 2610 according to Embodiment 7 of the present invention is not applied. Since the result is held in the processor element 101 until the prescribed output timing (= cycle 7) after the processing of the circuits A and B is completed, the two processor elements 101 are used only for holding data during this period.

  FIG. 28B shows the processing operation of the programmable logic circuit 2700 according to Embodiment 7 of the present invention. At the beginning of clock cycle 3, the results of circuits A and B are held in input / output control unit 2610, and the processing of circuit D is executed using two processor elements 101 during the data holding period in FIG. Yes. At the same time, the processing of the circuit E is performed using the two remaining processor elements 101. The circuits D and E have completed processing in half the number of cycles because the processing parallelism has increased. As a result, the overall processing performance is improved.

  As described above, the programmable logic circuit 2700 according to the seventh embodiment of the present invention can hold the data of the logical operation processing result in the unit of each processor element 101 in the input / output control unit 2610 at an arbitrary timing. After completing the arithmetic processing, it becomes possible to allocate the idle time until the next start signal input to other logical arithmetic processing.

  The present invention can be applied to a control device for controlling an electronic device.

The block diagram which shows the structure of the programmable logic circuit which concerns on Embodiment 1 of this invention The block diagram which shows the structure of the processor element of the programmable logic circuit which concerns on Embodiment 1 of this invention The block diagram which shows the structure of the logic element of the processor element of the programmable logic circuit which concerns on Embodiment 1 of this invention The figure which shows the structure of the memory device of the programmable logic circuit which concerns on Embodiment 1 of this invention The block diagram for demonstrating the function of the logic cell in the logic element of the processor element of the programmable logic circuit which concerns on Embodiment 1 of this invention The figure for demonstrating operation | movement of the logic cell in the logic element of the processor element of the programmable logic circuit which concerns on Embodiment 1 of this invention. The block diagram which shows the structure of the cross-connect switch of the processor element of the programmable logic circuit concerning Embodiment 1 of this invention The figure for demonstrating operation | movement of the cross-connect switch of the processor element of the programmable logic circuit which concerns on Embodiment 1 of this invention Timing chart for explaining the operation at the time of initialization of the programmable logic circuit according to the first embodiment of the present invention. FIG. 3 is a timing chart for explaining operations at the time of start-up and data processing of the programmable logic circuit according to the first embodiment of the present invention; The figure for demonstrating operation | movement of the logic cell in the logic element of the processor element of the programmable logic circuit which concerns on Embodiment 1 of this invention. The figure which expanded the operation | movement of the processor element at the time-axis direction at the time of mapping a 4-bit comparison circuit with the programmable logic circuit which concerns on Embodiment 1 of this invention FIG. 3 is a circuit diagram showing a 4-bit comparison circuit formed by a processor element when a 4-bit comparison circuit is mapped in the programmable logic circuit according to the first embodiment of the present invention; The block diagram which shows the structure of the programmable logic circuit which concerns on Embodiment 2 of this invention The block diagram which shows the structure of the processor element of the programmable logic circuit which concerns on Embodiment 2 of this invention. The block diagram which shows the structure of the logic element of the processor element of the programmable logic circuit concerning Embodiment 2 of this invention Timing chart for explaining the operation of the programmable logic circuit according to the second embodiment of the present invention The block diagram which shows the structure of the programmable logic circuit which concerns on Embodiment 3 of this invention. The block diagram which shows the structure of the logic element of the processor element of the programmable logic circuit which concerns on Embodiment 3 of this invention. Timing chart for explaining the operation of the programmable logic circuit according to the third embodiment of the present invention The block diagram which shows the structure of the programmable logic circuit which concerns on Embodiment 4 of this invention The figure for demonstrating the structural example of the multiport memory device of the programmable logic circuit which concerns on Embodiment 4 of this invention. The block diagram which shows the structure of the programmable logic circuit which concerns on Embodiment 5 of this invention. A block diagram showing composition of a programmable logic circuit concerning Embodiment 6 of the present invention. The block diagram which shows the structure of the logic element of the processor element of the programmable logic circuit concerning Embodiment 6 of this invention The block diagram which shows the structure of the programmable logic circuit based on Embodiment 7 of this invention The block diagram which shows the structure of the processor element of the programmable logic circuit based on Embodiment 7 of this invention (A) The figure for demonstrating the processing operation when the input / output control part which concerns on Embodiment 7 of this invention is not applied, (b) The processing operation of the programmable logic circuit which concerns on Embodiment 7 of this invention is demonstrated. Illustration to do

Explanation of symbols

100, 1400, 1800, 2100, 2400, 2600 Programmable logic circuit 101, 1401, 2401 Processor element 101a, 1401a Connection line 102 Memory device 103, 2610 Input / output control unit 104 Control bus 105 Input bus 106 Output bus 200, 1410, 2411 Logic element 201 Memory control unit 300 Logic cell 301 Cross-connect switch 302, 2611, 2612 Flip-flop 1402 Data bus 1403 Data holding memory cell 1411 Data bus output control unit 1810 Wired logic bus circuit 1811 Wired logic input bus 1812 Wired logic output bus 1813 Inverter 1814 Transistor 1815 Discharge controller 2101 Multiport memory Location 2402 static input bus 2403 dynamic input bus 2412 input control unit

Claims (8)

  A plurality of unit logic circuits connected in parallel; input signal control means for supplying an input signal received from the outside to the plurality of unit logic circuits; and an output signal for supplying an output signal of the plurality of unit logic circuits to the outside Each of the plurality of unit logic circuits is capable of changing its function based on the first setting information, and performs predetermined logic operation processing on the input signal to generate data. And data processing means for generating data by performing alignment, duplication and inversion processing of the data from the logic operation means based on the second setting information, and generating the data as the output signal to the output signal control means And storage means for storing the first and second setting information, wherein each of the plurality of unit logic circuits is based on the first and second setting information sequentially read from the storage means. There are the logical operation means and programmable logic circuitry that performs the operation of some or all of the functions are sequentially changed predetermined sequential circuit of the data processing means.   2. The logic operation unit according to claim 1, further comprising: a logic cell capable of changing a function based on the first setting information and generating the data by performing a predetermined logic operation process on the input signal. Programmable logic circuit.   2. The data processing unit includes a cross-connect switch that generates the data by performing alignment, duplication, and inversion processing of the data from the logical operation unit based on the second setting information. The programmable logic circuit according to 2.   4. The programmable logic circuit according to claim 3, wherein the data processing means includes a flip-flop that holds the data from the cross-connect switch and supplies the data to the output signal control means as the output signal.   A plurality of unit logic circuits connected in parallel, one unit logic circuit in the plurality of unit logic circuits, and another unit logic circuit adjacent to the one unit logic circuit in physical arrangement Connecting means for connecting, an input signal control means for supplying an input signal received from outside to the plurality of unit logic circuits, and an output signal control means for supplying output signals of the plurality of unit logic circuits to the outside. Each of the plurality of unit logic circuits can be changed in function based on first setting information, and a predetermined logical operation process is performed on the input signal or data from the other unit logic circuit adjacent thereto. Logical operation means for generating data by performing data alignment, duplication and inversion processing of the data from the logical operation means based on second setting information to generate data as the output signal Data processing means to be provided to the force signal control means, and storage means for storing the first and second setting information, wherein each of the plurality of unit logic circuits sequentially reads from the storage means. A programmable logic circuit that performs predetermined sequential circuit operations by sequentially changing some or all of the functions of the logic operation means and the data processing means based on the first and second setting information.   The logic operation means can change the function based on the first setting information, and performs predetermined logic operation processing on the data from the input signal or the other unit logic circuit adjacent to the data. The programmable logic circuit according to claim 5, further comprising a logic cell that generates   6. The data processing unit includes a cross-connect switch that generates the data by performing alignment, duplication, and inversion processing of the data from the logical operation unit based on the second setting information. 7. The programmable logic circuit according to 6.   8. The programmable logic circuit according to claim 7, wherein the data processing means includes a flip-flop that holds the data from the cross-connect switch and supplies the data to the output signal control means as the output signal.

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