JP2002050176A - Semiconductor device, its refreshing method, memory system, and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a refreshing method for a semiconductor device such as VSRAM. SOLUTION: In a semiconductor device 1, a memory cell array 20 is divided into four blocks, that is, a block (0) 22A, a block (1) 22B, a block (2) 22C and a block (3) 22 D. External access in a block 22 is synchronized with refreshment in residual all other blocks based on an external block signal generated at the outside of the semiconductor device 1.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a semiconductor device for retaining data by refresh, a refresh method thereof, a memory system, and electronic equipment.

[0002]

2. Description of the Related Art One of semiconductor memories is a VSRAM (Vir).
tually Static RAM). The memory cells of the VSRAM are the same as the memory cells of the DRAM,
AM does not need to multiplex column and row addresses. Also, the user can use the VSRAM without considering refresh (transparency of refresh).

[0003]

SUMMARY OF THE INVENTION It is an object of the present invention to provide a semiconductor device which retains data by refresh, a refresh method thereof, a memory system, and an electronic apparatus.

[0004]

(1) A refresh method for a semiconductor device according to the present invention is a refresh method for a semiconductor device having a memory cell array divided into a plurality of blocks, wherein the refresh method is performed outside the semiconductor device. An external access-refresh step of performing an external access in at least one of the blocks and a refresh in at least one of the other blocks based on an external clock signal that is a clock signal to be performed.

According to the present invention, since a refresh is performed in a block to be refreshed during an external access in a block to be externally accessed, the semiconductor device can be operated efficiently. Also, the present invention, for example,
When applied to a portable device, an external clock signal can be input to a semiconductor device even during standby. Therefore, the refresh can be performed by the external clock signal even in the standby state.

At least one block and at least one other block can be arbitrarily determined in the design of a semiconductor device. For example,
At least one said block as one block;
At least one other block may be the remaining blocks except one block. Further, at least one block may be a plurality of blocks.

The external clock signal is, for example, a clock signal generated by a CPU or a clock signal output by a system clock generating circuit.

The refresh in a block means, for example, a refresh of a memory cell in a certain row of the block. The row may be a single row or a plurality of rows. These can be arbitrarily determined in the design of the semiconductor device.

The external access means, for example, reading or writing data from or to a memory cell.

(2) A refresh method for a semiconductor device according to the present invention can be performed as follows.

The external access-refresh step includes a refresh request step of generating a refresh request in each of the blocks based on the external clock signal, and an address of the block to be externally accessed based on the external clock signal. A block address selecting step for selecting a block address; an external access performing step for performing an external access in the block to be externally accessed based on the selection of the external clock signal and the block address; Performing a refresh in the block to be refreshed based on a signal and the refresh request.

(3) A refresh method for a semiconductor device according to the present invention can be performed as follows.

The refresh request step and the block address selection step are synchronized based on the external clock signal.

According to this, when an external access is to be made to a certain block, it is possible to prevent that block from being refreshed.

(4) The method of refreshing a semiconductor device according to the present invention can be performed as follows.

The external access execution step and the refresh execution step are synchronized based on the external clock signal.

According to this, when an external access is to be made to a certain block, it is possible to prevent that block from being refreshed.

(5) The refresh method of the semiconductor device according to the present invention can be performed as follows.

The refresh execution step is included in the block address selection period.

According to this, when an external access is to be performed in a certain block, the block is not being refreshed and the external access is not delayed.

The period of the refresh execution step includes, for example, a refresh execution signal generation period.

(6) The method of refreshing a semiconductor device according to the present invention can be performed as follows.

After the end of the external access in the block to be externally accessed, refresh is performed in the block in which the external access has been completed.

According to this, refresh can be performed in all blocks.

(7) A refresh method for a semiconductor device according to the present invention can be performed as follows.

In the block address selecting step, in an external address signal input to the semiconductor device for external access, a lower part of the address signal is assigned to a block address signal for selecting the block address. .

Since the address signal changes frequently as it goes down, the block to be externally accessed is easily changed when the block address signal is determined as described above. Therefore, according to this, it is possible to prevent a certain block from being continuously accessed externally (that is, the refresh is continuously postponed). As a result, it is possible to increase the reliability of the refresh in all the blocks.

It is desirable to select the block address signals in order from the lowest order of the address signals. This means that, for example, if there are two blocks, the lowest address signal is
For example, when three or four blocks are assigned, the lowermost address signal and the address signal one level higher than the lowermost address are assigned as block address signals. Is five to eight, which means that the lowest address signal, the address signal one level higher than the lowest level, and the address signal two levels higher than the lowest level are assigned as block address signals.

(8) The method of refreshing a semiconductor device according to the present invention can be performed as follows.

The refresh requesting step includes a refresh request for at least one memory cell of each of the blocks. If the memory cells of the block to be externally accessed are not refreshed during the refreshable period, a next refreshable period is performed. And a refresh request step for requesting refresh of the memory cells of each of the blocks again.

According to this, the following effects are obtained. External access may continue in a certain block. As a result, in each block, the refresh of the memory cell for which the refresh request has been made may not be performed in all the blocks during the refreshable period. According to the present invention, in the next refreshable period, in each block, a refresh request for the same memory cell for which the refresh request was made is made again in the previous refreshable period. Therefore, refresh can be ensured in all the memory cells.

Note that at least one memory cell is
For example, it means a memory cell in a certain row of each block.
The row may be a single row or a plurality of rows. These can be arbitrarily determined in the design of the semiconductor device.

The refreshable period is, for example, a period from the generation of a refresh request to the generation of the next refresh request. During a refreshable period, a certain memory cell of each block to be refreshed is refreshed. The refreshable period can be set arbitrarily within a period in which the memory cell can hold data.

(9) The refresh method of the semiconductor device according to the present invention can be performed as follows.

If the memory cells of each block are refreshed during the refreshable period, a step of requesting a refresh of at least one other memory cell of each block during the next refreshable period is provided.

The at least one other memory cell means, for example, a memory cell in a row different from a row in each block described above, and can be arbitrarily determined in the design of a semiconductor device. For example, when one row is the n-th row of the block, a different row is the (n + 1) -th row of the block.

(10) The method of refreshing a semiconductor device according to the present invention can be performed as follows.

The semiconductor device is a VSRAM (virtual)
ly Static RAM).

(11) A semiconductor device according to the present invention includes a memory cell array divided into a plurality of blocks, an input section to which an external clock signal which is a clock signal generated outside the semiconductor device is input, and an external clock. A synchronization circuit for synchronizing external access in at least one of the blocks and refresh in at least one of the other blocks based on a signal.

According to the present invention, the same thing as described in (1) can be said. The input unit includes, for example, CL
There is a K (clock) buffer.

(12) The semiconductor device according to the present invention can be configured as follows.

The synchronizing circuit is provided corresponding to each of the blocks and a block address signal generating circuit for generating a block address signal which is an address of the block to be externally accessed. A plurality of refresh request signal generating circuits and a refresh execution signal or an external access execution signal in each of the blocks based on at least one of a block address signal and a refresh request signal. And a plurality of block controls.

The block address signal generating circuit can be included in, for example, an address buffer to which an external address signal for external access is input.

(13) The semiconductor device according to the present invention can be operated as follows.

The block control corresponding to the block to be externally accessed is based on a block address signal.
An external access execution signal for performing an external access is generated, and the block control corresponding to the block to be refreshed generates a refresh execution signal for performing a refresh in the block to be refreshed based on a refresh request signal. I do.

(14) The semiconductor device according to the present invention can be configured as follows.

An address buffer including the block signal generating circuit, to which an external address signal for external access is inputted, wherein the block address signal is
The lower order is assigned among the address signals.

According to this, the same thing as described in (7) can be said.

(15) The semiconductor device according to the present invention can be configured as follows.

In each of the blocks, a determination circuit for determining at least one memory cell to be refreshed, and a circuit for determining that the memory cells in at least one of the blocks have not been refreshed by an external access during a refreshable period. A judgment circuit for judging, and a re-decision circuit for re-deciding the refresh of the memory cells of each block in a next refreshable period based on the judgment of the judgment circuit.

According to this, the same thing as described in (8) can be said. The determining circuit includes, for example, a refresh counter. The determination circuit includes, for example, a refresh counter control. Again, the decision circuit includes, for example, a refresh counter.

(16) The semiconductor device according to the present invention can be configured as follows.

Each of the blocks is provided with another determining circuit for determining at least one other memory cell to be refreshed in each of the blocks when the memory cells of each of the blocks are refreshed during the refreshable period.

Another determination circuit is, for example, a refresh counter.

(17) The semiconductor device according to the present invention can be configured as follows.

The semiconductor device comprises a VSRAM (virtual)
ly Static RAM).

(18) The memory system according to the present invention
The semiconductor device according to any one of the above (1) to (17) is provided.

(19) An electronic apparatus according to the present invention includes the semiconductor device according to any one of (1) to (17).

[0059]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments of the present invention will be specifically described below with reference to the drawings. In the present embodiment, the present invention is applied to a VSRAM.

[Structure of Semiconductor Device] First, the structure of the present embodiment will be described. FIG. 1 is a circuit block diagram of a semiconductor device 1 according to the present embodiment. The semiconductor device 1 includes a data input / output buffer 10, a memory cell array 20,
(Clock) buffer 80 and address buffer 60
And.

The data input / output buffer 10 inputs and outputs 16-bit data (I / O _{0 to} I / O ₁₅ ).

In the memory cell array 20, a plurality of memory cells are arranged in an array. The memory cell includes an access transistor that is an n-type MOS transistor and a capacitor that stores data. The memory cell array 20 has four blocks 22, namely, block (0) 22A, block (1) 22B, and block (2).
22C and a block (3) 22D. In the present invention, the memory cell array 20 only needs to be divided into two or more blocks. The number of blocks may be odd or even.

Each block 22 includes, for each row of memory cells, a plurality of word lines for selecting each memory cell, a plurality of bit line pairs intersecting these word lines, and a plurality of word lines. The memory cells provided corresponding to the intersections with these bit line pairs. If the memory cell array 20 has, for example, 16M bits, each block 22 has, for example, 4M bits.

Each block 22 includes a row decoder 24 and a column decoder 26. The word line is selected by the row decoder 24. The bit line pair is selected by the column decoder 26.

An external clock signal, which is a clock signal generated outside the semiconductor device 1, is input to the CLK (clock) buffer 80. The external clock signal is sent from the CPU shown in FIG. The external clock signal is used for synchronizing various signals.

Address signals A _{0 to} A ₁₉ for external access are externally input to address buffer 60 in synchronization with an external clock signal from CLK buffer 80. The address signals A ₀ and A ₁ are the block address signals A
_0, is assigned to the A _1. The block address signal A ₀ ,
The A _1, block 22 is selected for reading or writing is performed. That is, when the block address signals (A ₀ , A ₁ ) are (“L”, “L”), the block (0) 22A is selected, and the block address signal (A ₀ , A ₁ ) becomes (“H”). "," L ") when, the selected block (1) 22B is a block address signal (a _0, a ₁₎ is, (" L "," when the H "), the block (2) 22C is selected When the block address signals (A ₀ , A ₁ ) are (“H”, “H”), the block (3) 22D is selected. The address signal A ₀ is the lowest address signal, and the address signal A ₁ is an address signal one level higher than the lowest.

[0067] address signal A ₂ to A ₇ are allocated to a column address signal A ₂ to A _7. The column address of each block 22 is selected by the column address signals A _{2 to} A ₇ . Address signal A ₈ to A ₁₉ is assigned to a row address signal A ₈ to A _19. The row address signal A ₈ to A _19, the row address of each block 22 is selected. The address signals A _{0 to} A ₁₉ are assigned in the order of the block address signal, the column address signal, and the row address signal.
The order may be different from this. The address buffer 60 will be described later in detail.

The semiconductor device 1 further includes four RF (refresh) request signal generation circuits 50 and an RF (refresh) timing signal generation circuit 70. RF
Timing signal generation circuit 70 includes a ring oscillation circuit and generates an RF timing signal. The RF timing signal is for periodically generating an RF request signal. The timing of generating the RF request signal is set by the RF timing signal.

The number of RF request signal generation circuits 50 is equal to the number of blocks 22. The RF request signal generation circuit 50 includes:
An RF timing signal from the RF timing signal generation circuit 70 and an external clock signal from the CLK buffer 80 are input. From the RF request signal generation circuit 50, the RF
A (refresh) request signal is output. That is, RF
The request signal (0) generation circuit 50A outputs an RF request signal (0), and the RF request signal (1) generation circuit 50B
Outputs an RF request signal (1), an RF request signal (2) is output from the RF request signal (2) generation circuit 50C, and an RF request signal (3) is output from the RF request signal (3) generation circuit 50D.
An F request signal (3) is output.

The semiconductor device 1 further includes a control unit 40. The control unit 40 has the same number of block controls as the number of blocks 22, here, four, ie, block control 40, that is, block (0) control 40 A, block (1) control 40 B, and block (2) control 40 C. , Block (3) control 40D. Each block control has
Block address signals A ₀ and A ₁ are input. The RF request signal (0) is input to the block (0) control 40A, and the block (1) control 40B
Receives an RF request signal (1) and receives a block (2)
The RF request signal (2) is input to the control 40C, and the RF request signal (3) is input to the block (3) control 40D.

Either the external access execution signal or the RF (refresh) execution signal is output from each of the block controls 40A to 40D depending on the selected block 22. An external access execution signal (0) or an RF execution signal (0) is output from the block (0) control 40A, and the block (1) control 40B
Outputs an external access execution signal (1) or an RF execution signal (1), and the block (2) control 40
C outputs an external access execution signal (2) or an RF execution signal (2), and the block (3) control 4
From 0D, an external access execution signal (3) or an RF execution signal (3) is output. Selected block 2
An external access execution signal is output from the block control corresponding to No. 2, and an RF execution signal is output from the other block controls corresponding to the other blocks 22.

For example, when the RF request signals (0) to (3) are generated, the block address signals (A ₀ , A ₁ )
In the case of (“L”, “L”), the block (0) control 40A outputs an external access execution signal (0) so that the block (0) 22A is selected, and the other block controls 40B to 40B. From 40D,
RF execution signals (1) to (3) are output. As a result, data is read or written in the block (0) 22A, and in each of the block (1) 22B, the block (2) 22C, and the block (3) 22D, the refresh of the memory cell in the row to be refreshed is performed. Is made. Block control 40A-4
0D will be described later in detail.

Semiconductor device 1 further includes a row predecoder 30A-30D and an RF (refresh) counter 100.
And. The RF counter 100 has the same configuration as a normal counter. Row predecoders 30A-30
D supplies a signal for driving the word line. The row predecoders 30A to 30D have refresh address signals RFA _{8 to} RF
A ₁₉ and the row address signals A ₈ to A ₁₉ is input. An output signal (external access execution signal (0) or RF execution signal (0)) from the block (0) control 40A is input to the row predecoder 30A, and the block (1) is input to the row predecoder 30B. Control 40
The output signal from B is input, the row predecoder 30C receives the output signal from the block (2) control 40C, and the row predecoder 30D receives the output signal from the block (3) control 40D. You. Row predecoders 30A to 30D will be described later in detail.

The output signal from row predecoder 30A is
The output signal from row predecoder 30A is input to row decoder 24B, the output signal from row predecoder 30C is input to row decoder 24C, and the output signal from row predecoder 30D is input to row decoder 24C. , Are input to the row decoder 24D.

The semiconductor device 1 further includes an RF (refresh) counter control 90. RF request signals (0) to (3) from the RF request signal generation circuit 50 are input to the RF counter control 90. The RF counter control 90 outputs a count-up signal. The count-up signal is input to the RF counter 100. The RF counter control 90 will be described later in detail.

The semiconductor device 1 further includes a CS and ZZ control 110. CS, ZZ control 11
Before describing 0, an operation cycle and a standby cycle will be described. The semiconductor device 1 has an operation cycle and a standby cycle.
In the operation cycle, data can be read or written. In the standby cycle, data cannot be read or written.
Note that refresh is also performed in the standby cycle.

A chip select signal / CS and a snooze signal ZZ are externally input to the CS and ZZ controls 110. When the chip select signal / CS is "L", an operation cycle is started. On the other hand, when the chip select signal / CS is "H", the standby cycle is started. In the standby cycle, the snooze signal ZZ
Is "L", the power is down. As a result, the current consumption of the semiconductor device 1 is minimized. On the other hand, when the snooze signal ZZ is "H" in the standby cycle, the operation is on standby.

The semiconductor device 1 further includes a WE / OE control 120. WE, OE control 12
To 0, a write enable signal / WE and an output enable signal / OE are input.

[Address Buffer] Next, the address buffer 60 will be described in detail with reference to FIGS. FIG. 2 is a circuit block diagram of the address buffer 60 and circuits related thereto. FIG. 3 is a timing chart for explaining the operation of the address buffer 60. Address buffer 60, the number corresponding to the pulse generating circuit and an address signal A ₀ to A _19, i.e., 20
Latch circuits.

The pulse generation circuit detects the rise of the external clock signal from the CLK buffer 80 and generates a pulse. Address signals A _{0 to} A ₁₉ from the outside are input to the respective latch circuits and output in synchronization with the above-mentioned pulses.
That is, block address signals A ₀ and A ₁ , column address signals A _{2 to} A ₇ , and row address signals A _{8 to} A ₁₉ are output.
Note that the pulse generation circuit and the latch circuit that generates the block address signals A ₀ and A ₁ correspond to a block address signal generation circuit.

[Block Control] Next, the control unit 4
The block control of 0 will be described in detail by taking the block (0) control 40A as an example. FIG.
FIG. 9 is a circuit block diagram of a block (0) control 40A and circuits related thereto. First, block (0)
The configuration of the control 40A will be described. The block (0) control 40A includes an external access execution signal (0) generation circuit 42 and an RF execution signal (0) generation circuit 44.
And a delay circuit 46.

External access execution signal (0) generating circuit 42
Receives an external clock signal and block address signals A ₀ and A ₁ from the CLK buffer 80, and outputs an external access execution signal (0). Block (0) 22
When A is selected, the external access execution signal (0) is
This is the output signal of the block (0) control 40A.

The RF execution signal (0) generation circuit 44 includes C
An external clock signal, block address signals A ₀ and A ₁ and an RF request signal (0) are input from the LK buffer 80, and an RF execution signal (0) is output. Block (0)
When 22A is not selected, the RF execution signal (0) becomes the output signal of the block (0) control 40A. The generation of the RF execution signal (0) is controlled by the block address signals (A ₀ , A ₁ ). More specifically, when the block address signals (A ₀ , A ₁ ) are other than (“L”, “L”), that is, when the block (0) 22A is not selected, the RF execution signal (0) generation circuit 44 Outputs an RF execution signal (0). On the other hand, when the block address signals (A ₀ , A ₁ ) are (“L”, “L”), that is, when the block (0) 22A is selected, the RF execution signal (0) generation circuit 44 outputs The execution signal (0) is not output.

The RF execution signal (0) is supplied to the delay circuit 4
6 is also input. The output signal of the delay circuit 46 is input to the clear (CLR) of the RF request signal (0) generation circuit 50A.

Next, block (0) control 40A
Will be described. Block (0) control
40A, a block address signal of (“L”, “L”)
(A ₀, A₁) And RF request signal (0) are input.
You. Synchronous with external clock signal from CLK buffer 80
External access execution signal (0) generation circuit 42
A section access execution signal (0) is output. RF execution signal
(0) The RF request signal (0) is input to the generation circuit 44.
However, the block address signal (A₀, A₁)of
(“L”, “L”) becomes a mask and the RF execution signal
(0) The generation circuit 44 does not generate the RF execution signal (0).
No. Therefore, the block (0) control 40A is
A section access execution signal (0) is output.

On the other hand, block address signals (A ₀ , A ₁ )
Is other than (“L”, “L”), the RF execution signal (0)
Since the RF request signal (0) is input to the generation circuit 44, the RF execution signal (0) is output from the RF execution signal (0) generation circuit 44 in synchronization with the external clock signal from the CLK buffer 80. And the external access execution signal (0)
The generation circuit 42 does not output the external access execution signal (0). Therefore, the block (0) control 40A outputs R
An F execution signal (0) is output. Note that the RF execution signal (0) is also input to the delay circuit 46. Delay circuit 46
Is the time required for refresh (for example, 20 ns to 4
0 ns), a reset signal is output. This reset signal stops the RF request signal (0).

Other Block Controls 40B-40D
Has the same configuration as the block (0) control 40A, and performs the same operation.

[Row Predecoder] Next, the row predecoders 30A to 30D will be described in detail using the row predecoder 30A as an example. FIG. 5 is a circuit block diagram of row predecoder 30A and circuits related thereto. Row predecoder 30A, the number corresponding to the row address signal A ₈ to A _19, that is, 12 of the selected block 32-1～32-
12 is provided. The selection blocks 32-1 to 32-12 select a row address signal or a refresh address signal, respectively.

Each of the selection blocks 32-1 to 32-12 includes switch and latch circuits 34 and 36 and a determination circuit 38, respectively. A row address signal (row address signal A _{8 in the case of the} selection block 32-1) is input to the switch & latch circuit 34. The switch & latch circuit 36 includes
A refresh address signal (refresh address signal RFA _{8 in the case of the} selection block 32-1) from the RF counter 100 is input.

The decision circuit 38 receives a signal from the block (0) control 40A (FIG. 1), that is, either the external access execution signal (0) or the RF execution signal (0). When the determination circuit 38 determines that the external access execution signal (0) has been input to the determination circuit 38, the determination circuit 38 outputs a row address latch signal. The row address latch signal is supplied to the switch & latch circuit 3
4, the row address signal is latched and output by the switch & latch circuit 34. This allows
Row predecoder 30A outputs a row address signal A ₈ to A _19. This is a signal for driving a word line of a row including a memory cell of an address to be externally accessed.

On the other hand, the judgment circuit 38 supplies the RF execution signal (0)
Is determined by the determination circuit 38, the determination circuit 38 outputs an RF address latch signal. RF
Since the address latch signal is input to the switch & latch circuit 36, the switch & latch circuit 36 latches and outputs the refresh address signal. Thus, the row predecoder 30A outputs the refresh address signal RFA ₈ ~RFA _19. This is a signal for driving the word line of the row to be refreshed.

Row predecoders 30B to 30D have the same configuration as row predecoder 30A, and operate in a similar manner.

[Refresh Operation of Semiconductor Device] Reading and writing of data in the semiconductor device 1 are the same as those of a normal static random access memory (SRAM), and a description thereof will be omitted. The refresh operation of the semiconductor device 1 will be described separately for an operation cycle and a standby cycle.

A refresh operation in an operation cycle of the semiconductor device 1 will be described with reference to FIGS. FIG. 6 is a timing chart for describing an operation cycle of semiconductor device 1. The frequency of the external clock signal from the CLK buffer 80 is, for example,
10 MHz to 20 MHz, the cycle is, for example, 50 ns to
100 ns. Chip select signal / CS is "L"
This is the operation cycle. The selection of the block address is started based on the rise of the external clock signal from the CLK buffer 80 (that is, the generation of the pulse described with reference to FIG. 3). In this embodiment,
One cycle of external clock signal (selection period of block 22)
Thus, the selection of a certain block 22 is completed, and a different block 22 or the same block 22 is selected in the next cycle (selection period of the block 22).

At time t ₀ , the RF timing signal becomes “H” (active). When the RF timing signal is at “H”, the signal R is set based on the rise of the first external clock signal (hereinafter referred to as the external clock signal).
F request signal (0) to (3) becomes "H" (active) (time t _1). The selection of the block address of the block (0) is started based on the rise of the external clock signal. Thus, the RF request signal (0)
(3) and the step of selecting the block address of the block (0) are synchronized based on the rise of the external clock signal.

An external access execution signal (0) is generated from the block (0) control 40A based on the selection of the external clock signal and the block (0). That is, the external access execution signal (0) becomes “H” (active). On the other hand, based on the external clock signal and the RF request signals (1) to (3), the remaining block control 40 issues RF execution signals (1) to (3).
(3) occurs. That is, the RF execution signals (1) to
(3) becomes “H” (active). As described above, the external access execution step of the block (0) and the refresh execution step of the blocks (1) to (3) are synchronized based on the rise of the external clock signal.

After time t ₁ , in block (0), a write or read operation is performed on the selected memory cell by the external access execution signal (0). That is, a write or read operation is performed in a memory cell selected by the row decoder 24A and the column decoder 26A.

On the other hand, the remaining blocks are refreshed. This will be described using the block (1) as an example.
In the block (1), a signal for selecting a row to be refreshed is output by the row predecoder 30B according to the RF execution signal (1), and the signal of the n-th row, which is the row to be refreshed, selected by the row decoder 24B. Refresh is performed in the memory cells connected to the word line. In time t _2, the refresh is finished, RF request signal (1) becomes "L". As a result, the RF execution signal (1) becomes “L”.

During the period when the block address is block (0), refresh is postponed in block (0) 22A. When the block address changes from block (0) to another block, refresh is performed in block (0). This will be described in detail. At time t _3, the block address is changed from the block (0) in the block (2). Since the RF request signal (0) is in the “H” (active) state, the block (0) control 4
From 0A, an RF execution signal (0) is generated. That is,
The RF execution signal (0) becomes “H” (active). In block (0) 22A, the RF execution signal (0)
The same row as the row refreshed in each of the other blocks 22 is refreshed in the previous selection period (selection period of block (0)). That is, refresh is performed in the memory cells connected to the word line in the n-th row selected by the row decoder 24A. At time t _4, the refresh is finished, RF request signal (0) is "L". As a result, the RF execution signal (0) becomes “L”.

As described above, the refresh operation of the memory cell selected by the word line of the n-th row in blocks (0) to (3) in the operation cycle is completed.

The word line in the n-th row may mean that the geometrical position of the word line in the n-th row is the same in each block 22. Even if the geometric positions of the word lines are not necessarily the same, it may mean the same row in the address space, that is, the case of the n-th word line in each block 22 as viewed from the control unit 40. .

Next, a refresh operation in a standby cycle of the semiconductor device 1 will be described with reference to FIGS. FIG. 7 is a timing chart illustrating a standby cycle of semiconductor device 1. The chip select signal / CS is "H", which is a standby cycle.

At time T ₀ , the RF timing signal changes to “H”.
(Active). With the RF timing signal at “H”, the RF request signals (0) to (3) become “H” (active) based on the first rise of the external clock CLK (time T ₁ ).

In the standby cycle, none of the blocks (0) to (3) is selected, so that the block controls 40A to 40D output the RF execution signals (0) to (0).
(3) occurs. That is, the RF execution signal (0) to
(3) becomes “H” (active).

After time T ₁ , all blocks 20 are refreshed. Since the refresh operation is the same as described above, the description is omitted. At time T _2, the refresh is finished, RF request signal (0) to (3) becomes "L". As a result, the RF execution signals (0) to (3) become “L”.
Becomes

As described above, the refresh in the memory cell selected by the word line of the n-th row in the blocks (0) to (3) in the standby cycle is completed.

In this embodiment, the refreshable period (in this embodiment, the refreshable period is a period from the rise of a certain refresh request signal to the rise of the next refresh request signal. The refreshable period In the memory cell selected by the word line of the n-th row of each block 22, refresh is performed, and during the next refreshable period, the (n + 1) -th row of each block 22 is refreshed. Is refreshed in the memory cell selected by the word line. When refreshing is performed on the memory cell selected by the word line of the last row (the 4095th row in the present embodiment), the memory cell selected by the word line of the first row (0th row) is refreshed. Refresh is performed. The above series of operations are repeated. Nth
The rows may or may not be at the same geometric location in each block 22.

As shown in FIG. 6, in the present embodiment, during reading or writing (external access) of data in a certain block 22, refreshing is performed in all the remaining blocks other than the certain block 22. The device 1 can be operated efficiently.

In the present embodiment, the reading or writing of data in a certain block 22 and the refresh in all the remaining blocks 22 are synchronized based on an external clock signal. Therefore, when the semiconductor device 1 is applied to, for example, a portable device, an external clock signal can be input to the semiconductor device 1 even during standby. Therefore, the refresh can be performed by the external clock signal even in the standby state.

In the present embodiment, during the selection period of a certain block 22, refresh is started and ended in the memory cells of a certain row of all the remaining blocks 22 (the period from the start to the end of the refresh). Is almost
It is equal to the period during which the refresh execution signal is generated, that is, the period of “H”. ). For this reason, when the selection period of a certain block 22 ends and the selection period of the next block 22 starts, the next block 22 is not in a refreshing state, and the write or read operation is not delayed. The period during which the refresh execution signal is generated is, for example, 20 ns to 40 ns. The block selection period is, for example, 50 ns to 100 ns.

In this embodiment, the block (0) 2
Selection of 2A to block (3) 22D is made by block address signals A ₀ and A ₁ . That is, the lower address of the external address signals A _{0 to} A ₁₉ is assigned to the block address signal. Since the address signal changes frequently as it goes down, the block 2 which is externally accessed
2 is constantly changing. Therefore, when the block address signal is allocated as described above, a certain block 22
, It is possible to prevent refresh from continuing to be postponed. Therefore, the reliability of the refresh in all the blocks 22 can be improved.

[RF Counter Control] As described above, in the present embodiment, refresh is postponed in the block 22 accessed from the outside. In this embodiment, an RF counter control 90 is provided as shown in FIG. 1 in order to ensure refresh in all the blocks 22.

The RF counter control 90 generates a count-up signal in all the blocks 22 after the refresh of the memory cell selected by the word line in the n-th row is completed. This increases one count of the RF counter 100, RF counter 100 outputs the refresh address signal RFA ₈ ~RFA ₁₉ corresponding thereto. Based on this output from the RF counter 100, the row predecoders 30A to 30D supply a signal for driving the word line of the (n + 1) th row.

FIG. 8 is a circuit block diagram of the RF counter control 90. RF counter control 90
Includes a NOR gate 92, a NAND gate 94, a delay circuit 96, and an inverter 98.

The NOR gate 92 receives the RF request signals (0) to (3). The output signal of the NOR gate 92 is input to the NAND gate 94. This includes
There are two routes. One is a path directly connecting the output terminal of the NOR gate 92 to the input terminal 94a of the NAND gate 94. The other is through a delay circuit 96 and an inverter 98, from the output terminal of the NOR gate 92 to NA.
This is a path leading to the input terminal 94b of the ND gate 94. The NAND gate 94 outputs an active-low count-up signal.

The mechanism by which the RF counter control 90 outputs a count-up signal is shown in FIGS.
This will be described with reference to FIG. FIG. 9 is a timing chart of an operation cycle of the semiconductor device 1 during a certain period. The chip select signal / CS is "L", which is an operation cycle.

[0117] at time t ₀ ~ Time semiconductor device 1 until t ₂ operation is the same as that of the operation from time t ₀ ~ time t ₂ of the timing chart shown in FIG. That is, block (1) 22B, block (2) 22C, block (3)
At 22D, the memory cell selected by the n-th row word line is refreshed.

[0118] After completion of block selection period of the address from the time t _1, even in the selection period of the next block address, since the block (0) 22A continues to be selected, block (0) In 22A, the word in the n-th row The memory cell selected by the line is not refreshed (postponement of refresh in a certain refreshable period). Therefore, R
The F request signal (0) remains "H" (active). During this period, since the RF request signal (0) is “H”,
NOR gate 92 outputs an "L" signal. Therefore, while the block (0) 22A continues to be selected, the NAND gate 94 outputs the “H” signal, so that no count-up signal is generated.

[0119] The next RF timing signal is "H" (active) and any time t ₅ made, so continue to select the block (0) 22A, a cycle of the RF timing signal, the count-up signal is not generated. Therefore, the next R
Even in the cycle of the F timing signal, each block 22
Thus, the memory cells selected by the same row, that is, the memory cells selected by the n-th row are refreshed. In detail, after the next RF timing signal is "H" (active) (time t _5), in synchronism with the rising of the external clock signal, RF request signal (1) to (3) is "H" (active ) (Time t ₆ ).

At time t ₆ , since the block (1) 22B is selected, the external access execution signal (1) and the RF execution signals (0), (2), and (3) change to “H” (active). Become. Accordingly, in the block (0) 22A, the block (2) 22C, and the block (3) 22D, the memory cell selected by the word line in the n-th row is refreshed.

At time t ₇ , the block address becomes
Block (1) changes to block (2). Since the RF request signal (1) is in the “H” (active) state,
The execution signal (1) becomes “H” (active). This R
By the F execution signal (1), in the block (1) 22B,
Refresh is performed in a memory cell selected by the word line in the n-th row. Then, after a predetermined time has elapsed, the refresh is finished, RF request signal (1) is is set to "L" (a time t _8). As a result, the RF execution signal (1) becomes “L”. As described above, the refresh in the memory cell selected by the word line in the n-th row in the blocks (0) to (3) is completed.

At time t ₈ , all RF request signals (0) to (3) become “L”.
Outputs a signal “H”. NAND gate 94
Is immediately input to the input terminal 94a.
Since “H” is being continuously input to the input terminal 94 b, a count-up signal of “L” (active low) is output from the NAND gate 94 (time t ₉ ).
The “H” signal output from the NOR gate 92 is
Since the signal passes through the delay circuit 96 and becomes an "L" signal at the inverter 98 and is input to the input terminal 94b, the output of the NAND gate 94 immediately becomes "H".

The RF counter 1 is activated by the count-up signal.
The count value of 00 is incremented by one, and the RF counter 100 outputs a corresponding refresh address signal, that is, an address signal corresponding to the next row to be refreshed. The output from the RF counter 100 causes the row predecoder 30A to which the refresh execution signal has been input.
-30D, the n-th row to be refreshed next
A signal for refreshing a memory cell selected by the +1 row word line is supplied.

As described above, in the present embodiment, the word line of the (n + 1) th row is refreshed until the memory cells selected by the word line of the nth row are refreshed in all the blocks 22 during a certain refreshable period. Is not refreshed in the memory cell selected by. Therefore, refresh can be ensured in the memory cells in all rows.

By the way, the RF counter control 90
Is provided, the refresh capability (the time during which the memory cell can hold data) and the number of refresh cycles (the number of word lines in each block 22. In this embodiment,
(4096 lines), the period of the RF timing signal must be determined. That is, for example, the refresh ability value is 200 ms, and the number of refresh cycles is about 4
Under the condition of 000 times (since the number of word lines is 4096), the period of the RF timing signal is set to 50 μs.

50 μs × 4000 = 200 ms Under this condition, if the refresh is postponed even once,
Data cannot be retained. Therefore, for example, the period of the RF timing signal is set to 45 μs.

45 μs × 4000 = 180 ms (200 ms−180 ms) ÷ 45 μs ≒ 444 times If the period of the RF timing signal is 45 μs, 444
Data can be retained even if the refresh is postponed up to the number of times.

[Application Example of Semiconductor Device to Electronic Apparatus] The semiconductor device 1 can be applied to an electronic apparatus such as a portable apparatus. FIG. 10 is a block diagram of a part of the mobile phone system. An SRAM, a VSRAM, an EEPROM, a keyboard, and an LCD driver are connected to the CPU via a bus line. The LCD driver is connected to a liquid crystal display unit by a bus line.
The VSRAM in FIG. 10 is the semiconductor device 1. VSRA
M constitutes a memory system connected to the CPU.

FIG. 11 is a perspective view of a portable telephone 600 provided with the portable telephone system shown in FIG. The mobile phone 600 includes a keyboard 612, a liquid crystal display 614,
Main unit 61 including earpiece 616 and antenna 618
0, and a cover 620 including a transmitter 622.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram of a semiconductor device according to an embodiment.

FIG. 2 is a circuit block diagram of an address buffer and related circuits.

FIG. 3 is a timing chart for explaining the operation of an address buffer.

FIG. 4 is a circuit block diagram of a block (0) control and a circuit related thereto.

FIG. 5 is a circuit block diagram of a row predecoder and circuits related thereto.

FIG. 6 is a timing chart for explaining an operation cycle of the semiconductor device according to the embodiment.

FIG. 7 is a timing chart for explaining a standby cycle of the semiconductor device according to the embodiment.

FIG. 8 is a circuit block diagram of RF counter control.

FIG. 9 is a timing chart of an operation cycle of the semiconductor device according to the present embodiment during a certain period.

FIG. 10 is a block diagram of a part of a mobile phone system.

11 is a perspective view of a mobile phone provided with the mobile phone system shown in FIG.

[Explanation of symbols]

 Reference Signs List 1 semiconductor device 10 data input / output buffer 20 memory cell array 22 block 22A block (0) 22B block (1) 22C block (2) 22D block (3) 24 row decoder 24A to 24D row decoder 26 column decoder 26A to 26D column decoder 30A -30D Row predecoder 32-1-32-12 Selection block 34 Switch & latch circuit 36 Switch & latch circuit 38 Judgment circuit 40 Control unit 40A Block (0) Control 40B Block (1) Control 40C Block (2) Control 40D Block (3) Control 42 External access execution signal (0) generation circuit 44 RF execution signal (0) generation circuit 46 Delay circuit 50 RF request signal generation circuit 50A RF request signal (0) generation circuit 50B RF request No. (1) generation circuit 50C RF request signal (2) generation circuit 50D RF request signal (3) generation circuit 60 address buffer 70 RF timing signal generation circuit 80 clock 90 RF counter control 92 NOR gate 94 NAND gate 94a, 94b input terminal 96 delay circuit 98 inverter 100 RF counter 110 CS, ZZ control 120 WE, OE control

Claims (19)

[Claims] 1. A method of refreshing a semiconductor device having a memory cell array divided into a plurality of blocks, wherein at least one of the blocks is based on an external clock signal that is a clock signal generated outside the semiconductor device. A method of refreshing a semiconductor device, comprising: an external access-refreshing step of performing an external access and a refresh in at least one other block. 2. The external access-refresh step according to claim 1, wherein the external access-refresh step generates a refresh request in each of the blocks based on the external clock signal; and an external access based on the external clock signal. A block address selecting step of selecting a block address, which is an address of the block to be performed; and an external access for performing an external access in the block to be externally accessed based on the selection of the external clock signal and the block address. Performing, in the block to be refreshed based on the external clock signal and the refresh request,
And a refresh execution step of performing a refresh. 3. The method according to claim 2, wherein the refresh requesting step and the block address selecting step are synchronized based on the external clock signal. 4. The method for refreshing a semiconductor device according to claim 2, wherein the external access execution step and the refresh execution step are synchronized based on the external clock signal. 5. The method of refreshing a semiconductor device according to claim 2, wherein the refreshing step is included during the block address selection period. 6. The refresh method of a semiconductor device according to claim 1, wherein after the external access in the block to be externally accessed is completed, refresh is performed in the block in which the external access has been completed. 7. The block address selecting step according to claim 2, wherein in the block address selecting step, in an external address signal input to the semiconductor device for external access, A method for refreshing a semiconductor device, wherein a method of allocating a block address to a block address signal for selecting a block address. 8. The memory according to claim 2, wherein the refresh request step includes a refresh request for at least one memory cell of each of the blocks, and the memory of the block to be externally accessed during a refreshable period. If the cell is not refreshed,
A refresh method for a semiconductor device, comprising a refresh requesting step of requesting refresh of the memory cells of each block again in a next refreshable period. 9. The device according to claim 8, wherein when the memory cells of each block are refreshed during the refreshable period, at least one other memory cell of each block is refreshed during the next refreshable period. A method of refreshing a semiconductor device, the method including: 10. The semiconductor device according to claim 1, wherein the semiconductor device is a virtual statically static random access memory (VSRAM).
Refresh method for a semiconductor device, including a RAM). 11. A memory cell array divided into a plurality of blocks, an input unit to which an external clock signal which is a clock signal generated outside the semiconductor device is input, and at least one of the blocks based on an external clock signal. And a synchronization circuit for synchronizing the external access in and the refresh in at least one of the other blocks. 12. The synchronization circuit according to claim 11, wherein the synchronization circuit is provided corresponding to each of the blocks, and a block address signal generation circuit that generates a block address signal that is an address of the block to be externally accessed. A plurality of refresh request signal generating circuits for generating a refresh request signal in the block; and A plurality of block controls for generating an execution signal or an external access execution signal. 13. The block control according to claim 12, wherein the block control corresponding to the block to be externally accessed includes an external access execution signal for executing an external access in the block to be externally accessed based on a block address signal. The semiconductor device, wherein the block control corresponding to the block to be refreshed and corresponding to the block to be refreshed generates a refresh execution signal for performing a refresh in the block to be refreshed based on a refresh request signal. 14. An address buffer according to claim 12, further comprising an address buffer including the block signal generating circuit, to which an external address signal for external access is inputted. Assign lower order, semiconductor device. 15. The circuit according to claim 11, wherein a decision circuit for deciding at least one memory cell to be refreshed in each of said blocks, and at least one of said blocks being accessed by an external access during a refreshable period. A determining circuit for determining that the memory cell has not been refreshed; and determining again the refreshing of the memory cell of each of the blocks in a next refreshable period based on the determination of the determining circuit. A semiconductor device, comprising: a circuit; 16. The device according to claim 15, wherein at least one other memory cell to be refreshed is determined in each of the blocks by refreshing the memory cells of each of the blocks during a refreshable period. Semiconductor device, comprising: a determination circuit. 17. The semiconductor device according to claim 11, wherein the semiconductor device is a virtual statically static random access memory (VSRAM).
Semiconductor device including a RAM). 18. A memory system comprising the semiconductor device according to claim 1. 19. An electronic apparatus comprising the semiconductor device according to claim 1. Description: