JP2005057044A - Thin film transistor and its manufacturing method, electro-optical device substrate therefor and its manufacturing method, and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a TFT which has stable element characteristics without causing deterioration or variations in element characteristics and without generating short defects between gate electrodes, and also to provide its manufacturing method. <P>SOLUTION: The method of manufacturing the TFT comprises processes of forming the semiconductor layer of a prescribed thickness from a semiconductor substrate, forming a first gate insulation film 2a on top of a semiconductor film 1a, patterning a multilayer film composed of the semiconductor film 1a and the first gate insulation film 2a into a prescribed shape by photolithography and an etching method, and forming a gate electrode on top of the semiconductor film 1a via the first gate insulation film 2a. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a thin film transistor and a manufacturing method thereof, a substrate for an electro-optical device and a manufacturing method thereof, an electro-optical device, and an electronic apparatus.

2. Description of the Related Art Conventionally, a thin film transistor (Thin Film) that constitutes a peripheral driving circuit and a pixel switching element in an electro-optical device substrate used in an electro-optical device such as a liquid crystal display device from the viewpoints of high speed, low power consumption, and high integration. A technique using single crystal silicon for an active layer of a transistor (hereinafter abbreviated as TFT) is known. Conventionally, SOI (Silicon On Insulator) technology has been used as a technology for forming single crystal silicon on an insulating substrate such as glass or quartz.
By the way, as a procedure for forming the TFT on the substrate, after forming a silicon (Si) layer to be an active layer of the TFT on the substrate, the Si layer is patterned by photolithography and etching, and the Si layer is formed. A general method is to form a gate insulating film thereon and then form a gate electrode (see, for example, Patent Document 1).
JP 2002-261091 A

As described above, in the conventional TFT manufacturing method, the gate insulating film is formed after patterning the Si layer. However, when this method is used, the Si layer and the photoresist are in direct contact during the patterning of the Si layer, and impurities such as heavy metals contained in the photoresist enter the Si layer, so that the TFT device characteristics can be obtained. Deteriorated and the characteristics varied.
Further, when the Si layer is dry-etched, the Si layer is damaged by plasma, which causes deterioration of device characteristics.
Furthermore, when the gate insulating film is formed by thermal oxidation after patterning the Si layer, the shape of the gate insulating film formed on the side wall portion of the Si layer tends to be thicker on the upper side where oxidation tends to proceed and thinner on the lower side. It is in. Due to such a shape, when a conductive film to be a gate electrode is formed next and etching is performed, an etching residue of the conductive film may be generated below the side wall of the Si layer which is a shadow of etching. As a result, a short circuit failure between adjacent gate electrodes occurs.
In addition, the gate insulating film thickness at the upper end face of the Si layer reflects the stress concentration during the thermal oxidation process, as reflected by the shape of the gate insulating film that tends to be thicker and thicker on the upper side where oxidation is likely to proceed. As a result of the formation of an acute angle shape due to the thickness of the gate insulating film at the acute angle portion, the gate insulating film becomes thinner than the other portions, and the withstand voltage of the transistor is reduced.
In addition, the Si layer portion having the acute angle shape described above has many defects due to stress concentration at the time of thermal oxidation treatment, and is likely to cause a parasitic MOS.
As described above, TFTs using single crystal silicon based on SOI technology originally have the advantages of high speed, low power consumption, and high integration. However, as long as a conventional manufacturing method is employed, Had a fear of causing problems.

  The present invention has been made to solve the above-described problems, and has a TFT having stable element characteristics without causing deterioration and variations in element characteristics of the TFT, and further, short circuit failure between the gate electrodes, and the TFT. It is an object to provide a manufacturing method, a substrate for an electro-optical device using the same, and a manufacturing method thereof. It is another object of the present invention to provide an electro-optical device and an electronic apparatus using this type of substrate for an electro-optical device.

In order to achieve the above object, a TFT manufacturing method of the present invention is a TFT manufacturing method using a composite substrate in which a semiconductor substrate and a supporting substrate are bonded together via an insulating layer, and the semiconductor substrate A step of forming a semiconductor layer having a predetermined layer thickness from, a step of forming a first gate insulating film on the semiconductor layer, and a laminated film comprising the semiconductor layer and the first gate insulating film, The method includes a step of patterning into a predetermined shape using photolithography and an etching method, and a step of forming a gate electrode on the semiconductor layer through the first gate insulating film.
In the TFT manufacturing method of the present invention, after forming the first gate insulating film on the semiconductor layer, a laminated film composed of the semiconductor layer and the first gate insulating film is used using the mask formed thereon. Since etching and patterning are performed collectively, the semiconductor layer and the photoresist are not in direct contact. For this reason, impurities such as heavy metals contained in the photoresist are difficult to enter the Si layer, and TFT characteristic deterioration and characteristic variation can be suppressed. Further, since the Si layer is covered with the first gate insulating film during the dry etching of the Si layer, it is difficult for the Si layer to be damaged by plasma, and deterioration of characteristics due to this can be suppressed. Further, after patterning the laminated film, a conductive film to be a gate electrode is formed on the laminated film whose sidewall shape is relatively straight, so that the conductive film is etched below the sidewall of the Si layer as in the prior art. A short circuit failure of the gate electrode can be prevented without causing the remaining. That is, in the TFT manufacturing method of the present invention, the first gate insulating film functions as a protective film for the semiconductor layer by performing photolithography and etching processes in a state where the first gate insulating film is formed on the semiconductor layer. To obtain the above-mentioned actions and effects. However, a special protective film is not formed, but the protective film is used as it is as a gate insulating film, so that the number of manufacturing steps is not increased, and this is a rational method.
In the method of the present invention, the problem of intrusion of impurities in the photoresist and the problem of plasma damage during dry etching occur in the first gate insulating film, but these problems occur in the semiconductor film. Compared with the case where this occurs, the influence on the device characteristics is much less.

In the TFT manufacturing method of the present invention, it is desirable that a silicon oxide film is used as the first gate insulating film, and the first gate insulating film is formed by a thermal oxidation method.
By forming the first gate insulating film by a thermal oxidation method, a high-quality gate insulating film can be obtained, and a TFT having good element characteristics can be manufactured.

The method further includes a step of forming a second gate insulating film so as to cover at least the patterned laminated film after the step of patterning the laminated film, and the first gate insulating film and the semiconductor layer are formed on the semiconductor layer. It is desirable to form a gate electrode through the second gate insulating film.
According to the above configuration, the gate insulating film of the TFT is constituted by the two layers of the first and second gate insulating films, so that the gate leakage current can be reduced and the reliability of the device is further improved. Can be improved. In addition, when the second gate insulating film is formed over the entire surface of the substrate, a step due to the semiconductor layer can be reduced and planarization can be achieved.

The second gate insulating film is preferably formed by chemical vapor deposition (hereinafter abbreviated as CVD).
According to this configuration, the second gate insulating film can be easily formed in a short time using a known method.

The TFT of the present invention includes a semiconductor layer, a first gate insulating film formed only on the upper surface of the semiconductor layer, a second gate insulating film covering the semiconductor layer and the first gate insulating film, And a gate electrode formed above the semiconductor layer with the first gate insulating film and the second gate insulating film interposed therebetween.
According to this configuration, a TFT having stable element characteristics can be obtained without causing deterioration or variation in TFT characteristics or short-circuit failure between gate electrodes. Further, since the gate insulating film is composed of two layers, a highly reliable TFT element can be realized.

The method for manufacturing a substrate for an electro-optical device according to the present invention is a method for manufacturing a substrate for an electro-optical device including a thin film transistor using a composite substrate in which a semiconductor substrate and a support substrate are bonded together via an insulating layer, The TFT manufacturing method of the present invention is used.
According to this configuration, it is possible to obtain an electro-optical device substrate including a TFT having stable element characteristics without causing deterioration or variation in TFT characteristics or short circuit failure between gate electrodes.

In the method for manufacturing a substrate for an electro-optical device according to the present invention, it is desirable to use a silicon oxide film as the second gate insulating film.
It is conceivable that the second gate insulating film is formed on the entire surface of the substrate. In that case, the formation region of the second gate insulating film may be a display region in the electro-optical device. In such a case, if a silicon oxide film is used as the second gate insulating film, the silicon oxide film is transparent, so that problems such as coloration do not occur in the display.

The substrate for an electro-optical device according to the present invention is manufactured by the above-described method for manufacturing a substrate for an electro-optical device according to the present invention.
According to this configuration, it is possible to obtain an electro-optical device substrate including a TFT having stable element characteristics without causing deterioration or variation in TFT characteristics or short circuit failure between gate electrodes.

An electro-optical device according to the present invention includes the substrate for an electro-optical device according to the present invention.
According to this configuration, an electro-optical device with little variation in display characteristics can be obtained.

An electronic apparatus according to the present invention includes the electro-optical device according to the present invention.
According to this configuration, it is possible to realize an electronic device including a display unit with little variation in display characteristics.

Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
[Electro-optical device substrate and electro-optical device]
FIG. 1 is a plan view for explaining the entire configuration of a liquid crystal panel as an example of the electro-optical device of the present invention, and a TFT array substrate is viewed from the side of a counter substrate together with each component formed thereon. It is the top view which showed the state. FIG. 2 is a cross-sectional view taken along the line AA ′ of FIG.

The liquid crystal panel shown in FIGS. 1 and 2 has liquid crystal sealed between a pair of substrates, a TFT array substrate 10 (substrate for an electro-optical device) forming one substrate, and the other disposed opposite to the TFT array substrate 10. And a counter substrate 20 constituting the substrate.
FIG. 1 shows a state in which the TFT array substrate 10 is viewed from the counter substrate 20 side together with the components formed thereon. As shown in FIG. 1, a sealing material 51 is provided on the TFT array substrate 10 along the edge thereof, and a light shielding film 53 as a frame is provided on the inner side of the sealing material 51 in parallel with the sealing material 51. It has been. Moreover, in FIG. 1, the code | symbol 52 has shown the display area. The display area 52 is an area inside the light shielding film 53 as a frame, and is an area used for display on the liquid crystal panel. Reference numeral 54 denotes a non-display area that is an area outside the display area.

In the non-display area 54, the data line driving circuit 101 and the external circuit connection terminal 102 are provided along one side of the TFT array substrate 10, and the scanning line driving circuit 104 is provided along two sides adjacent to the one side. The precharge circuit 103 is provided along the remaining side. Further, a plurality of wirings 105 are provided for connecting the data line driving circuit 101, the precharge circuit 103, the scanning line driving circuit 104, and the external circuit connection terminal 102.
In addition, a conductive material 106 is provided at a position corresponding to the corner portion of the counter substrate 20 for electrical connection between the TFT array substrate 10 and the counter substrate 20. The counter substrate 20 having substantially the same outline as the sealing material 51 is fixed to the TFT array substrate 10 by the sealing material 51.

As shown in FIG. 2, the TFT array substrate 10 is formed on a substrate main body 10A made of a light-transmitting insulating substrate such as quartz and its surface on the liquid crystal layer 50 side, and is made of indium tin oxide (hereinafter referred to as indium tin oxide). The pixel electrode 9a made of a transparent conductive film such as a film (abbreviated as ITO), the pixel switching TFT (switching element) 30 provided in the display region, and an organic film such as a polyimide film, and a rubbing process, etc. And the alignment film 16 subjected to the predetermined alignment process.
On the other hand, the counter substrate 20 includes a substrate body 20A made of quartz, a counter electrode 21 formed on the surface of the liquid crystal layer 50, an alignment film 22, a metal, and the like, and an area other than the opening area of each pixel portion. The light shielding film 23 provided on the light shielding film 53 and the light shielding film 53 as a frame made of the same or different material as the light shielding film 23 are mainly used.
A liquid crystal layer 50 is formed between the TFT array substrate 10 and the counter substrate 20 that are configured as described above and are arranged so that the pixel electrode 9a and the counter electrode 21 face each other.

As shown in FIG. 2, a first interlayer insulating film 12 is provided between the substrate body 10 </ b> A of the TFT array substrate 10 and the plurality of pixel switching TFTs 30. Further, a light shielding film 11 a is formed directly below the semiconductor film 1 a constituting the pixel switching TFT 30 via the first interlayer insulating film 12.
As shown in FIG. 2, the pixel switching TFT 30 has an LDD (Lightly Doped Drain) structure, and a channel region 1a ′ of the semiconductor film 1a in which a channel is formed by an electric field from the scanning line 3a (gate electrode). The gate insulating film 2 that insulates the scanning line 3a from the semiconductor film 1a, the data line 6a, the low concentration source region 1b and the low concentration drain region 1c of the semiconductor film 1a, the high concentration source region 1d and the high concentration drain of the semiconductor film 1a. A region 1e is provided. In the present embodiment, the gate insulating film 2 is a substrate that covers the first gate insulating film 2a formed only on the upper surface of the semiconductor film 1a and the semiconductor film 1a and the first gate insulating film 2a. It consists of two layers with the second gate insulating film 2b formed on the entire surface.

  Further, in this liquid crystal panel, as shown in FIG. 2, the gate insulating film 2 is extended from a position facing the scanning line 3a and used as a dielectric film, and the semiconductor film 1a is extended to form a first storage capacitor. The storage capacitor 70 is configured by using the electrode 1f and a part of the capacitor line 3b opposite to the electrode 1f as a second storage capacitor electrode. The capacitor line 3b and the scanning line 3a are formed of the same polysilicon film or a polysilicon film and a laminated structure of a single metal, an alloy, a metal silicide, etc., and the dielectric film of the storage capacitor 70 and the gate insulation of the pixel switching TFT 30 The film 2 is composed of two identical silicon oxide films. The channel region 1a ', the source region 1d, the drain region 1e, and the first storage capacitor electrode 1f of the pixel switching TFT 30 are composed of the same semiconductor film 1a. These semiconductor films 1a are made of single crystal silicon and are formed on the insulating substrate 10A by SOI technology. As described above, by using single crystal silicon for the semiconductor film 1a which is an active layer of the transistor, high performance and high integration of the transistor can be achieved.

  Further, as shown in FIG. 2, the contact hole 5 leading to the high concentration source region 1d of the pixel switching TFT 30 and the pixel switching TFT 30 are formed on the scanning line 3a, the gate insulating film 2 and the first interlayer insulating film 12. A second interlayer insulating film 4 in which contact holes 8 leading to the high concentration drain region 1e are respectively formed is formed. Further, on the data line 6 a and the second interlayer insulating film 4, a third interlayer insulating film 7 in which a contact hole 8 to the high concentration drain region 1 e of the pixel switching TFT 30 is formed is formed. The pixel electrode 9a is provided on the upper surface of the third interlayer insulating film 7 thus configured.

[Method of manufacturing electro-optical device]
Next, as an example of the method for manufacturing the electro-optical device of the present invention, a method for manufacturing the liquid crystal panel shown in FIGS. 1 and 2 will be described with reference to FIGS.
First, as shown in FIG. 3A, an oxide film 206b is formed on the surface of a single crystal silicon substrate (semiconductor substrate) 206 by thermal oxidation. Note that hydrogen ions (H ⁺ ) are implanted into the single crystal silicon substrate 206 at, for example, an acceleration voltage of 100 keV and a dose of 10 × 10 ¹⁶ / cm ² .

  Next, as shown in FIG. 3B, a quartz substrate (supporting substrate) 10A that is a substrate body of the TFT array substrate 10 is prepared, and a metal film is formed on the surface of the substrate 10A by a sputtering method or the like. The light shielding film 11a is formed by patterning the metal film. Thereafter, the first interlayer insulating film 12 is formed on the quartz substrate 10A including the light shielding film 11a by sputtering, CVD, or the like. As a material of the first interlayer insulating film 12, high insulating glass such as silicon oxide, NSG (non-doped silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), etc. Etc. can be illustrated.

Then, the substrate body 10A and the single crystal silicon substrate 206 are bonded together via the oxide film 206b on the single crystal silicon substrate 206 and the first interlayer insulating film 12 on the quartz substrate 10A. In this bonding step, for example, a method of directly bonding the two substrates 10A and 206 by heat treatment at 300 ° C. for 2 hours can be employed.
Further, in order to further increase the bonding strength, it is necessary to raise the heat treatment temperature to about 450 ° C. However, the thermal expansion coefficient of the substrate body 10A made of quartz or the like and the thermal expansion coefficient of the single crystal silicon substrate 206 are reduced. Since there is a large difference, if the substrate is heated as it is, defects such as cracks are generated in the single crystal silicon substrate, and the quality of the manufactured TFT array substrate 10 may be deteriorated. In order to suppress the occurrence of defects such as cracks, the single crystal silicon substrate 206 once subjected to heat treatment for bonding at 300 ° C. is thinned to about 100 to 150 μm by wet etching or CMP, and then further It is desirable to perform a high temperature heat treatment. For example, etching is performed using a KOH aqueous solution at 80 ° C. so that the thickness of the single crystal silicon substrate 206 becomes 150 μm, and then bonding is performed with the substrate body 10A, followed by heat treatment again at 450 ° C. It is desirable to increase the bonding strength.

Next, as shown in FIG. 3C, the single crystal silicon substrate 206 is attached to the substrate body 10A while leaving the oxide film 206b and the single crystal silicon layer 206a on the bonded surface side of the bonded single crystal silicon substrate 206. Heat treatment for peeling (separating) from the substrate is performed.
This peeling phenomenon of the substrate occurs because silicon bonds are broken at a certain layer near the surface of the single crystal silicon substrate 206 by hydrogen ions introduced into the single crystal silicon substrate 206. The heat treatment here can be performed, for example, by heating the two bonded substrates to 600 ° C. at a rate of temperature increase of 20 ° C. per minute. By this heat treatment, the bonded single crystal silicon substrate 206 is separated from the substrate body 10A, and a semiconductor film 206a made of single crystal silicon is formed on the surface of the substrate body 10A.
Next, as shown in FIG. 3D, a silicon oxide film 60 is formed on the surface of the single crystal silicon layer 206a. At this time, if a thermal oxidation method is used, a silicon oxide film 60 is formed on the upper surface and side surfaces of the single crystal silicon layer 206a. This silicon oxide film 60 will later become the first gate insulating film. However, the silicon oxide film 60 formed by thermal oxidation is a dense and high-quality film, which is preferable for reducing the gate leakage current. The thickness of the silicon oxide film 60 is, for example, 10 to 30 nm, preferably 20 nm.

  Next, as shown in FIG. 4A, the laminated film composed of the single crystal silicon layer 206a and the silicon oxide film 60 is collectively patterned by a photolithography process and an etching process, and an island-shaped semiconductor having a predetermined pattern is formed. A film 1a and a first gate insulating film 2a are formed. In particular, a region where the capacitor line 3b is formed below the data line 6a to be formed later and a region where the capacitor line 3b is formed along the scanning line 3a are extended from the semiconductor film 1a constituting the pixel switching TFT 30. The formed first storage capacitor electrode 1f is formed.

  Next, as shown in FIG. 4B, a silicon oxide film 2b is formed on the entire surface of the substrate including the surface of the patterned laminated film by using the CVD method. This silicon oxide film becomes the second gate insulating film 2b and constitutes the gate insulating film 2 together with the first gate insulating film 2a formed by the thermal oxidation method. The gate insulating film 2 can be composed of only the first gate insulating film 2a, but in this case, only the side surface of the semiconductor film 1a is covered with the gate insulating film 2 when the manufacturing method of the present embodiment is used. There will be no. On the other hand, when the second gate insulating film 2b is formed, the side surface of the semiconductor film 1a is also covered with the gate insulating film 2, which can further contribute to the reduction of the gate leakage current, and the reliability of the TFT element. Improves. Further, since the second gate insulating film 2b is formed over the entire surface of the substrate, the step of the semiconductor film 1a can be reduced. The thickness of the silicon oxide film to be the second gate insulating film 2b is slightly thicker than that of the first gate insulating film 2a, for example, 30 to 90 nm, preferably 60 nm. As a material for the second gate insulating film 2b, a silicon nitride film can be used instead of the silicon oxide film. However, the silicon nitride film has a characteristic that it absorbs in the wavelength region of blue light, and the light transmitted through the silicon nitride film is slightly yellowed. Therefore, when this configuration is applied to a display device such as a liquid crystal panel, it is better to remove the silicon nitride film from the region contributing to display.

Next, as shown in FIG. 4C, a resist film 301 is formed at a position corresponding to the N channel semiconductor film 1a (only the N channel region is shown in the drawing, and the P channel region is not shown). In other words, the P-channel semiconductor film 1a is doped with a dopant 302 of a group V element such as P at a low concentration (for example, P ions at an acceleration voltage of 70 keV and a dose of 2 × 10 ¹¹ / cm ² ).
Next, as shown in FIG. 5A, a resist film is formed at a position corresponding to a P-channel semiconductor film 1a (not shown), and a dopant 303 of a group III element such as B is formed on the N-channel semiconductor film 1a. Is doped at a low concentration (for example, B ions at an acceleration voltage of 35 keV and a dose of 1 × 10 ¹² / cm ² ).

Next, as shown in FIG. 5B, a resist film 305 is formed on the surface of the substrate 10 excluding the end of the channel region 1a ′ of each semiconductor film 1a for each P channel and N channel. The dose of about 1 to 10 times that of the step shown in FIG. 5A for the dopant 306 of the group V element such as P and the N channel of about 1 to 10 times the dose shown in FIG. 4C. A dopant 306 of a group III element such as B is doped.
Next, as shown in FIG. 5 (c), in order to reduce the resistance of the first storage capacitor electrode 1f formed by extending the semiconductor film 1a, a portion other than the first storage capacitor electrode 1f on the surface of the substrate body 10A is formed. A resist film 307 (wider than the scanning line 3a) is formed in a corresponding portion, and using this as a mask, a V group element dopant 308 such as P is deposited at a low concentration (for example, P ions are accelerated by 70 keV). Doping (at a voltage of 3 × 10 ¹⁴ / cm ² dose).

Next, as shown in FIG. 6A, after the polysilicon layer 3 is deposited with a thickness of about 350 nm by a low pressure CVD method or the like, phosphorus (P) is thermally diffused to make the polysilicon layer 3 conductive. . Alternatively, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film 3 may be used. Thereby, the conductivity of the polysilicon layer 3 can be increased. Further, in order to increase the conductivity of the polysilicon layer 3, a single metal, an alloy, a metal silicide or the like containing at least one of Ti, W, Co, and Mo is formed on the polysilicon layer 3 by sputtering, CVD. For example, a layered structure having a thickness of 150 to 200 nm can be formed by a method such as an electron beam heating vapor deposition method.
Next, as shown in FIG. 6B, the capacitor line 3b is formed together with the scanning line 3a having a predetermined pattern as shown in FIG. 2 by a photolithography process, an etching process and the like using a resist mask. After that, the polysilicon remaining on the back surface of the substrate body 10A is removed by etching while covering the surface of the substrate body 10A with a resist film.

Next, as shown in FIG. 6C, a position corresponding to the N-channel semiconductor film 1a is covered with a resist film 309 in order to form a P-channel LDD region of the driving circuit TFT in the semiconductor film 1a. Using the gate electrode as a mask, a dopant 310 of a group III element such as B is doped at a low concentration (for example, BF ₂ ions at an acceleration voltage of 90 keV and a dose of 3 × 10 ¹³ / cm ² ). A low concentration source region and a low concentration drain region are formed.
Subsequently, as shown in FIG. 6D, in order to form the P-channel high concentration source region 1d and the high concentration drain region 1e of the pixel switching TFT 30 and the drive circuit TFT in the semiconductor film 1a, A resist layer is formed on the scanning line 3a corresponding to the P channel with a mask wider than the scanning line 3a (not shown) in a state where the position corresponding to the semiconductor film 1a is covered with the resist film 309. In the state, a dopant 311 of a group III element such as B is doped at a high concentration (for example, BF ₂ ions are accelerated at 90 keV at a dose of 2 × 10 ¹⁵ / cm ² ).

Next, as shown in FIG. 7A, in order to form the N-channel LDD regions of the pixel switching TFT 30 and the drive circuit TFT in the semiconductor film 1a, a position corresponding to the P-channel semiconductor film 1a is resisted. Covering with a film (not shown) and using the scanning line 3a (gate electrode) as a mask, a dopant of a V group element such as P is made at a low concentration (for example, P ions are accelerated by 70 keV, 6 × 10 ¹² / cm ² ) to form an N-channel low concentration source region 1b and a low concentration drain region 1c.
Subsequently, as shown in FIG. 7B, in order to form the N-channel high concentration source region 1d and the high concentration drain region 1e of the pixel switching TFT 30 and the driving circuit TFT in the semiconductor film 1a, the scanning line 3a After the resist 62 is formed on the scanning line 3a corresponding to the N channel with a wider mask, the dopant 61 of a V group element such as P is similarly used at a high concentration (for example, P ions are accelerated at a voltage of 70 keV, 4 Doping is performed at a dose of × 10 ¹⁵ / cm ² . As described above, the TFT 30 is manufactured.

Next, as shown in FIG. 7C, NSG, PSG, BSG, BPSG, etc. are used to cover the capacitor line 3b and the scanning line 3a by using, for example, atmospheric pressure or reduced pressure CVD method or TEOS gas. A second interlayer insulating film 4 made of a silicate glass film, a silicon nitride film, a silicon oxide film or the like is formed. The film thickness of the second interlayer insulating film 4 is preferably about 500 to 1500 nm, and more preferably 800 nm.
Thereafter, an annealing process at about 850 ° C. is performed for about 20 minutes in order to activate the high concentration source region 1d and the high concentration drain region 1e.
Next, as shown in FIG. 7D, the contact hole 5 for the data line is formed by dry etching such as reactive etching, reactive ion beam etching, or wet etching. Further, contact holes for connecting the scanning lines 3 a and the capacitor lines 3 b to wirings (not shown) are also formed in the second interlayer insulating film 4 by the same process as the contact holes 5.

Next, as shown in FIG. 8A, on the second interlayer insulating film 4, a low resistance metal such as light-shielding Al or a metal silicide is formed on the second interlayer insulating film 4 by a sputtering process or the like as a metal film 6 for about 100. Deposit to a thickness of ˜700 nm, preferably about 350 nm.
Further, as shown in FIG. 8B, the metal film 6 is patterned by a photolithography process, an etching process, and the like to form data lines 6a.
Next, as shown in FIG. 8C, a silicate glass film such as NSG, PSG, BSG, or BPSG is used to cover the data line 6a using, for example, atmospheric pressure or reduced pressure CVD or TEOS gas. Then, a third interlayer insulating film 7 made of a silicon nitride film, a silicon oxide film or the like is formed. The film thickness of the third interlayer insulating film 7 is preferably about 500 to 1500 nm, and more preferably 800 nm.

Next, as shown in FIG. 9A, in the pixel switching TFT 30, the contact hole 8 for electrically connecting the pixel electrode 9a and the high concentration drain region 1e is formed by reactive etching or reactive ion beam. It is formed by dry etching such as etching or wet etching.
Next, as shown in FIG. 9B, a transparent conductive thin film 9 such as ITO is deposited on the third interlayer insulating film 7 to a thickness of about 50 to 200 nm by sputtering or the like.
Further, as shown in FIG. 9C, the transparent conductive thin film 9 is patterned by a photolithography process, an etching process, and the like to form a pixel electrode 9a. In the case where the liquid crystal device of the present embodiment is a reflective liquid crystal device, the pixel electrode 9a may be formed from an opaque material having a high reflectance such as Al.
Subsequently, after applying a polyimide alignment film coating solution on the pixel electrode 9a, the alignment film 16 is formed by performing a rubbing process in a predetermined direction so as to have a predetermined pretilt angle. .
As described above, the TFT array substrate (electro-optical device substrate) 10 is manufactured.

Next, a method for manufacturing the counter substrate 20 and a method for manufacturing a liquid crystal panel from the TFT array substrate 10 and the counter substrate 20 will be described.
For the counter substrate 20 shown in FIG. 2, a light transmissive substrate such as a glass substrate is prepared as the substrate body 20A, and a light shielding film 23 and a light shielding film 53 as a peripheral parting are formed on the surface of the substrate body 20A. The light-shielding film 23 and the light-shielding film 53 serving as a peripheral parting are formed through a photolithography process and an etching process after sputtering a metal material such as Cr, Ni, and Al. These light shielding films 23 and 53 may be formed of a material such as resin black in which carbon, Ti, or the like is dispersed in a photoresist in addition to the above metal material.
Thereafter, a counter electrode 21 is formed by depositing a transparent conductive thin film such as ITO on the entire surface of the substrate main body 20A to a thickness of about 50 to 200 nm by sputtering or the like. Further, after an alignment film coating solution such as polyimide is applied to the entire surface of the counter electrode 21, the alignment film 22 is formed by performing a rubbing process in a predetermined direction so as to have a predetermined pretilt angle. To do. The counter substrate 20 is manufactured as described above.

Then, the TFT array substrate 10 and the counter substrate 20 manufactured as described above are bonded to each other with a sealing material 51 so that the alignment films 16 and 22 face each other. A liquid crystal panel having the above-described structure is manufactured by sucking, for example, liquid crystal formed by mixing a plurality of types of nematic liquid crystals into the space to form a liquid crystal layer 50 having a predetermined thickness.
Finally, for example, a TN (Twisted Nematic) mode, a VA (Vertically Aligned) mode, and a PDLC (Polymer Dipersed Liquid) are respectively provided on the side on which the projection light of the counter substrate 20 enters and the side on which the emission light of the TFT array substrate 10 exits. A polarizing film, a retardation film, a polarizing means, and the like are arranged in a predetermined direction according to an operation mode such as a (Crystal) mode or a normally white mode / normally black mode.

As described above, in the TFT manufacturing method of the present embodiment, after the first gate insulating film 2a is formed on the semiconductor film 1a, the stacked film composed of the semiconductor film 1a and the first gate insulating film 2a is formed. The semiconductor film 1a and the photoresist are not in direct contact with each other because they are collectively etched and patterned using the resist mask formed thereon. For this reason, impurities such as heavy metals contained in the photoresist are less likely to enter the semiconductor film 1a, and TFT characteristic deterioration and characteristic variation can be suppressed. Further, since the semiconductor film 1a is covered with the first gate insulating film 2a during the dry etching of the semiconductor film 1a, the semiconductor film 1a is hardly damaged by plasma, and the deterioration of characteristics due to this can be suppressed. Further, after patterning the laminated film, the polysilicon layer 3 to be the scanning line 3a (gate electrode) is formed on the laminated film having a relatively straight side wall shape. A short circuit failure of the gate electrode can be prevented without the etching residue of the conductive film occurring in the lower portion of the side wall.
In addition, the gate insulating film 2 on the upper end surface of the Si layer is stress-concentrated during the thermal oxidation treatment, as reflected by the shape of the gate insulating film 2a that tends to be thicker and thicker on the upper side where oxidation is likely to proceed. As a result, the gate insulating film 2 in the acute angle portion becomes thin, and as a result, the breakdown voltage of the transistor can be prevented from being lowered due to being thinner than the other portions.
In addition, the generation of defects due to the stress concentration during the thermal oxidation process in the semiconductor film 1a having the acute angle shape described above can be suppressed, and the generation of parasitic MOS can also be suppressed.
That is, this method allows the first gate insulating film 2a to function as a protective film for the semiconductor film 1a by performing photolithography and etching processes in a state where the first gate insulating film 2a is formed on the semiconductor film 1a. The above actions and effects are obtained. However, a special protective film is not formed, but the protective film is used as it is as a gate insulating film, so that the number of manufacturing steps is not increased and it is a rational method. Further, since the gate insulating film 2 of the TFT 30 is constituted by the first and second gate insulating films 2a and 2b, the gate leakage current can be sufficiently reduced, and the reliability of the element is further improved. can do.

[Modification of electro-optical device]
As an embodiment of the electro-optical device of the present invention, a liquid crystal panel having a cross-sectional structure shown in FIG. 10 may be used instead of the liquid crystal panel having the cross-sectional structure shown in FIG. The basic structure of the liquid crystal panel shown in FIG. 10 is exactly the same as that shown in FIG. 2. In FIG. 10, the same components as those shown in FIG.
In the liquid crystal panel shown in FIG. 2, a first interlayer insulating film 12 is provided between the substrate body 10 </ b> A of the TFT array substrate 10 and the pixel switching TFT 30, and the first interlayer insulating film is directly below the semiconductor film 1 a constituting the TFT 30. The light shielding film 11 a was formed through 12. On the other hand, in the liquid crystal panel shown in FIG. 10, the light shielding film 11 a is covered with a two-layer insulating film of a silicon oxide film 71 and a silicon nitride film 72, and a first interlayer insulating layer is formed immediately below the semiconductor film 1 a constituting the TFT 30. The light shielding film 11a is formed through the film 12, the silicon nitride film 72, and the silicon oxide film 71.
Also in this structure, a TFT having stable element characteristics can be obtained as in the liquid crystal panel shown in FIG. Further, in the case of this structure, since the light shielding film 11a is covered with two layers of insulating films, it is possible to prevent deterioration due to oxidation of the light shielding film 11a and to obtain a highly reliable TFT array substrate.

[Projection type display device]
Next, a projection type display device that is an example of an electronic apparatus including the electro-optical device according to the above embodiment will be described.
FIG. 11 is a schematic configuration diagram showing an example of the projection display device of the present invention. In FIG. 11, a projection display device 1100 is provided with three liquid crystal panels (electro-optical devices) described above, and the schematic configuration of the optical system of the projection display device used as the RGB liquid crystal devices 962R, 962G, and 962B, respectively. The figure is shown. A light source device (light source) 920 and a uniform illumination optical system 923 are employed in the optical system of the projection display device of this example. The projection display device includes a color separation optical system 924 as color separation means for separating the light beam W emitted from the uniform illumination optical system 923 into red (R), green (G), and blue (B); The three light valves 925R, 925G, and 925B as modulation means for modulating the respective color light beams R, G, and B and the color synthesis prism 910 as color synthesis means for recombining the modulated color light beams were combined. A projection lens unit 906 is provided as a projection optical system for enlarging and projecting a light beam on the surface of the projection surface 100. Further, a light guide system 927 for guiding the blue light beam B to the corresponding light valve 925B is also provided.

  The uniform illumination optical system 923 includes two lens plates 921 and 922 and a reflection mirror 931, and the two lens plates 921 and 922 are arranged to be orthogonal to each other with the reflection mirror 931 interposed therebetween. The two lens plates 921 and 922 of the uniform illumination optical system 923 each include a plurality of rectangular lenses arranged in a matrix. The light beam emitted from the light source device 920 is divided into a plurality of partial light beams by the rectangular lens of the first lens plate 921. These partial light beams are superimposed in the vicinity of the three light valves 925R, 925G, and 925B by the rectangular lens of the second lens plate 922. Therefore, by using the uniform illumination optical system 923, even when the light source device 920 has a non-uniform illuminance distribution in the cross section of the emitted light beam, the three light valves 925R, 925G, and 925B can be uniformly illuminated. It can be illuminated.

Each color separation optical system 924 includes a blue-green reflecting dichroic mirror 941, a green reflecting dichroic mirror 942, and a reflecting mirror 943. First, in the blue-green reflecting dichroic mirror 941, the blue light beam B and the green light beam G included in the light beam W are reflected at right angles and directed toward the green reflecting dichroic mirror 942. The red light beam R passes through the mirror 941, is reflected at a right angle by the rear reflecting mirror 943, and is emitted from the emission unit 944 of the red light beam R to the color synthesis prism 910 side.
Next, in the green reflection dichroic mirror 942, only the green light beam G out of the blue and green light beams B and G reflected by the blue-green reflection dichroic mirror 941 is reflected at right angles, and the green light beam G is emitted from the emitting portion 945. The light is emitted to the side of the combining optical system. The blue light beam B that has passed through the green reflecting dichroic mirror 942 is emitted from the emission part 946 of the blue light beam B to the light guide system 927 side. In this example, the distances from the light beam W emission part of the uniform illumination optical element to the color light emission parts 944, 945, and 946 in the color separation optical system 924 are set to be substantially equal.

Condensing lenses 951 and 952 are disposed on the emission side of the emission portions 944 and 945 for the red and green light beams R and G of the color separation optical system 924, respectively. Therefore, the red and green light beams R and G emitted from the respective emission portions are incident on these condenser lenses 951 and 952 and are collimated.
The collimated red and green light beams R and G are incident on the light valves 925R and 925G and modulated, and image information corresponding to each color light is added. That is, these liquid crystal devices are subjected to switching control in accordance with image information by a driving unit (not shown), thereby modulating each color light passing therethrough. On the other hand, the blue light beam B is guided to the corresponding light valve 925B via the light guide system 927, where it is similarly modulated according to the image information. The light valves 925R, 925G, and 925B in this example further include incident-side polarization means 960R, 960G, and 960B, emission-side polarization means 961R, 961G, and 961B, and liquid crystal panels 962R and 962G disposed therebetween. , 962B.

The light guide system 927 includes a condensing lens 954 arranged on the emission side of the emission part 946 of the blue light beam B, an incident-side reflection mirror 971, an emission-side reflection mirror 972, and an intermediate lens arranged between these reflection mirrors. 973 and a condenser lens 953 disposed on the front side of the light valve 925B. The blue light beam B emitted from the condenser lens 946 is guided to the liquid crystal device 962B via the light guide system 927 and modulated. The optical path length of each color light beam, that is, the distance from the emission part of the light beam W to each liquid crystal device 962R, 962G, 962B is the longest for the blue light beam B, and therefore, the light amount loss of the blue light beam is the largest. However, the light loss can be suppressed by interposing the light guide system 927.
The color light beams R, G, and B modulated through the light valves 925R, 925G, and 925B are incident on the color synthesis prism 910 and synthesized there. Then, the light synthesized by the color synthesis prism 910 is enlarged and projected onto the surface of the projection surface 100 at a predetermined position via the projection lens unit 906.
Since the projection display device includes the liquid crystal panels (electro-optical devices) 962R, 962G, and 962B of the above-described embodiment as light valves, an electronic device including a display unit with little variation in display characteristics is realized. Can do.

The technical scope of the present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the present invention. For example, in the above embodiment, an insulating material such as glass is used for the substrate 10A. However, the substrate is not necessarily an insulating material, and a substrate made of a semiconductor or a conductive material may be used.
In the above embodiment, the transmissive liquid crystal device is described as an example of the electro-optical device. However, the present invention is applied to various devices such as a reflective liquid crystal device and an electroluminescence display device. Can do.

FIG. 2 is a plan view for explaining the overall configuration of a liquid crystal panel which is an example of the electro-optical device of the present invention, and shows a state in which the TFT array substrate is viewed from the side of the counter substrate together with each component formed thereon. It is a top view. It is A-A 'sectional drawing of FIG. FIG. 4 is a process diagram illustrating a method for manufacturing an electro-optical device. FIG. 4 is a process diagram illustrating a method for manufacturing an electro-optical device. FIG. 4 is a process diagram illustrating a method for manufacturing an electro-optical device. FIG. 4 is a process diagram illustrating a method for manufacturing an electro-optical device. FIG. 4 is a process diagram illustrating a method for manufacturing an electro-optical device. FIG. 4 is a process diagram illustrating a method for manufacturing an electro-optical device. FIG. 4 is a process diagram illustrating a method for manufacturing an electro-optical device. FIG. 6 is a cross-sectional view illustrating a modification of the electro-optical device. It is the schematic block diagram which showed an example of the projection type display apparatus of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1a ... Semiconductor film, 1a '... Channel region, 2 ... Gate insulating film, 2a ... 1st gate insulating film, 2b ... 2nd gate insulating film, 3a ... Gate electrode, 10A ... Quartz substrate, 30 ... TFT (Thin film transistor) , 101, 103, 104 ... peripheral drive circuit, 206 ... single crystal silicon substrate (semiconductor substrate), 962R, 962G, 962B ... liquid crystal panel (electro-optical device)

Claims (10)

A method of manufacturing a thin film transistor using a composite substrate in which a semiconductor substrate and a support substrate are bonded together via an insulating layer,
Forming a semiconductor layer having a predetermined layer thickness from the semiconductor substrate;
Forming a first gate insulating film on the semiconductor layer;
Patterning a laminated film composed of the semiconductor layer and the first gate insulating film into a predetermined shape using photolithography and etching;
And a step of forming a gate electrode on the semiconductor layer through the first gate insulating film.   2. The method of manufacturing a thin film transistor according to claim 1, wherein a silicon oxide film is used as the first gate insulating film, and the first gate insulating film is formed by a thermal oxidation method.   After the step of patterning the laminated film, the method further includes a step of forming a second gate insulating film so as to cover at least the patterned laminated film, and the first gate insulating film and the first gate are formed on the semiconductor layer. 3. The method of manufacturing a thin film transistor according to claim 1, wherein a gate electrode is formed through two gate insulating films.   4. The method of manufacturing a thin film transistor according to claim 3, wherein the second gate insulating film is formed by chemical vapor deposition.   A semiconductor layer; a first gate insulating film formed only on an upper surface of the semiconductor layer; a second gate insulating film covering the semiconductor layer and the first gate insulating film; and above the semiconductor layer A thin film transistor comprising: a gate electrode formed through the first gate insulating film and the second gate insulating film. A method for manufacturing a substrate for an electro-optical device including a thin film transistor using a composite substrate in which a semiconductor substrate and a support substrate are bonded together via an insulating layer,
5. A method for manufacturing a substrate for an electro-optical device, wherein the method for manufacturing a thin film transistor according to claim 1 is used.   7. The method for manufacturing a substrate for an electro-optical device according to claim 6, wherein a silicon oxide film is used as the second gate insulating film.   An electro-optical device substrate manufactured by the method for manufacturing an electro-optical device substrate according to claim 6.   An electro-optical device comprising the electro-optical device substrate according to claim 8. An electronic apparatus comprising the electro-optical device according to claim 9.

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