JP2005056959A - Interposer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interposer that is connected between an integrated circuit element and a connecting-destination wiring board and can reduce the crosstalk among signal via conductors disposed in a matrix. <P>SOLUTION: The interposer 10 has an intermediate coefficient of linear expansion between those of the integrated circuit element 30 and the connecting-destination wiring board 20, and relieves the strains of the circuit element 30 and the wiring board 20 caused by thermal expansion. In the interposer 10, grounding via conductor rows constituted by linearly disposing grounding via conductors are disposed among via conductors which are disposed on the surface of a dielectric layer in a matrix after passing through the dielectric layer in the thickness direction. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention is an interposer using a dielectric for connecting an integrated circuit element to a wiring board.

  2. Description of the Related Art A wiring board using a dielectric material such as ceramic is used as a wiring board on which a semiconductor component such as LSI or IC is mounted, or a circuit element such as a transmission line or a filter is formed inside the board. A plurality of via conductors for signal (electric signal transmission / reception), power supply (DC power supply), ground (electric signal grounding), etc. are formed on such a wiring board, and the characteristic impedance of the signal line is improved. The frequency characteristics are being improved stably. For example, Patent Document 1 proposes a method for matching the characteristic impedance of signal transmission lines formed on both surfaces of a wiring board with the characteristic impedance of signal via conductors. That is, by arranging the ground via conductor adjacent to the signal via conductor connecting the signal transmission lines formed on both surfaces, the characteristic impedance of the signal via conductor is matched with the characteristic impedance of the signal transmission line with high accuracy. This minimizes the deterioration of the signal waveform of the high-speed logic circuit and improves its propagation.

JP-A-6-37416

However, in such a via conductor, when this wiring board is applied to a high-speed logic circuit with a clock frequency of 1 GHz or more, the characteristic impedance Z ₀ in the high-frequency band of the signal via conductor that transmits the signal of the high-speed logic circuit is stabilized. And electromagnetic interference given to adjacent signal via conductors, so-called crosstalk becomes a problem. In particular, high-speed logic circuit, MPU, implement LSI such as a DSP or RAM on the wiring board, the repetition period T _P is T _P ≦ 1 nS, rising, falling time _{t r,} t _f is t _r, t _f ≦ 100pS In the case of transmitting a steep high-speed pulse signal through a wiring board, the frequency band of the high-speed pulse signal is a wide-band high-frequency signal ranging from several hundred MHz to 10 GHz or more including the harmonic signal. There is a considerable impact on the performance of LSI high-speed logic circuits by causing crosstalk in other signal via conductors adjacent to signal via conductors that transmit such high-speed pulse signals (such as noise margin reduction or signal waveform distortion). Is often affected.

  An object of the present invention is to provide an interposer that reduces electromagnetic interference, that is, crosstalk, generated between adjacent signal via conductors when a sharp high-speed pulse signal of a high-speed logic circuit is transmitted.

Means for Solving the Problems and Effects of the Invention

In order to solve the above problems, the present invention has an intermediate linear expansion coefficient between the linear expansion coefficient of an integrated circuit element and the linear expansion coefficient of a connection destination wiring board, and the integrated circuit element and the connection destination wiring board In the interposer for reducing thermal expansion strain,
A first side pad array connecting the integrated circuit elements is formed on the first main surface side of the ceramic dielectric layer,
A second side pad array connected to a connection destination wiring board for transmitting and receiving signals of the integrated circuit element is formed on the second main surface side of the ceramic dielectric layer,
Via conductors that penetrate the ceramic dielectric layer in the thickness direction and are electrically connected to the first side pad array and the second side pad array are arranged in a matrix of a plurality of vertical and horizontal portions,
The via conductor has a signal via conductor and a ground via conductor that are respectively connected to the signal output of the integrated circuit element and the ground, and the ground via conductors arranged so that the axes of the adjacent ground via conductors are positioned on a straight line. The columns constitute at least part of the matrix arrangement,
It is characterized in that crosstalk accompanying coupling between adjacent via conductors is reduced.

In this way, an interposer (for example, a linear expansion coefficient of 7 to 8 × 10 ⁻⁶ / ° C.) having a linear expansion coefficient intermediate between the linear expansion coefficient of the integrated circuit element and the linear expansion coefficient of the connection destination wiring substrate is flip-chip. Of connected wiring boards using integrated circuit elements (for example, linear expansion coefficient 2 to 3 × 10 ⁻⁶ / ° C.) and resin substrates (for example, linear expansion coefficient 15 to 20 × 10 ⁻⁶ / ° C.) The thermal expansion strain between the integrated circuit element and the connection destination wiring board is reduced by being sandwiched therebetween. Specifically, due to the difference in coefficient of linear expansion, relative displacement in the in-plane direction between the terminals is likely to occur between the integrated circuit element and the interposer, and between the interposer and the connection destination wiring board. Therefore, a shearing stress is applied to the solder connection portion between the terminals. In this case, if the plate-like substrate that forms the main part of the interposer is made of a ceramic material having a high Young's modulus, the rigidity of the interposer is increased, and the amount of elastic deformation of the interposer even if there is a difference in linear expansion coefficient. As a result, the shear deformation acting on the solder joint portion is reduced, and problems such as peeling of the connecting portion and disconnection can be prevented.

When the characteristic impedance of the signal via conductor is arranged in a matrix as compared with a single case, the adjacent signal via conductor (hereinafter simply referred to as “target line”) surrounding the target signal via conductor (hereinafter simply referred to as “target line”). It is well known that the characteristic impedance Z ₀ of the target line can be reduced corresponding to the number M) (also referred to as “line”). That is, when the dielectric constant of the filled dielectric is ε _r , the line diameter is d, and the distance between the centers of adjacent lines is S, the characteristic impedance Z ₀ is given as follows. . Z ₀ ≈ {138 / (ε _r ) ^1/2 } {(M + 1) / M} log ₁₀ {S / (M) ^{1 / (M + 1)} d} ----- (201). Therefore, the characteristic impedance Z ₀ can be further reduced by reducing S / d and increasing the number M of adjacent lines. Furthermore, by arranging ground via conductors (via conductors to be connected to the ground of the connected wiring board, that is, grounded) in a matrix, the signal via conductors arranged in a matrix form, the characteristic impedance Z of the target line is distributed. It is possible to further reduce ₀ . Specifically, as shown in FIG. 11A and FIG. 12A, the signal via conductors are formed in rows, and both sides thereof are sandwiched by the ground via conductor rows (hereinafter, this arrangement is referred to as “ The characteristic impedance Z ₀ of each signal via conductor can be further reduced by adopting “signal / ground via conductor multi-line arrangement”. Crosstalk between the outermost adjacent signal via conductor, as its characteristic impedance Z ₀ is small, it is possible to reduce the crosstalk signal V _b (see FIG. 9, the details will be described later). As described above, the signal via conductor is arranged in a matrix and the signal / ground via conductor multi-line arrangement is adopted, so that the characteristic impedance Z ₀ of the signal via conductor can be sufficiently reduced, so that an electric signal is transmitted through the target line. In this case, the crosstalk generated in the adjacent line is reduced in the coupling coefficient γ between the lines (between the signal via conductors), and the near-end crosstalk signal and the far-end crosstalk signal can be reduced. (Details will be described later).

Further, the interposer of the present invention may be configured such that a plurality of signal via conductors are arranged in one row between a pair of adjacent ground via conductor rows. When signal via conductors and ground via conductors are arranged in multiple lines as described above, the characteristic impedance Z ₀ of the target line which is the signal via conductor is sufficiently reduced (see FIG. 11, details will be described later) and coupled. The coefficient γ can be remarkably reduced to about γ ≦ 1/10. As a result, it is possible to reduce the crosstalk to 1/4 or less, which is extremely smaller than when the ground via conductors are not distributed (all via conductors are signal via conductors). It was found from the result of reference).

The interposer of the present invention may be configured such that a plurality of signal via conductors are arranged in two rows between a pair of adjacent ground via conductor rows. When the signal via conductor and the ground via conductor are arranged in multiple lines as described above, the characteristic impedance Z ₀ of the target line that is the signal via conductor is sufficiently reduced (see FIG. 12, details will be described later). The coupling coefficient γ can be reduced to about γ ≦ 1/4. As a result, it is possible to reduce the crosstalk to 1/2 or less compared to the case where the ground via conductors are not distributed (when all via conductors are signal via conductors), analysis and high frequency simulation (details will be described later, see FIG. 14). From the result of. In addition, analyzing the characteristics from another viewpoint of the form of the high-frequency transmission line, a distributed constant line having a structure substantially equivalent to a strip line with the signal via conductor as the internal conductor line and the ground via conductor as the ground conductor is formed. Thus, an electrical environment is formed in which the coupled line (the target line and the observation line) that is the signal via conductor is shielded from the outside by the ground via conductor. For this reason, the characteristic impedance Z ₀ of the coupled line is reduced to greatly reduce crosstalk between the lines, and various noises caused by EMC (Electro Magnetic Compatibility) electromagnetic interference entering from the outside of the interposer are reduced. You can also

Also, the interposer of the present invention is configured to satisfy d <S ≦ 3d, where d is the outer diameter of the cross section perpendicular to the axis of the signal via conductor, and S is the distance between the axes of adjacent signals adjacent to each other. You can also. If configured in this way (which is of course not included because each via conductor is short-circuited at S = d), M = 2 (around the target signal via conductor) in the above equation (201) (2 via conductors are arranged at a distance S, one each on the left and right sides), Z ₀ ≈ 78 / (ε _r ) ^1/2 ------ (202) by applying S = 3d . Now, assuming that the dielectric is alumina and the relative dielectric constant ε _r is ε _r = 9, Z ₀ ≈26 (Ω) ------ (203) from the equation (202). Therefore, in the interposer of the present invention in the range of d <S ≦ 3d ------ (204), the characteristic impedance Z ₀ of each signal via conductor can be reduced to 26 (Ω) or less, and the crosstalk can be reduced. It can be sufficiently reduced.

Hereinafter, the best mode of the present invention will be described with reference to the accompanying drawings. FIG. 1 shows a state in which the interposer 10 of the present invention is mounted on the main substrate 20 and the integrated circuit element 30.
Here, the integrated circuit element 30 is MPU (Micro Processor Unit), DSP (Digital Signal Processor). A Flip Chip or CSP (Chip Size Package) using an LSI such as RAM (Random Access Memory) is shown. Further, the main substrate 20 which is a connection wiring substrate of the interposer 10 is a resin substrate such as epoxy resin, polyimide resin, BT (bismaleimide triazine) resin, PPE (polyphenylene ether) resin, or the above resin and glass fiber or polyimide fiber. It is composed of a substrate using a composite material with organic fibers.

  Next, the structure of the interposer 10 will be briefly described with reference to FIG. (2A) is a cross-sectional view (cross-sectional view seen from the side) of the interposer 10 in the thickness direction, and the structure (cross-sectional view seen from the top) of the FF cross-section is shown in (2B). First, in (2A), the dielectric layer (ceramic dielectric layer) 11 constituting the main part of the interposer 10 has a thickness of 0.45 to 0.75 mm, and the material thereof is alumina or LTCC (named as Low Temperature Cofire Ceramic, borosilicate). A glass ceramic in which an inorganic ceramic filler such as alumina is added to acid glass or lead borosilicate glass in a weight ratio of 40 to 60% is used. A via conductor that passes straight through in the thickness direction of the dielectric layer 11 has a circular cross-sectional shape perpendicular to its axis, and its outer diameter is d. The distance between axes with respect to the nearest via conductor, that is, the pitch is S Are arranged at equal intervals.

Normally, the ground via conductors GV1 and GV2 that are connected to the ground terminal of the integrated circuit element 30 are positioned at both ends of the via conductor array, and the signal via conductors SV1 and SV2 that are respectively connected to the signal output terminals of the integrated circuit element 30 between them. , ------, SV9 is arranged. A first side pad array GPA11, SPA11, SPA12 ----, GPA12 is formed on the first main surface MS1 side of the dielectric layer 11, and a second side pad array GPA21 is formed on the second main surface MS2 side. SPA21, SPA22, ----, and GPA22 are formed, and are connected to the respective counterpart terminals (electrode pads) of the integrated circuit element 30 or the connection destination wiring board 20 through the solder balls (solder bumps) GSB11, GSB21, etc. for connection. Conducted. In order to prevent the solder from spreading when forming the solder balls, dielectric thin films CTF1 and CTF2 are formed on both surfaces (first main surface MS1 and second main surface MS2) of the dielectric layer 11 excluding the pad array portion. Yes. In (2B), which represents the FF cross section of (2A), the via conductors are not only arranged in a matrix (lattice or zigzag), but are also arranged in groups with uneven spacing between the via conductors. Ground via conductors GV1, GV2 --- are arranged in the outer peripheral area of the via conductor matrix MTX, and the signal via conductors SV1, SV2-- Are arranged. For the via conductor matrix MTX composed of the majority of signal via conductors SV, for example, N _G : N _S so that the number N _S of signal via conductors SV and the number N _G of ground via conductors GV are in an optimum ratio. = 1: 2 and a small number of ground via conductors GV are arranged in a row and distributed, and the interposer 10 is configured to reduce crosstalk between the signal via conductors SV.

  When a Si IC chip is applied as the integrated circuit element 30, its thermal expansion coefficient is 2.6 ppm / ° C., and when a resin substrate is applied to the connection wiring board 20, its thermal expansion coefficient is between 15 and 20 ppm / ° C. In order to alleviate the thermal expansion strain, it is preferable that the thermal expansion coefficient of the dielectric layer 11 of the interposer 10 is in the range of 3 to 8 ppm / ° C. The dielectric of the dielectric layer 11 includes a high-temperature fired ceramic (alumina, oxide-based insulating engineering ceramic, non-oxide-based insulating engineering ceramic, etc.) having a firing temperature of 1000 ° C. or higher, and a firing temperature of 700 ° C. to A low-temperature fired ceramic (containing borosilicate glass, silica, or the like) at about 800 ° C. can also be used. As the conductor metal forming the via conductor, a high melting point metal such as tungsten, molybdenum, tantalum and niobium, which does not oxidize or evaporate at a high temperature during firing exceeding 1000 ° C. for high temperature fired ceramics, For low-temperature fired ceramics, copper, silver and gold having a relatively low melting point and excellent conductivity can be used when the co-firing method is employed.

  The manufacturing process of the interposer 10 of the present invention will be briefly described as follows. First, an alumina green sheet is produced using a ceramic green sheet forming technique. Vias (through holes) are drilled, punched or laser processed in this alumina green sheet. Next, a paste containing a conductive metal is printed on the alumina green sheet by using a screen printing apparatus to form a pad array for connection on both sides of the alumina green sheet, and the via is filled in the via. . Then, the alumina green sheet filled with the paste was transferred to a firing furnace and heated to several hundreds of degrees C., whereby the alumina and the metal in the paste were simultaneously sintered to provide the pad array on both surfaces and the through via conductor. The interposer 10 is obtained. In order to prevent solder flow of the pad array, another alumina thin film sheet may be formed by leaving the pad array portions on both surfaces of the alumina green sheet.

  Here, the arrangement of via conductors as viewed from the first main surface MS1 to which the integrated circuit element 30 of the interposer 10 is connected will be described with reference to FIG. The positions of the via conductors are determined according to the arrangement of the electrode terminals of the Flip Chip which is the integrated circuit element 30, and the via conductors are arranged in a staggered lattice pattern. In this embodiment, the spacing between adjacent rows (center-to-center distance) is 230 μm, the spacing between the upper and lower rows is 138 μm, and the distance between the axes between the adjacent via conductors, that is, the pitch S is S = 180 μm. . Since the outer diameter (wire diameter) d of each via conductor is d = 90 μm, S = 2d is optimally arranged in terms of impedance characteristics.

Next, the mutual impedance Z _M associated with the coupling between the adjacent signal via conductors SV and the characteristic impedance Z ₀ generated between the signal via conductor SV and the adjacent ground via conductor row are derived. Prepare for crosstalk analysis. First, the mutual impedance Z _M and the line coupling capacitance C ₁₂ associated with the coupling of the adjacent signal via conductors SV1 and SV2 are given by (101) and (102) shown in FIG. Also, the characteristic impedance of the line (target signal via conductor SV) covered with the ground metal conductor (metal plate) having the interval b above and below the signal via conductor row in which the signal via conductors SV are arranged at equal intervals of the pitch S. As shown in (5A) of FIG. 5, Z ₀ has the same electrical condition as when a plurality of coupled lines are arranged on the strip line, and the characteristic impedance Z ₀ is shown in FIG.
It was found as a result of the analysis of the high-frequency line that it is given by the equation (103) shown in (5B). Furthermore, as shown in FIG. 6 (6A), the signal via conductor rows are arranged in two rows at the top and bottom at a center distance D, and the top and bottom are covered with a ground metal conductor (metal plate) having a distance b. As a result of analysis of the distributed constant line, it was found that the characteristic impedance Z ₀ can be expressed by the equation (104) shown in (6B).

Next, the points of the arrangement conditions, required parameters, and quantitative relational expressions for crosstalk between adjacent signal via conductors SV will be described. 7, 8, 9, and 10 regarding electromagnetic interference between adjacent via conductors, that is, so-called “crosstalk”, considering via conductors as distributed constant lines (hereinafter simply referred to as “lines”). Analyze using In FIG. 7, the parameter causing crosstalk is (7A), the relationship between adjacent lines is (7B), the structure and coupling of adjacent lines is (7C), and the relationship between the basic circuit and crosstalk is (7D). ). Each coupling shown in (7A) (taken from a plane perpendicular to the axis of the line) and each coupling shown in (7C) (taken from a plane parallel to the axis of the line) exist between the lines, especially the coupling capacitance. C ₁₂ and mutual inductance L _M is a major cause resulting in cross-talk. In the basic circuit of (7D), a line 1 for transmitting an electrical signal such as a high-speed clock pulse of several GHz is a “target line”, and a line that receives electromagnetic interference due to an electric field and a magnetic field generated in the target line adjacent to the line 1 2 is an “observation line”. Interference signals are generated at both ends of the observation line 2 and the pulse generator side of the signal source is referred to as a near end crosstalk signal V _b , and the end side of the line 1 is referred to as a far end crosstalk signal V _f . The magnitude of the crosstalk signal, in FIG. 8 (1) and (2) as shown in the formula, mainly of the coupling coefficient γ and the transmission signal between the lines rise time t _r (of the high-speed clock signal pulse The degree of steepness of the leading edge / rear edge, that is, the upper limit frequency of the broadband high frequency determined by the harmonics of the clock signal) and the line length le. This interposer is regarded as a TEM (Transverse Electromagnetic) line (the electric and magnetic fields are formed in a plane perpendicular to the line, and no electric and magnetic fields are generated in the signal traveling direction). The end crosstalk signal _Vb is taken up and the characteristics of the line are analyzed and evaluated.

Next, as a preparation for deriving the coupling coefficient γ, the relational expressions are summarized using FIGS. 9 and 10. The required parameters are arranged in (9A) of FIG. 9, and the coupling coefficient γ is obtained as γ = C ₁₂ / C ₁₁ ≈Z ₀ / Z _M ------ (10) from the expression (3) of FIG. It was. The relationship parameter between the lines for deriving γ obtained by the equation (10) is shown in (9B), the relationship between the coupling capacitance C ₁₂ between the lines and the mutual impedance Z _M , and the characteristic impedance Z _{0 of the} target line (usually these FIG. 10 summarizes the relationship between the ground impedance C ₁₁ ) and the ground capacitance C ₁₁ . The mutual impedance Z _M between the lines is uniquely determined by the line diameter d and the line pitch S as shown in FIG. 4 (4A). However, the self-impedance Z ₀ of the target line depends on the environmental conditions of the line ( ambient conditions of the subject line: Depends signal arrangement of the via conductor row and the ground via conductors column, or the ratio n such a number n _S and the number n _G of the ground via conductors GV signal via conductor SV).

Next, in the via conductor matrix MTX arranged in a matrix on the interposer 10, the representative arrangement of the signal via conductor row SVL and the ground via conductor row GVL and the target line / observation line which is the signal via conductor SV in the arrangement ( Hereinafter, the self-impedance Z ₀ of the “line” is analyzed. First, when the dispersion ratio n (n = N _S / N _G ) between the number N _S of signal via conductors SV and the number N _G of ground via conductors GV is n = 1, that is, as shown in FIG. When the ground via conductor rows GVL1, GVL2 and the signal via conductor rows SVL1, SVL2 are alternately arranged so that the distance between the centers of each row is equal to S (equal to the via conductor arrangement pitch S). Analyzes about. As shown in Analysis 1 of (B), the arrangement of the signal via conductor row SVL1 and the ground via conductor rows GVL1 and GVL2 is as follows. It can be considered to be equivalent to a multi-line type strip line having a structure equivalent to the ground metal plate 2 (GND) and the signal via conductor row SVL1 arranged therebetween as one horizontal coupling strip conductor. At this time, the coupling coefficient γ between the target line and the observation line is obtained by the self-impedance Z ₀ of the line and the mutual impedance Z _M between the lines as shown in Analysis 2 of (B). Here, the mutual inductance Z _M between the two lines is given by the mutual impedance Z _M of the expression (102) shown in (4B) of FIG. 4, and the respective self-impedance Z ₀ of both lines is expressed by (5B in FIG. ) Is given by the characteristic impedance Z ₀ in the equation (103).

Next, when the ratio n (n = N _S / N _G ) of the number N _S of signal via conductors SV and the number N _G of ground via conductors GV is n = 2, that is, as shown in FIG. In addition, an analysis is performed in which two signal via conductor rows SVL1, SVL2 are arranged at equal intervals of a center-to-center distance S (equal to the via conductor arrangement pitch S) between a pair of ground via conductor rows GVL1, GVL2. To do. The arrangement of the signal via conductor rows SVL1, SVL2 and the ground via conductor rows GVL1, GVL2 is as shown in Analysis 1 of (B). GVL2 is equivalent to ground metal plate 2 (GND), and two signal via conductor rows SVL1 and SVL2 arranged between them are equivalent to two upper and lower coupled strip conductor rows. I think there is. At this time, the coupling coefficient γ between the target line and the observation line is obtained by the self-impedance Z ₀ of the line and the mutual impedance Z _M between the lines as shown in Analysis 2 of (B). Here, the mutual inductance Z _M between the two lines is given by the mutual impedance Z _M of the equation (102) shown in FIG. 4 (4B), and the respective self-impedance Z ₀ of both lines is shown in FIG. It is given by the characteristic impedance Z ₀ of the equation (104) shown in 6B).

  The coupling coefficient γ given in FIG. 11 and FIG. 12 is summarized in FIG. 13 on the basis of comparison when there is no ground via conductor row GVL, that is, when all via conductors are signal via conductors SV. Furthermore, in order to be able to compare with the results of the high-frequency simulation described later, the via conductor placement conditions (parameters) adopted for each high-frequency simulation are listed in the combination column of each signal via conductor row SVL / ground via conductor row GVL. Applying, the concrete value of coupling coefficient γ was estimated.

If the near-end crosstalk signal V _b (1) is derived from the relational expression of FIG. 8 using this coupling coefficient γ, the crosstalk is obtained as shown in FIG. From this analysis result, in the interposer 10 of the present invention, when one or two signal via conductor rows SVL are arranged between the pair of ground via conductor rows GVL, that is, when the dispersion ratio n is n ≦ 2. It can be seen that the crosstalk can be greatly reduced to about 1/2 or less of the case where there is no ground via conductor row GVL (the ground via conductors GV are not dispersedly arranged). Incidentally, as a condition to be applied to the analysis of cross-talk, high-speed clock pulses (repetition frequency f = 6 GHz) of pulse rise time t _r t _r ≒ 20psec the outer diameter d of the via conductor d = 90 [mu] m, the target line is transmitted ( 1 psec = 10 ⁻¹² sec), and the relative dielectric constant ε _r of alumina of the dielectric layer 11 of the interposer 10 was set to ε _r = 9.

Finally, in order to confirm the performance of the interposer of the present invention, a high frequency simulation was performed, and the result will be described. 15, 16, and 17, when there is no ground via conductor row GVL, when two signal via conductor rows SVL are arranged between a pair of ground via conductor rows, the gap between the pair of ground via conductor rows Shows the observation results of crosstalk in three cases when one signal via conductor row SVL is arranged. When a 6 GHz high-speed clock pulse is fed to the target line and the interposer of the present invention is transmitted from the first main surface side (conducting to the integrated circuit element) to the second main surface (conducting to the connection destination wiring board). The near-end crosstalk signal V _b generated on the first main surface of the observation line adjacent thereto is examined. Large signal waveform of the voltage waveform is a power supply signal [reference as opposed to (7D) of FIG. 7] V _k of transmitting target line, small signal waveform is near-end crosstalk signal V _b, the signal V _b The magnitude of the crosstalk noise (V _b / V _k ) (%) was displayed by comparing the peak value of the signal with the feeding signal V _k . Arrangement conditions of via conductors in one embodiment of the interposer are shown above each voltage waveform. The high-frequency simulation used SPICE circuit simulator (Apsim SPICE from Applied Simulation Technology) to analyze high-speed transients in psec units.

The high-frequency simulation results (size of crosstalk) in FIGS. 15, 16 and 17 are shown together with the crosstalk analysis results in FIG. In this case, the length le of the via conductor is le = 5d = 450 μm, and the propagation time of the high-speed clock pulse V _k propagating through the distributed constant line of the via conductor is represented by v _p = C / (ε _r ) ^1/2 , where C is the speed of light, C = 3 × 10 ¹⁰ (cm / S), approximately 5 psec or less, and the high-speed clock pulse V _k rise time tr ≈ 20 psec, extremely fast observation We conducted cross-talk survey analysis. When the result of the high-frequency line analysis in FIG. 14 is compared with the result of the high-frequency simulation, they are in good agreement, and it can be seen from these results that the performance of the interposer of the present invention is excellent. .

The structure schematic diagram which connected the interposer of this invention to the integrated circuit element and the connecting point wiring board. The structure schematic diagram showing the structure of the interposer of this invention. The structure schematic diagram which shows the grid | lattice-like arrangement | positioning of the via conductor of the interposer of this invention. The figure showing the arrangement | positioning and mutual impedance of the object track | line which is a signal via conductor, and the observation track | line adjacent to it. Shows an arrangement and a characteristic impedance Z ₀ of the strip line covered with a ground metal conductor and below the first column signal via conductor row of. Shows an arrangement and a characteristic impedance Z ₀ of the strip line covered with a ground metal conductor upper and lower two rows signal via conductor row of. The figure explaining the electromagnetic interference of the object track | line which is a signal via conductor, and the observation track | route adjacent to it. The figure showing the relational expression of the crosstalk in the electromagnetic interference of FIG. The figure showing the relational expression of coupling coefficient (gamma) in the crosstalk of FIG. The figure which derives | leads-out the line impedance and coupling capacity for calculating | requiring the coupling coefficient (gamma) of FIG. The figure showing the structure of the via conductor matrix which has arrange | positioned one signal via conductor row | line | column between a pair of ground via conductor row | lines, and the analysis of the coupling degree. The figure showing the structure of the via conductor matrix which has arrange | positioned two signal via conductor rows between a pair of ground via conductor rows, and the analysis of the coupling degree. The figure showing the derivation | leading-out result of the coupling coefficient (gamma) with respect to the structure of the via conductor matrix of FIG.11 and FIG.12. FIG. 14 is a diagram illustrating crosstalk noise derived from the coupling coefficient γ of FIG. 13. The figure showing the crosstalk signal waveform observed by the high frequency simulation when there is no ground via conductor row. The figure showing the crosstalk signal waveform observed by the high frequency simulation in the case of arranging two signal via conductor rows between a pair of ground via conductor rows. The figure showing the crosstalk signal waveform observed by the high frequency simulation in the case of arranging one signal via conductor row between a pair of ground via conductor rows.

Explanation of symbols

10 Interposer
20 Connected wiring board
30 Integrated circuit elements
SVL signal via conductor row
GVL ground via conductor row
GV ground via conductor
SV signal via conductor
Z ₀ characteristic impedance (self-impedance)
Z _M Mutual impedance
V _b Near-end crosstalk signal
V _f Far end crosstalk signal γ Coupling coefficient
MTX via conductor matrix
11 Dielectric layer
PA 1st pad array, 2nd pad array
MS1 first main surface
MS2 2nd main surface d Outer diameter of circular section perpendicular to the axis of via conductor (diameter of via conductor, outer diameter of line)
S Distance between the axes of adjacent via conductors (via conductor pitch)
n Dispersion ratio ε _r Relative permittivity
le Via conductor length (track length)
t _r Fast clock pulse rise time

Claims (4)

In the interposer for reducing the thermal expansion strain between the integrated circuit element and the connection destination wiring board, having an intermediate linear expansion coefficient between the linear expansion coefficient of the integrated circuit element and the connection destination wiring board,
A first side pad array for connecting the integrated circuit element is formed on the first main surface side of the ceramic dielectric layer,
A second side pad array connected to the connection destination wiring substrate for transmitting and receiving signals of the integrated circuit element is formed on the second main surface side of the ceramic dielectric layer;
Via conductors that penetrate the ceramic dielectric layer in the thickness direction and are electrically connected to the first side pad array and the second side pad array are arranged in a matrix of a plurality of vertical and horizontal portions,
The via conductor has a signal via conductor and a ground via conductor respectively conducting to the signal output of the integrated circuit element and the ground, and is arranged so that the axes of the adjacent ground via conductors are positioned on a straight line. A ground via conductor row constitutes at least a part of the matrix-like arrangement,
An interposer that reduces crosstalk associated with coupling between adjacent via conductors. The interposer according to claim 1, wherein a plurality of the signal via conductors are arranged in a row between a pair of adjacent ground via conductor rows. 2. The interposer according to claim 1, wherein the plurality of signal via conductors are arranged in two rows between a pair of adjacent ground via conductor rows. 4. Any one of claims 1 to 3, wherein d <S ≦ 3d is satisfied, where d is an outer diameter of a cross section perpendicular to the axis of the signal via conductor, and S is an inter-axis distance between adjacent signals. Interposer as described in the section.

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