JP2005056958A - Interposer - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an interposer that is connected between an integrated circuit element and a connecting-destination wiring board and can reduce the crosstalk among signal via conductors disposed in a matrix. <P>SOLUTION: The interposer has an intermediate coefficient of linear expansion between those of the integrated circuit element 30 and the connecting-destination wiring board 20, and relieves the strains of the circuit element 30 and the wiring board 20 caused by thermal expansion. In the interposer, grounding via conductors GV are distributed in a group of via conductors formed of the signal via conductors SV among via conductors which are disposed on the surface of a dielectric layer in a matrix after passing through the dielectric layer in the thickness direction. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention is an interposer using a dielectric for connecting an integrated circuit element to a wiring board.

  2. Description of the Related Art A wiring board using a dielectric material such as ceramic is used as a wiring board on which a semiconductor component such as LSI or IC is mounted, or a circuit element such as a transmission line or a filter is formed inside the board. A plurality of via conductors for signal (electric signal transmission / reception), power supply (DC power supply), ground (electric signal grounding), etc. are formed on such a wiring board, and the characteristic impedance of the signal line is improved. The frequency characteristics are being improved stably. For example, Patent Document 1 proposes a method for matching the characteristic impedance of signal transmission lines formed on both surfaces of a wiring board with the characteristic impedance of signal via conductors. That is, by arranging the ground via conductor adjacent to the signal via conductor connecting the signal transmission lines formed on both surfaces, the characteristic impedance of the signal via conductor is matched with the characteristic impedance of the signal transmission line with high accuracy. This minimizes the deterioration of the signal waveform of the high-speed logic circuit and improves its propagation.

JP-A-6-37416

However, in such a via conductor, when this wiring board is applied to a high-speed logic circuit with a clock frequency of 1 GHz or more, the characteristic impedance Z ₀ in the high-frequency band of the signal via conductor that transmits the signal of the high-speed logic circuit is stabilized. And electromagnetic interference given to adjacent signal via conductors, so-called crosstalk becomes a problem. In particular, high-speed logic circuit, MPU, implement LSI such as a DSP or RAM on the wiring board, the repetition period T _P is T _P ≦ 1 nS, rising, falling time _{t r,} t _f is t _r, t _f ≦ 100pS In the case of transmitting a steep high-speed pulse signal through a wiring board, the frequency band of the high-speed pulse signal is a wide-band high-frequency signal ranging from several hundred MHz to 10 GHz or more including the harmonic signal. There is a considerable impact on the performance of LSI high-speed logic circuits by causing crosstalk in other signal via conductors adjacent to signal via conductors that transmit such high-speed pulse signals (such as noise margin reduction or signal waveform distortion). Is often affected.

  An object of the present invention is to provide an interposer that reduces electromagnetic interference, that is, crosstalk, generated between adjacent signal via conductors when a sharp high-speed pulse signal of a high-speed logic circuit is transmitted.

Means for Solving the Problems and Effects of the Invention

In order to solve the above-mentioned problems, the present invention has an intermediate linear expansion coefficient between the linear expansion coefficient of the integrated circuit element and the linear expansion coefficient of the connection destination wiring board, and the thermal expansion between the integrated circuit element and the connection destination wiring board. In the interposer to reduce distortion,
A first side pad array connecting the integrated circuit elements is formed on the first main surface side of the ceramic dielectric layer,
A second side pad array connected to a connection destination wiring substrate that transmits and receives an integrated circuit element signal is formed on the second main surface side of the ceramic dielectric layer,
Via conductors that penetrate the ceramic dielectric layer in the thickness direction and are electrically connected to the first side pad array and the second side pad array are arranged in a matrix of a plurality of vertical and horizontal portions,
The via conductor has a signal via conductor and a ground via conductor that are respectively connected to the signal output of the integrated circuit element and the ground,
A main via group in which ground via conductors are dispersedly arranged in a main via group formed of signal via conductors constitutes at least a part of the matrix arrangement,
It is characterized in that crosstalk accompanying coupling between adjacent via conductors is reduced.

In this way, an interposer (for example, a linear expansion coefficient of 7 to 8 × 10 ⁻⁶ / ° C.) having a linear expansion coefficient intermediate between the linear expansion coefficient of the integrated circuit element and the linear expansion coefficient of the connection destination wiring substrate is flip-chip. Of connected wiring boards using integrated circuit elements (for example, linear expansion coefficient 2 to 3 × 10 ⁻⁶ / ° C.) and resin substrates (for example, linear expansion coefficient 15 to 20 × 10 ⁻⁶ / ° C.) The thermal expansion strain between the integrated circuit element and the connection destination wiring board is reduced by being sandwiched therebetween. Specifically, due to the difference in coefficient of linear expansion, relative displacement in the in-plane direction between the terminals is likely to occur between the integrated circuit element and the interposer, and between the interposer and the connection destination wiring board. Therefore, a shearing stress is applied to the solder connection portion between the terminals. In this case, if the plate-like substrate that forms the main part of the interposer is made of a ceramic material having a high Young's modulus, the rigidity of the interposer is increased, and the amount of elastic deformation of the interposer even if there is a difference in linear expansion coefficient. As a result, the shear deformation acting on the solder joint portion is reduced, and problems such as peeling of the connecting portion and disconnection can be prevented.

When the characteristic impedance of the signal via conductor is arranged in a matrix as compared with a single case, the adjacent signal via conductor (hereinafter simply referred to as “target line”) surrounding the target signal via conductor (hereinafter simply referred to as “target line”). It is well known that the characteristic impedance Z ₀ of the target line can be reduced corresponding to the number M) (also referred to as “line”). That is, when the dielectric constant of the filled dielectric is ε _r , the line diameter is d, and the distance between the centers of adjacent lines is S, the characteristic impedance Z ₀ is given as follows. . Z ₀ ≈ {138 / (ε _r ) ^1/2 } {(M + 1) / M} log ₁₀ {S / (M) ^{1 / (M + 1)} d} ----- (201). Therefore, the characteristic impedance Z ₀ can be further reduced by reducing S / d and increasing the number M of adjacent lines. Further, by disposing ground via conductors (the via conductors are connected to the ground of the connection wiring board, that is, grounded) to the signal via conductors arranged in a matrix, the characteristic impedance Z ₀ of the target line is further increased. It is possible to reduce. Specifically, as shown in (4A) of FIG. 4, when the distance between the centers of the signal via conductor as the target line and the ground via conductor nearest to it is H, (4A) is approximately (4B). Can be displayed as equivalent. In this case, the characteristic impedance Z ₀ of the subject line of the signal via conductor as illustrated in (101) wherein the (4C), is possible to reduce the characteristic impedance Z ₀ even by narrowing the distance between the centers H it can. As described above, the signal via conductors are arranged in a matrix and the ground via conductors are distributed, so that the characteristic impedance Z ₀ of the signal via conductors can be made sufficiently small. In the crosstalk generated in, the coupling coefficient γ between the lines (between signal via conductors) becomes small, and the near-end crosstalk signal and the far-end crosstalk signal can be reduced. (Details will be described later).

Also, the interposer of the present invention, the number of signal via conductors and N _S, the number of ground via conductors when a N _G, whose distribution ratio _{N S / N G, 1 ≦} N S / N G ≦ 3 It can also be configured to satisfy. With this distributed array ground via conductors for signals via conductor, sufficiently reduce the characteristic impedance Z ₀ of the aforementioned subject line, or sufficiently large that capacity C _T11
(Details will be described later), and the coupling coefficient γ becomes smaller as about γ ≦ 1/2. As a result, it is possible to reduce the crosstalk to 1/2 or less compared to the case where the ground via conductors are not distributed (when all via conductors are signal via conductors), analysis and high frequency simulation (details will be described later, FIG. 15 and FIG. 18)).

Further, the interposer of the present invention may be configured such that every other signal via conductor and ground via conductor are alternately arranged vertically and horizontally. In this way, as shown in FIG. 11, each signal via conductor can have all four neighboring via conductors as ground via conductors, that is, each signal via conductor is best surrounded by a ground via conductor. Becomes an array of In this case, from the result of analysis, when the ratio n (n = N _S / N _G ) between the number N _G of the ground via conductors GV and the number N _S of the signal via conductors SV is n = 1, the nearest neighbor It was found that the coupling coefficient γ between the signal via conductors was γ ≦ 1/3, and the crosstalk between the signal via conductors was minimized (crosstalk noise was 10% or less, details will be described later). In other words, a structure close to a coaxial line with the signal via conductor as the inner conductor and the ground via conductor as the outer conductor is formed, and the electrical via that shields the signal via conductor and the adjacent signal via conductor with the ground via conductor is formed. An environment is formed. For this reason, the crosstalk between the signal via conductors is greatly reduced, and various noises due to EMC (Electro Magnetic Compatibility) electromagnetic interference entering from the outside of the interposer are also reduced.

Also, the interposer of the present invention is configured to satisfy d <S ≦ 3d, where d is the outer diameter of the cross section perpendicular to the axis of the signal via conductor, and S is the distance between the axes of adjacent signals adjacent to each other. You can also. This configuration naturally does not include this condition because each via conductor is short-circuited at S = d, but M = 4 (up, down, left, and right around the target signal via conductor) 4 signal via conductors are arranged at a distance S each), and applying S = 3d, Z ₀ ≈61 / (ε _r ) ^1/2 ------ (202) is obtained. Now, assuming that the dielectric is alumina and the relative dielectric constant ε _r is ε _r = 9, Z ₀ ≈20 (Ω) ------ (204) from the equation (202). d <S ≦ 3d ------ In the interposer of the present invention in the range of (205), the characteristic impedance Z ₀ of each signal via conductor is as small as 20 (Ω) or less, and the crosstalk is practically hindered. It can be reduced to a range where there is no.

Hereinafter, the best mode of the present invention will be described with reference to the accompanying drawings. FIG. 1 shows a state in which the interposer 10 of the present invention is mounted on the main substrate 20 and the integrated circuit element 30.
Here, the integrated circuit element 30 is MPU (Micro Processor Unit), DSP (Digital Signal Processor). A Flip Chip or CSP (Chip Size Package) using an LSI such as RAM (Random Access Memory) is shown. Further, the main substrate 20 which is a connection wiring substrate of the interposer 10 is a resin substrate such as epoxy resin, polyimide resin, BT (bismaleimide triazine) resin, PPE (polyphenylene ether) resin, or the above resin and glass fiber or polyimide fiber. It is composed of a substrate using a composite material with organic fibers.

  Next, the structure of the interposer 10 will be briefly described with reference to FIG. (2A) is a cross-sectional view (cross-sectional view seen from the side) of the interposer 10 in the thickness direction, and the structure (cross-sectional view seen from the top) of the FF cross-section is shown in (2B). First, in (2A), the dielectric layer 11 (ceramic dielectric layer) forming the main part of the interposer 10 has a thickness of 0.45 to 0.75 mm, and the material thereof is alumina or LTCC (named Low Temperature Cofire Ceramic; A glass ceramic in which an inorganic ceramic filler such as alumina is added to acid glass or lead borosilicate glass in a weight ratio of 40 to 60% is used. A via conductor that passes straight through the thickness direction of the dielectric layer 11 has a circular cross-sectional shape perpendicular to its axis, and its outer diameter is d. The distance between axes with respect to the nearest via conductor, that is, the pitch is S Are arranged at equal intervals.

Normally, the ground via conductors GV1 and GV2 that are connected to the ground terminal of the integrated circuit element 30 are positioned at both ends of the via conductor array, and the signal via conductors SV1 and SV2 that are respectively connected to the signal output terminals of the integrated circuit element 30 between them. , ------, SV9 is arranged. First side pad arrays GPA11, SPA11, SPA12 ----, GPA12 are formed on the first main surface MS1 side of the dielectric layer 11, and second side pad arrays GPA21, SPA21 are formed on the second main surface MS2 side. , SPA22, ----, GPA22 are formed, and are connected to the respective counterpart terminals (electrode pads) of the integrated circuit element 30 or the connection destination wiring substrate 20 through the connection solder balls (solder bumps) GSB11, GSB21, etc. Has been. In order to prevent the solder from spreading when forming the solder balls, dielectric thin films CTF1 and CTF2 are formed on both surfaces (first main surface MS1 and second main surface MS2) of the dielectric layer 11 excluding the pad array portion. Yes. In (2B), which represents the FF cross section of (2A), the via conductors are not only arranged in a matrix (lattice or zigzag), but are also arranged in groups with uneven spacing between the via conductors. The ground via conductors GV1, GV2 and others are arranged at the outermost edge of the via conductor matrix MTX, and the signal via conductors SV1, SV2, etc. are arranged at an inner area (pitch) S between them. Yes. The number N _S and the number N _G is a predetermined ratio of the ground via conductors GV signal via conductors SV in composed mainly via group MSVG the signal via conductors SV for the majority, for example, N _G: N _S = 1: 3 A small number of ground via conductors GV are distributed and the interposer 10 is configured to reduce crosstalk between the signal via conductors SV.

  When an IC chip made of Si is applied as the integrated circuit element 30, the coefficient of thermal expansion is between 2.6 ppm / ° C. and when a resin substrate is applied to the connection wiring board 20, the coefficient of thermal expansion is between 15 and 20 ppm / ° C. In order to alleviate the thermal expansion strain, the thermal expansion coefficient of the dielectric layer 11 of the interposer 10 is preferably in the range of 3 to 8 ppm / ° C. The dielectric of the dielectric layer 11 includes a high-temperature fired ceramic (alumina, oxide-based insulating engineering ceramic, non-oxide-based insulating engineering ceramic, etc.) having a firing temperature of 1000 ° C. or higher, and a firing temperature of 700 ° C. to A low-temperature fired ceramic (containing borosilicate glass, silica, or the like) at about 800 ° C. can also be used. As the conductor metal forming the via conductor, a high melting point metal such as tungsten, molybdenum, tantalum and niobium, which does not oxidize or evaporate at a high temperature during firing exceeding 1000 ° C. for high temperature fired ceramics, For low-temperature fired ceramics, copper, silver and gold having a relatively low melting point and excellent conductivity can be used when the co-firing method is employed.

  The manufacturing process of the interposer 10 of the present invention will be briefly described as follows. First, an alumina green sheet is produced using a ceramic green sheet forming technique. Vias (through holes) are drilled, punched or laser processed in this alumina green sheet. Next, a paste containing a conductive metal is printed on the alumina green sheet by using a screen printing apparatus to form a pad array for connection on both sides of the alumina green sheet, and the via is filled in the via. . Then, the alumina green sheet filled with the paste was transferred to a firing furnace and heated to several hundreds of degrees C., whereby the alumina and the metal in the paste were simultaneously sintered to provide the pad array on both surfaces and the through via conductor. The interposer 10 is obtained. In order to prevent solder flow of the pad array, another alumina thin film sheet may be formed by leaving the pad array portions on both surfaces of the alumina green sheet.

  Here, the arrangement of via conductors as viewed from the first main surface MS1 to which the integrated circuit element 30 of the interposer 10 is connected will be described with reference to FIG. The positions of the via conductors are determined according to the arrangement of the electrode terminals of the Flip Chip which is the integrated circuit element 30, and the via conductors are arranged in a staggered lattice pattern. In this embodiment, the spacing between adjacent rows (center-to-center distance) is 230 μm, the spacing between the upper and lower rows is 138 μm, and the distance between the axes between the adjacent via conductors, that is, the pitch S is S = 180 μm. . Since the outer diameter (wire diameter) d of each via conductor is d = 90 μm, S = 2d is optimally arranged in terms of impedance characteristics.

Next, the characteristic impedance (hereinafter also referred to as “self-impedance”) Z ₀ and the capacitance per unit length (hereinafter also referred to as “self-capacitance”) C ₁₁ as well as the adjacent signal vias of each signal via conductor SV Mutual impedance Z _M and line coupling capacitance (per unit length) C _{12 due to} coupling between conductors SV, and mutual impedance Z _GM formed by the signal via conductor SV and the nearest ground via conductor GV dispersedly arranged (To distinguish from the mutual impedance Z _M between the signal via conductors SV described above) and the line coupling capacitance C _G12 (to distinguish from the line coupling capacitance between the signal via conductors SV above “ (Referred to as “grounding capacity”) and prepare for the next crosstalk analysis. First, the coupling between the signal via conductor SV (crosstalk analysis target line) and the nearest ground via conductor GV will be described with reference to FIG. The condition of the two signal via conductors SV and the ground via conductor GV represented by (4A) can be rewritten to the equivalent condition of (4B) by regarding the ground via conductor GV as a ground (grounding conductor). Accordingly, the mutual impedance between the signal via conductor SV and the ground via conductor GV, that is, the above-described ground impedance _ZGM is expressed by (101), and the line coupling capacitance, that is, the ground capacitance _CG12 is expressed by the equation (102). I understood that it was given. The self-impedance Z ₀ and the self-capacitance C ₁₁ of each signal via conductor SV having the length le and the wire diameter d are given by (103) and (104) shown in FIG. Then, it was found that the mutual impedance Z _M and the line coupling capacitance C ₁₂ associated with the coupling of the signal via conductors SV1 and SV2 that are closest to each other are given by (106) and (107) shown in FIG.

Next, the points of the arrangement conditions, required parameters, and quantitative relational expressions for crosstalk between adjacent signal via conductors SV will be described. 7, 8, 9, and 10 regarding electromagnetic interference between adjacent via conductors, that is, so-called “crosstalk”, considering via conductors as distributed constant lines (hereinafter simply referred to as “lines”). Analyze using In FIG. 7, the parameter causing crosstalk is (7A), the relationship between adjacent lines is (7B), the structure and coupling of adjacent lines is (7C), and the relationship between the basic circuit and crosstalk is (7D). ). Each coupling shown in (7A) (taken from a plane perpendicular to the axis of the line) and each coupling shown in (7C) (taken from a plane parallel to the axis of the line) exist between the lines, especially the coupling capacitance. C ₁₂ and mutual inductance L _M is a major cause resulting in cross-talk. In the basic circuit of (7D), a line 1 for transmitting an electrical signal such as a high-speed clock pulse of several GHz is a “target line”, and a line that receives electromagnetic interference due to an electric field and a magnetic field generated in the target line adjacent to the line 1 2 is an “observation line”. Interference signals are generated at both ends of the observation line 2 and the pulse generator side of the signal source is referred to as a near end crosstalk signal V _b , and the end side of the line 1 is referred to as a far end crosstalk signal V _f . The magnitude of the crosstalk signal, in FIG. 8 (1) and (2) as shown in the formula, mainly of the coupling coefficient γ and the transmission signal between the lines rise time t _r (of the high-speed clock signal pulse The degree of steepness of the leading edge / rear edge, that is, the upper limit frequency of the broadband high frequency determined by the harmonics of the clock signal) and the line length le. This interposer is regarded as a TEM (Transverse Electromagnetic) line (electric and magnetic fields are formed in a plane perpendicular to the line, and no electric or magnetic field is generated in the signal traveling direction). The crosstalk signal _Vb is taken up and the characteristics of the line are analyzed and evaluated.

Next, as a preparation for deriving the coupling coefficient γ, the relational expressions are summarized using FIGS. 9 and 10. The required parameters are arranged in (9A) of FIG. 9, and the coupling coefficient γ is obtained as γ = C ₁₂ / C ₁₁ ≈Z ₀ / Z _M ------ (10) from the expression (3) of FIG. It was. The relationship parameter between the lines for deriving γ obtained by the equation (10) is shown in (9B), the relationship between the coupling capacitance C ₁₂ between the lines and the mutual impedance Z _M , and the characteristic impedance Z _{0 of the} target line (usually these 10 is called “self-impedance” in comparison with the mutual impedance) and the relationship between the ground capacitance C ₁₁ is summarized in FIG. The mutual impedance Z _M between the lines is uniquely determined by the line diameter d and the line pitch S as shown in FIG. 6 (6A), but the self-impedance Z ₀ of the target line depends on the environmental conditions of the line ( ambient conditions of the subject line: signal via conductor ratio n such a number n _S and the number n _G of the ground via conductors GV of SV) by different.

Next, in the ground via conductors GV which are distributed thereto and composed mainly via groups MSVG the signal via conductors SV arranged in a matrix form on the interposer 10, the number of numbers N _S and the ground via conductors of the signal via conductor N _G And the ratio n {n = N _S / N _G ----- (220), and when this ratio is simply referred to as “dispersion ratio n”}, the total ground capacitance C _T11 of the target line and the target By analyzing the coupling capacitance C ₁₂ or C ₂₂ between the line and the observation line, the analysis of the coupling state between the signal via conductors SV adjacent to each other (between the target line and the observation line) is advanced. First, the case where the dispersion ratio n is n = 1 will be described with reference to FIG. At this time, as shown in (A), the signal via conductors SV and the ground via conductors GV are alternately arranged, and any of the signal via conductors SV is vertically and horizontally, that is, the ground vias closest to the four sides. The arrangement is surrounded by the conductor GV. For this reason, as shown in [Analysis 1] in (B), four ground via conductors GV are coupled to one signal via conductor SV for both the target line and the observation line.
That is, the line coupling capacitance of N = 4 ----- (221) (this N is referred to as “grounding coefficient”) in the target line and the observation line that are the signal via conductors SV, in other words, the grounding capacity NC _G12 {Fig. 4 (see (102)). However, since the center-to-center distance between the target line and the observation line is (2) ^1/2 S at this time, the line-to-line coupling capacitance C ₂₂ is the line-to-line coupling capacity when the center-to-center distance is S. ₁₁ , C ₂₂ = (2) ^-1/2 C ₁₁ ----- (222). As shown in [Analysis 2] of (B), the total ground capacitance C _T11 for both the target line and the observation line is the self-capacitance C _{11 of the} line {see (104) in FIG. 5} and the ground capacitance NC. Since it is given as the sum of _G12 , the total ground capacitance C _T11 is obtained as C _T11 = NC _G12 + C11 = 4C _G12 + C ₁₁ ------ (223).

Next, the case where the dispersion ratio n is n = 2 will be described with reference to FIG. At this time, the arrangement of the signal via conductors SV and the ground via conductors GV can take various arrangements. In any case, as shown in (A), two signal via conductors SV and one ground via conductor GV are mutually connected. Adjacent to one another, that is, a group is formed. At this time, for any signal via conductor SV, the four adjacent via conductors (upper, lower, left and right), the adjacent four via conductors (diagonal lines), and the outer sides thereof are further positioned. When the adjacent via conductors are included in the target range, it can be seen that at least 1+ (2) ^1/2 ground via conductors GV are adjacent to each signal via conductor SV with the pitch S between the via conductors as a unit. . Therefore, as shown in [Analysis 1] in (B), the ground via conductor GV is N = 1 + (2) ^{1/2 for} one signal via conductor SV for both the target line and the observation line. ----- (224) will be combined. That is, the line coupling capacitance of the ground coefficient N, in other words, the ground capacitance _NCG12 is generated in the target line and the observation line that are the signal via conductors SV. However, since the center-to-center distance between the target line and the observation line is S at this time, the line-to-line coupling capacitance is the line-to-line coupling capacitance C _{12 in} the case of the center-to-center distance S (see (107) in FIG. 6). Become. Subject line, total ground capacitance C _T11 for any observation line, as shown in [Analysis 2] (B), since given as the sum of the self capacitance C ₁₁ and the ground capacitance NC _G12 of the line, that The total grounding capacitance C _T11 is obtained as C _T11 = NC _G12 + C11 = {1+ (2) ^1/2 } C _G12 + C ₁₁ ≈2.4C _G12 + C ₁₁ ------ (225).

The case where the dispersion ratio n is n = 3 will be described with reference to FIG. At this time, the arrangement of the signal via conductors SV and the ground via conductors GV can take various arrangements. Basically, as shown in (A), three signal via conductors SV and one ground via conductor GV are mutually connected. Adjacent to one another, that is, a group is formed. At this time, for any signal via conductor SV, the four adjacent via conductors (upper, lower, left and right), the adjacent four via conductors (diagonal lines), and the outer sides thereof are further positioned. When the adjacent via conductors are in the target range, it can be seen that at least two ground via conductors GV are adjacent to each signal via conductor SV with the pitch S between the via conductors as a unit. Therefore, as shown in [Analysis 1] in (B), the ground via conductor GV is N = 2−2 ---- (to one signal via conductor SV for both the target line and the observation line. 226) will be combined. That is, the line coupling capacitance of the ground coefficient N, in other words, the ground capacitance _NCG12 is generated in the target line and the observation line that are the signal via conductors SV. However, at this time, since the center-to-center distance between the target line and the observation line is S, the line-to-line coupling capacity is the line-to-line coupling capacity C ₁₂ in the case of the center-to-center distance S. Subject line, total ground capacitance C _T11 for any observation line, as shown in [Analysis 2] (B), since given as the sum of the self capacitance C ₁₁ and the ground capacitance NC _G12 of the line, that The total grounding capacity C _T11 is obtained as C _T11 = NC _G12 + C11 = 2C _G12 + C ₁₁ ------ (227).

The coupling coefficient γ between the target line and the observation line is given by γ = C ₁₂ / C _T11 or γ = C ₂₂ / C _T11 ------ (228) from the equation (10) in FIG. In the cases where n = 1, 2, and 3, the ground via conductors GV are not dispersed, that is, when the via conductors are all signal via conductors SV, the above (221) to (228) are used as a reference for comparison. When the coupling coefficients for the respective dispersion ratios n are collected, the analysis result of FIG. 14 is obtained. Here, the arrangement condition of via conductors is that the pitch S is S = 2d ------ (229), the length le of each via conductor is le = 5d ------ (230), and the coupling coefficient γ Was calculated and displayed in FIG.

Using this coupling coefficient gamma, a condition applied to the crosstalk, the pulse rise time t _r of the high-speed clock pulses of the outer diameter d of the via conductor d = 90 [mu] m, the target line is transmitted (repetition frequency f = 6 GHz) Assuming that t _r = 20 psec (1 psec = 10 ⁻¹² sec) and the relative dielectric constant ε _r of alumina of the dielectric layer 11 of the interposer 10 is ε _r = 9, the near-end crosstalk signal V _b (1 ), The crosstalk is obtained as shown in FIG. From this analysis result, it can be seen that in the interposer 10 of the present invention, if the dispersion ratio n is n ≦ 3, the crosstalk can be greatly reduced to about 1/3 or less of the case where the ground via conductors GV are not dispersedly arranged.

Finally, in order to confirm the performance of the interposer of the present invention, a high frequency simulation was performed, and the result will be described. 16 and 17, (A) When the ground via conductors VG are not dispersedly arranged, (B) When the dispersion ratio n = 2, (C) When the dispersion ratio n = 3, (D) The dispersion ratio n = 1 The results of high frequency simulation of crosstalk in the four cases are shown. When the 6 GHz high-speed clock pulse is fed to the target line and the interposer of the present invention is transmitted from the first main surface side (conductive to the integrated circuit element) to the second main surface (conductive to the connection destination wiring board), The near-end crosstalk signal V _b generated on the first main surface of the observation line adjacent to it is examined. The large signal waveform of the voltage waveform is a supply signal [reference as opposed to (7D) of FIG. 7] V _k of transmitting target line is the small signal waveform near-end crosstalk signal V _b, the signal V The magnitude of the crosstalk noise (V _b / V _k ) (%) is observed by comparing the peak value of _b with the feed signal V _k . On the upper side of each voltage waveform, the arrangement conditions of the via conductor in one embodiment of the interposer (the outer diameter d of the via conductor is d = 90 μm, and the pitch S between the adjacent via conductors is S = 2d) are shown. This high-frequency simulation uses a SPICE circuit simulator (Apsim SPICE from Applied Simulation Technology) to perform high-speed transient analysis in psec units.

When the high-frequency simulation results of FIGS. 16 and 17 are summarized, the relationship between the dispersion ratio n and the crosstalk noise shown in FIG. 18 is obtained. In this case, the length le of the via conductor is le = 5d = 450 μm, and the propagation time of the high-speed clock pulse V _k propagating through the distributed constant line of the via conductor is represented by v _p = C / (ε _r ) ^1/2 , where C is the speed of light, C = 3 × 10 ¹⁰ (cm / S), approximately 5 psec or less, and the high-speed clock pulse V _k rise time tr ≈ 20 psec, extremely fast observation A crosstalk survey analysis was conducted. Comparing the result of the high frequency simulation shown in FIG. 18 with the result of the high frequency line analysis shown in FIG. 15 shows that both agree fairly well and that the performance of the interposer of the present invention is excellent.

The structure schematic diagram which connected the interposer of this invention to the integrated circuit element and the connecting point wiring board. The structure schematic diagram showing the structure of the interposer of this invention. The structure schematic diagram which shows the grid | lattice-like arrangement | positioning of the via conductor of the interposer of this invention. The figure showing arrangement | positioning of the ground via conductor adjacent to a signal via conductor, its equivalent conditions, and its characteristic impedance. The figure showing the structure of a signal via conductor, and its characteristic impedance. The figure showing the arrangement | positioning and mutual impedance of the object track | line which is a signal via conductor, and the observation track | line adjacent to it. The figure explaining the electromagnetic interference of the object track | line which is a signal via conductor, and the observation track | route adjacent to it. The figure showing the relational expression of the crosstalk in the electromagnetic interference of FIG. The figure showing the relational expression of coupling coefficient (gamma) in the crosstalk of FIG. The figure which derives | leads-out the line impedance and coupling capacity for calculating | requiring the coupling coefficient (gamma) of FIG. The figure showing the analysis of arrangement | positioning and the coupling degree of the signal via conductor and the ground via conductor in the dispersion ratio n = 1. The figure showing the analysis of arrangement | positioning and the coupling | bonding degree of the signal via conductor and the ground via conductor in dispersion ratio n = 2. The figure showing the analysis of arrangement | positioning and the coupling degree of the signal via conductor and ground via conductor in dispersion ratio n = 3. The figure showing the derivation | leading-out result of the coupling coefficient (gamma) with respect to each dispersion ratio n. The figure showing the crosstalk noise derived from the coupling coefficient γ in FIG. Dispersion ratio n = 2 A diagram showing a crosstalk signal waveform observed in a high-frequency simulation under other conditions. The figure showing the crosstalk signal waveform observed in the high frequency simulation on condition of dispersion ratio n = 1 and n = 3. FIG. 18 is a diagram summarizing the relationship between the dispersion ratio n and crosstalk noise based on the observed waveforms in FIGS. 16 and 17.

Explanation of symbols

10 Interposer
20 Connected wiring board
30 Integrated circuit elements
SVG signal via conductor group
GV ground via conductor
SV signal via conductor
Z ₀ characteristic impedance (self-impedance)
Z _M Mutual impedance
V _b Near-end crosstalk signal
V _f Far end crosstalk signal γ Coupling coefficient
MTX via conductor matrix
MSVG main beer group
11 Dielectric layer
PA 1st pad array, 2nd pad array
MS1 first main surface
MS2 2nd main surface d Outer diameter of circular section perpendicular to the axis of via conductor (diameter of via conductor, outer diameter of line)
S Distance between the axes of adjacent via conductors (via conductor pitch)
n Dispersion ratio
N Grounding factor
C ₁₁ Capacity per unit length (self capacity)
C _G12 line-to-line coupling capacitance (grounding capacitance)
C _T11 Total grounding capacity ε _r Relative permittivity
le Via conductor length (track length)
t _r Fast clock pulse rise time

Claims (4)

In the interposer for reducing the thermal expansion strain between the integrated circuit element and the connection destination wiring board, having an intermediate linear expansion coefficient between the linear expansion coefficient of the integrated circuit element and the connection destination wiring board,
A first side pad array for connecting the integrated circuit element is formed on the first main surface side of the ceramic dielectric layer,
A second side pad array connected to the connection destination wiring substrate for transmitting and receiving signals of the integrated circuit element is formed on the second main surface side of the ceramic dielectric layer;
Via conductors that penetrate the ceramic dielectric layer in the thickness direction and are electrically connected to the first side pad array and the second side pad array are arranged in a matrix of a plurality of vertical and horizontal portions,
The via conductor has a signal via conductor and a ground via conductor respectively conducting to the signal output of the integrated circuit element and the ground,
The main via group in which the ground via conductors are dispersedly arranged in the main via group formed of the signal via conductors constitutes at least a part of the matrix arrangement,
An interposer that reduces crosstalk associated with coupling between adjacent via conductors. The dispersion ratio N _S / _NG satisfies 1 ≦ N _S / N _G ≦ 3, where N _S is the number of signal via conductors and N _G is the number of ground via conductors. The interposer described in. The interposer according to claim 1 or 2, wherein the signal via conductors and the ground via conductors are arranged alternately every other length and width. 4. Any one of claims 1 to 3, wherein d <S ≦ 3d is satisfied, where d is an outer diameter of a cross section perpendicular to the axis of the signal via conductor, and S is an inter-axis distance between adjacent signals. Interposer as described in the section.

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