JP2005051534A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit device provided with a delay adjustment circuit which gives optimal internal operation timing, to each of circuit blocks whose constituting component characteristics differ from each other. <P>SOLUTION: The delay adjustment circuit 10 is provided with two delay generation circuits which are arranged with respect to the circuit blocks BL1, BL2, respectively, and are constituted of delay elements having supply voltage dependency and temperature dependency the same as those of the components of their corresponding circuit blocks, and two delay control circuits arranged corresponding to the individual delay generation circuits. The delay control circuits output control signals CNT1, CNT2 to their corresponding circuit blocks. Delay generation circuits 21, 22 are constituted of delay elements having the supply voltage dependency and temperature dependency the same as those of the components of their corresponding circuit blocks BL1, BL2. Each of generation circuits 21, 22 changes a ratio of making a control signal effective/ineffective with respect to two or more stages of delay elements, and adjusting it to the supply voltage dependency and temperature dependency of its corresponding circuit block, adjusts a delay amount, and provides optimal operation timing. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a semiconductor integrated circuit device having a function of adjusting internal operation timings of a plurality of circuit blocks.

  In a semiconductor integrated circuit device that requires high speed operation, the internal operation timing is adjusted using a delay circuit that delays an input signal. As a configuration of the delay circuit, a configuration in which a plurality of delay elements are connected in series is common. For example, in a semiconductor device having a CMOS (Complementary Metal-Oxide Semiconductor device) configuration, an inverter composed of a P-channel MOS transistor and an N-channel MOS transistor connected in series is generally used as a delay element. By selecting the number of delay elements in the delay circuit, the input signal can be delayed by a desired delay time.

  However, the characteristics of each element constituting the delay element are difficult to equalize due to manufacturing variations, fluctuations in power supply voltage and ambient temperature, and there is a problem that the input signal cannot be delayed with high accuracy. It was.

  Therefore, recently, a number of delay adjustment circuits capable of accurately delaying an input signal have been proposed (see, for example, Patent Document 1 and Non-Patent Document 1). As an example, there is a configuration including a delay generation circuit including a plurality of stages of delay elements and a delay control circuit for controlling a delay amount of the delay generation circuit. A circuit such as a DLL (Delay Locked Loop) circuit or a PLL (Phase Locked Loop) is applied as the delay control circuit.

  Here, the DLL circuit generates a synchronized clock in order to cooperatively operate a plurality of internal circuits mounted on the same system. The DLL circuit mainly includes an input clock and a feedback clock fed back from the inside. A phase comparator that performs phase comparison, a charge pump circuit that outputs a control signal based on a comparison result of the phase comparator, and a filter circuit that removes a high-frequency component due to noise from the control signal.

  The delay generation circuit controls the delay time in response to the control signal from the filter circuit. In the DLL circuit, when the phases of the input clock and the feedback clock match, the control signal becomes a fixed value, and the delay amount in the delay generation circuit is fixed.

  That is, since the delay generation circuit can set the delay amount with the accuracy guaranteed by the DLL circuit, the timing can be adjusted without being affected by fluctuations in the operating environment such as power supply voltage and temperature and process variations.

Furthermore, in a plurality of circuit blocks mounted on the semiconductor integrated circuit, a delay generation circuit composed of delay elements having the same configuration as the delay generation circuit in the delay adjustment circuit is arranged, respectively, and in accordance with a control signal generated by the delay control circuit Therefore, in any circuit block, a constant delay amount can always be given to an input signal regardless of fluctuations in the operating environment.
JP-A-10-55668 "SLDRAM: High-Performance, Open-Standard Memory", Peter Gillingham et al., IEEE Micro Nov./Dec, 1997, pp.29-39.

  However, the amount of change in the internal operation timing is not necessarily the same between the plurality of circuit blocks constituting the semiconductor integrated circuit device because the power supply voltage dependence and temperature dependence of the electrical characteristics of the constituent elements are different.

  Therefore, as described above, if the delay adjustment of each circuit block is uniformly performed by the control signal from the delay adjustment circuit, the operation margin is reduced depending on the change direction of the internal operation timing.

  SUMMARY OF THE INVENTION Therefore, an object of the present invention is to provide a semiconductor integrated circuit device having a delay adjustment circuit that provides optimum internal operation timing for circuit blocks having different temperature dependence and power supply voltage dependence of constituent element characteristics. It is to be.

  According to the semiconductor integrated circuit device of the present invention, a plurality of circuit blocks having different power supply voltage dependency and temperature dependency of delay amounts generated by constituent elements, and delay amounts given to input signals by the plurality of circuit blocks are provided. A delay adjustment circuit that adjusts the delay adjustment circuit. The delay adjustment circuit is arranged for each of the plurality of circuit blocks, and each of the plurality of first stages outputs the input clock with a delay amount corresponding to the control signal. Phase comparison results between a plurality of first delay generation circuits having a plurality of delay elements and an output signal of the first delay generation circuit corresponding to the input clock and arranged for each of the plurality of first delay generation circuits And a plurality of delay control circuits for generating a control signal in response to. Each of the plurality of circuit blocks includes a sub-block that executes a predetermined operation in accordance with an input signal, and a plurality of stages that outputs the input signal with a delay amount corresponding to a control signal generated by a corresponding delay control circuit. And a second delay generation circuit having two delay elements. In each of the plurality of circuit blocks, the first delay element and the second delay element have a power supply voltage dependency and a temperature dependency with a delay amount equal to the elements constituting the sub-block.

  According to the semiconductor integrated circuit device of the present invention, in a semiconductor integrated circuit device in which a plurality of circuit blocks having different power supply voltage dependency and temperature dependency are mounted, the power supply voltage dependency specific to the circuit block is provided for each circuit block. By providing a delay amount according to the temperature dependence, it is possible to stably secure a sufficient operating margin regardless of fluctuations in the operating environment such as the power supply voltage and temperature.

  Embodiments of the present invention will be described in detail with reference to the drawings. In the drawings, the same or corresponding parts are denoted by the same reference numerals, and description thereof will not be repeated.

  First, prior to describing a semiconductor integrated circuit device according to an embodiment, a semiconductor device provided with a conventional delay adjustment circuit regarding the necessity of optimization of internal operation timing for each circuit block, which is a problem to be solved by the present invention. This will be described in detail based on the integrated circuit device.

  FIG. 10 is a diagram schematically showing a configuration of a semiconductor integrated circuit device including a conventional delay adjustment circuit.

  Referring to FIG. 10, the semiconductor integrated circuit device includes a plurality of circuit blocks BL1 and BL2, and a delay adjustment circuit 100 for adjusting a delay amount given to an input signal in each circuit block.

  The delay adjustment circuit 100 includes a delay generation circuit 120 that gives a constant delay amount to the input clock CLKIN, and a delay control circuit 110 that controls the delay amount.

  As an example, a DLL circuit is applied to the delay control circuit 110. The delay control circuit 110 outputs a control signal based on the comparison result of the phase comparator (PC: Phase Comparator) PC10 that compares the phase of the input clock CLKIN and the feedback clock fed back from the delay generation circuit 120, and the phase comparator PC10. A charge pump circuit (CP) C10 for output and a filter circuit (LPF: Low Pass Filter) L10 for removing high frequency components of the control signal are included.

  The phase comparator PC10 generates a phase comparison result signal by comparing the phases of the input clock CLKIN and the feedback clock, although the detailed circuit configuration is not shown. Specifically, when the phase of the feedback clock is delayed from the input clock CLKIN, the phase comparison result signal of “H” (logic high) level is output. On the other hand, when the phase of the feedback clock is ahead of the input clock CLKIN, a phase comparison result signal of “L” (logic low) level is output. Here, the phase comparison result signal is a signal that transitions between two potential states, a high potential and a low potential, and corresponds to the “H” level when the potential is high and to the “L” level when the potential is low. Equivalent to.

  Upon receiving the phase comparison result signal, the charge pump circuit C10 performs a charge pump operation according to the potential of the phase comparison result signal, and outputs a control signal to the subsequent filter circuit L10.

  The filter circuit L10 transmits the high frequency component of the control signal, that is, the control signal CNT from which noise has been removed, to the delay generation circuit 120.

  At this time, the control signal CNT is also transmitted to the delay generation circuits 201 and 202 arranged in the circuit blocks BL1 and BL2. Therefore, each of the delay generation circuits 201 and 202 generates a delay amount corresponding to the control signal CNT.

  FIG. 11 shows a configuration of delay generation circuit 201 shown in FIG. Since the delay generation circuits 120 and 202 shown in FIG. 10 have the same basic configuration as the delay generation circuit 201, the delay generation circuit 201 will be described as a representative.

  Referring to FIG. 11, delay generation circuit 201 includes a plurality of delay units DU1 to DUm (m is a natural number of 1 or more) connected in series between an input node and an output node. Hereinafter, when the delay units DU1 to DUm are collectively referred to, the symbol DU is used.

  The delay generation circuits 120, 201, and 202 are composed of the same delay unit DU, and each generate a delay time corresponding to the product of the unit delay amount of the delay unit DU and the number of units m.

  The delay unit DU is basically composed of a CMOS inverter. As an example, delay unit DU1 includes an inverter composed of P channel MOS transistor P1 and N channel MOS transistor N1, and an inverter composed of P channel MOS transistor P2 and N channel MOS transistor N2.

  Delay unit DU1 further includes N-channel MOS transistors NC1 and NC2 respectively coupled between the sources of N-channel MOS transistors N1 and N2 of each inverter and the ground potential.

  N channel MOS transistors NC1 and NC2 have gates coupled to control signal line 40 for transmitting control signal CNT, and are driven to an on / off state in accordance with the potential of control signal CNT received at the gate. In N channel MOS transistors NC1 and NC2, the channel resistance changes according to the potential of control signal CNT, whereby the delay amount of delay unit DU1 increases or decreases.

  Specifically, when control signal CNT is at “H” level (when the phase of the feedback clock is delayed), N-channel MOS transistors NC1 and NC2 are driven to an on state. Accordingly, since the channel resistance is lowered, the fall time of the signal output from the output node of each inverter is shortened, and the delay amount is reduced.

  On the other hand, when control signal CNT is at "L" level (when the phase of the feedback clock is advanced), N-channel MOS transistors NC1 and NC2 are driven to an off state. Therefore, since the channel resistance increases, the fall time of the signal output from the output node of each inverter becomes longer and the delay amount increases.

  Further, in each of the delay units DU2 to DUm (not shown), the delay amount is increased or decreased according to the potential of the control signal CNT, similarly to the delay unit DU1.

  As described above, the delay amount of the delay unit DU is adjusted by controlling the potential level of the control signal CNT according to the phase difference between the input clock CLKIN and the feedback clock.

  When the phases of the input clock CLKIN and the feedback clock coincide and the delay control circuit 110 is locked, the control signal CNT becomes a fixed potential, and the delay amount of the delay unit DU is fixed to a predetermined value. Therefore, the delay time generated in the delay generation circuits 120, 201, 202 having a plurality of delay units DU is controlled to a constant value determined according to the input clock CLKIN without being affected by fluctuations in the external environment such as temperature and power supply voltage. The

  FIG. 12 is an operation waveform diagram for explaining the operation timing of circuit blocks BL1 and BL2 included in the semiconductor integrated circuit device of FIG. 12A is an operation waveform diagram when the power supply voltage VDD is 1.0V, and FIG. 12B is an operation waveform diagram when the power supply voltage VDD is 1.2V.

  Referring to FIG. 12A, the delay generation circuits 201 of the circuit blocks BL1 and BL2 according to the control signal CNT generated based on the phase comparison result between the input clock CLKIN having a constant period d1 and the feedback clock. In 202, delay amounts d10 and d11 are generated.

  In the circuit block BL1, the signal SG11 delayed by the delay amount d10 with respect to the input signal SG10 is output. In the circuit block BL2, a signal SG14 that is further delayed by a delay amount d11 with respect to the input signal SG11 is output.

  As described above, the delay amounts d10 and d11 generated in the delay generation circuits 201 and 202 are determined according to the control signal CNT output from the delay control circuit 110 and are not affected by fluctuations in the power supply voltage. Therefore, as shown in FIG. 12B, even when the power supply voltage fluctuates to 1.2 V, the delay amounts d10 and d11 do not change and are kept constant.

  Here, referring again to FIG. 10, the circuit block BL <b> 1 calculates the logical product of the sub-block SB <b> 1 that performs arithmetic processing on the input signal SG <b> 10, and the output signal SG <b> 12 of the sub-block SB <b> 1 It further includes a logic gate LG1 that performs an operation and outputs a signal SG13 as an operation result.

  Similarly, in the circuit block BL2, the logical product of the sub-block SB2 that performs arithmetic processing on the input signal SG11, the output signal SG15 of the sub-block SB2 and the output signal SG14 of the delay generation circuit 202 is calculated, and the signal SG16 is obtained as the calculation result. Is further included. The configuration of each circuit block BL1, BL2 is one form thereof, and is not necessarily limited to this form.

  In the circuit block BL1, the input signal SG10 is input to the delay generation circuit 201 and also input to the sub-block SB1 as an internal signal. The sub-block SB1 is composed of, for example, a logic circuit, performs a logical operation on the signal SG10, and outputs a signal SG12. The signal SG12 has a predetermined delay time with respect to the input signal SG10 due to the characteristics of elements constituting the logic circuit.

  The output signal SG12 is input to the logic gate LG1 together with the signal SG11 output from the delay generation circuit 201. From the output node of the logic gate LG1, a signal SG13, which is the operation result of the logical product of these two signals, is output.

  Similarly, in the circuit block BL2, the input signal SG11 is input to the delay generation circuit 202 and also input to the sub-block SB2 as an internal signal. In the sub-block SB2, the input signal SG11 is delayed by a predetermined delay amount due to the characteristics of the constituent elements and output as the signal SG15.

  Signal SG15 is input to logic gate LG2 along with signal SG14 output from delay generation circuit 202. From the output node of the logic gate LG2, a signal SG16, which is the operation result of the logical product of these two signals, is output.

  Here, the elements constituting the sub-blocks SB1 and SB2 usually have the property that the electrical characteristics change when the power supply voltage, the ambient temperature, and the like fluctuate. For this reason, the delay time generated in each of the sub-blocks SB1 and SB2 varies due to fluctuations in the operating environment such as the power supply voltage and the ambient temperature.

  FIG. 13 is an operation waveform diagram for explaining operation timing in the semiconductor integrated circuit device of FIG. FIG. 13A is an operation waveform diagram at a temperature T0 [° C.], and FIG. 13B is an operation waveform diagram at a temperature T1 (> T0) [° C.].

  Referring to FIG. 13A, in the circuit block BL1, the delay generation circuit 201 outputs a signal SG11 delayed by a certain delay time d10 with respect to the signal SG10. At this time, the signal SG12 obtained by delaying the signal SG10 by the delay time d12 is generated in the sub-block SB1. Signal SG11 and signal SG12 are input to logic gate LG1. The logic gate LG1 outputs the operation result of these logical products at the timing when the signal SG11 is activated.

  A period (= d10−d12) from the time when the signal SG12 is input to the logic gate LG1 to the time when the logic is obtained represents the operation margin (hereinafter also referred to as timing margin) M12 of the circuit block BL1. In addition, since the limited operation margin is a factor that causes malfunctions, the operation margin must be obtained stably regardless of changes in the operating environment.

  In the circuit block BL2, the delay generator circuit 202 outputs a signal SG14 obtained by delaying the signal SG11 by the delay time d11. On the other hand, in the sub-block SB2, a signal SG15 obtained by delaying the signal SG11 by the delay time d13 is generated. Signal SG14 and signal SG15 are input to logic gate LG2. The logic gate LG2 outputs the operation result of the logical product of these two signals at the timing when the signal SG14 is activated. As shown in FIG. 13A, the operation margin M13 in the circuit block BL2 is a period given by (d11-d13).

  Next, referring to FIG. 13B, the delay time generated in the sub-blocks SB1 and SB2 in each circuit block BL1 and BL2 as the temperature rises from T0 [° C] to T1 [° C]. It is assumed that d12 and d14 have changed due to the temperature dependence of the element characteristics. For example, in the sub-block SB1 of the circuit block BL1, the delay time increases from d12 to d14. Also in the sub-block SB2 of the circuit block BL2, the delay time changes from d13 to d15. In the sub-block SB1 and the sub-block SB2, it is assumed that the amount of change in the delay time d14 is large and the amount of change in the delay time d15 is small due to the difference in temperature dependence of the constituent element characteristics.

  In the circuit block BL1, the delay time d10 is controlled to a fixed time by the delay adjustment circuit 201 as the delay period d14 increases. Thereby, the operation margin M14 (= d10−d14) at the temperature T1 [° C.] is smaller than the operation margin M12 at the temperature T0 [° C.].

  On the other hand, in the circuit block BL2, the delay time d15 is slightly increased, whereas the delay time d11 is controlled to a fixed time by the delay adjustment circuit 201. As a result, the operating margin M15 (= d11−d15) at the temperature T1 [° C.] slightly decreases from the operating margin M13 at the temperature T0 [° C.].

  Here, the operation margin of the entire semiconductor integrated circuit is determined by the strictest operation margin in order to prevent malfunction in all circuit blocks. Therefore, the operating margin of the semiconductor integrated circuit at the temperature T1 [° C.] is M14, which is a result of a large decrease due to the temperature rise.

  As described above, each of the circuit blocks BL1 and BL2 has a specific temperature dependency and power supply voltage dependency, whereas the delay amount in the delay generation circuits 201 and 202 is set to a constant value by the delay adjustment circuit 100. Since it is held, there is a disadvantage that the operation margin is limited by fluctuations in the power supply voltage and the ambient temperature.

  For this reason, in the delay generation circuits 201 and 202 arranged in the circuit blocks BL1 and BL2, respectively, it is necessary to generate a delay amount in consideration of the power supply voltage dependency and the temperature dependency specific to the circuit block. In view of this, the present embodiment proposes a configuration for generating an optimum delay amount for securing an operation margin for each circuit block.

Embodiment 1 FIG.
FIG. 1 schematically shows a structure of a semiconductor integrated circuit device according to the first embodiment of the present invention.

  Referring to FIG. 1, the semiconductor integrated circuit device includes a plurality of circuit blocks BL1 and BL2, and a delay adjustment circuit 10 that adjusts a delay amount given to an input signal in the circuit blocks BL1 and BL2. In this embodiment, two circuit blocks BL1 and BL2 (for example, equivalent to an array-related circuit and a peripheral circuit in a DRAM (Dynamic Random Access Memory)) having different functions are arranged. The present invention is not limited and can be widely applied to semiconductor integrated circuit devices on which a plurality of circuit blocks of two or more are mounted.

  The circuit block BL1 includes a sub-block SB1 that executes predetermined arithmetic processing, and a delay generation circuit 21 that delays an input signal. Similarly, the circuit block BL2 includes a sub-block SB2 and a delay generation circuit 22. Note that the circuit block BL1 and the circuit block BL2 have different power supply voltage dependency and temperature dependency of the constituent elements.

  FIG. 2 is a diagram showing a configuration of the delay adjustment circuit 10 shown in FIG.

  Referring to FIG. 2, delay adjustment circuit 10 includes delay generation circuits 31 and 32 that give a delay amount to input clock CLKIN, and delay control circuits 11 and 12 that control the delay amount. The delay generation circuits 31 and 32 and the delay control circuits 11 and 12 that control the delay generation circuits 31 and 32 are different from the conventional delay adjustment circuit 100 shown in FIG. 10 that includes a single delay generation circuit and delay control circuit.

  For example, a DLL circuit is applied to the delay control circuits 11 and 12. The delay control circuit 11 compares the phase of the input clock CLKIN with the feedback clock fed back from the delay generation circuit 31, and the charge pump circuit that outputs the control signal CNT1 based on the comparison result of the phase comparator PC1. C1 and a filter circuit L1 for removing a high frequency component of the control signal CNT1.

  Similarly, the delay control circuit 12 also includes a phase comparator PC2 that compares the phase of the input clock CLKIN and the feedback clock, a charge pump circuit C2 that outputs a control signal CNT2 based on the comparison result of the phase comparator PC2, and a control signal CNT2. And a filter circuit L2 for removing the high-frequency component of. Since the configuration of each circuit is the same as that described in FIG. 10, detailed description thereof will not be repeated.

  Control signals CNT1 and CNT2 output from the delay control circuits 11 and 12 are input to the corresponding delay generation circuits 31 and 32, respectively. At this time, as shown in FIG. 1, the control signal CNT1 is transmitted to the delay generation circuit 21 in the circuit block BL1, and the control signal CNT2 is transmitted to the delay generation circuit 22 in the circuit block BL2.

  That is, the delay amount between the delay generation circuit 31 and the delay generation circuit 21 in the circuit block BL1 is adjusted by the control signal CNT1, and the delay amount between the delay generation circuit 32 and the delay generation circuit 22 in the circuit block BL2 is adjusted by the control signal CNT2. Is adjusted.

  Here, the delay generation circuit 31 and the delay generation circuit 21 are composed of the same elements as the elements constituting the circuit block BL1. Further, the delay generation circuit 32 and the delay generation circuit 22 are composed of the same elements as the elements constituting the circuit block BL2. Therefore, the control signals CNT1 and CNT2 are generated in the delay adjustment circuit 10 based on the electrical characteristics specific to the corresponding circuit block, and the delay amount can be adjusted with high accuracy for each circuit block.

  FIG. 3 shows a configuration of delay generation circuit 21 shown in FIG. Since the delay generation circuits 21 and 22 shown in FIG. 1 and the delay generation circuits 31 and 32 shown in FIG. 2 have the same basic configuration, the delay generation circuit 21 is representatively shown.

  Referring to FIG. 3, delay generation circuit 21 includes n (n is an even number) delay units DCU1 to DCUn connected in series between an input node and an output node.

  Delay unit DCU1 has an inverter formed of P-channel MOS transistor P1 and N-channel MOS transistor N1, and N-channel MOS transistor NC1 coupled between the source of N-channel MOS transistor N1 and the ground potential.

  N-channel MOS transistor NC1 has a gate coupled to control signal line 40, and is driven to an on / off state in accordance with the potential of control signal CNT1 input to the gate. As the channel resistance of the N-channel MOS transistor NC1 changes according to the potential of the control signal CNT1, the delay amount of the delay unit DCU1 increases or decreases.

  An enabling switch circuit SW1 is arranged between the gate of the N channel MOS transistor NC1 and the control signal line 40. The enabling switch circuit SW1 selectively couples the gate of the N-channel MOS transistor NC1 with the control signal line 40 or the power supply voltage VDD. Thereby, the enabling switch circuit SW1 enables / disables the control signal CNT1.

  When the N-channel MOS transistor NC1 and the control signal line 40 are electrically coupled by the enabling switch circuit SW1, the control signal CNT1 is enabled. Therefore, the delay amount of the delay unit DCU1 is adjusted according to the potential of the control signal CNT1.

  On the other hand, when the N-channel MOS transistor NC1 and the control signal wiring 40 are electrically separated by the enabling switch circuit SW1, the control signal CNT1 is invalidated. At this time, the delay characteristics of the delay unit DCU1 reflect the element characteristics of the transistors constituting the delay unit DCU1.

  Similarly to delay unit DCU1, delay units DCU2 to DCUn are respectively connected to an inverter composed of P channel MOS transistors P2 to Pn and N channel MOS transistors N2 to Nn, and between N channel MOS transistors N2 to Nn and the ground potential. N-channel MOS transistors NC2 to NCm coupled to each other.

  Enabling switch circuits SW2 to SWn are arranged between N channel MOS transistors NC2 to NCn and control signal wiring 40, respectively.

  Each of the delay units DCU2 to DCUn is adjusted in delay amount by the control signals CNT1 being enabled / disabled by the corresponding enable switch circuits SW2 to SWn.

  In this way, the delay amount can be adjusted for each delay unit by individually switching the enable switch circuits SW1 to SWn arranged in the delay units DCU1 to DCUn and setting the control signal CNT1 to be valid / invalid. it can. Therefore, the delay amount generated in the entire delay generation circuit 21 is adjusted by changing the ratio of the enable switch circuit that sets the control signal CNT1 to be effective among the n enable switch circuits SW1 to SWn. Can do.

  For example, when all the n enable switch circuits SW1 to SWn are set to be effective, a delay amount corresponding to the control signal CNT1 from the delay control circuit 11 is generated in any of the delay units DCU1 to DCUn. Therefore, the delay amount generated in the delay generation circuit 21 is a fixed value that is not affected by fluctuations in the power supply voltage or the ambient temperature, as described above.

  On the other hand, when all of the n enable switch circuits SW1 to SWn are set to invalid, a delay amount that depends on the characteristics of the constituent elements occurs in any of the delay units DCU1 to DCUn. That is, the delay amount generated in the delay generation circuit 21 reflects the power supply voltage dependency and temperature dependency of the constituent elements.

  Further, when i (i is a natural number between 1 and n) among n enable switch circuits SW1 to SWn is set to be effective, the intermediate delay amount generated in the above two patterns according to the ratio. A delay amount becomes a value.

  FIG. 4 is a layout diagram showing an arrangement example of the enabling switch circuits SW1 to SWn of FIG.

  Referring to FIG. 4, N channel MOS transistors NC1-NCn have drains connected to the sources of N channel MOS transistors N1-Nn constituting a CMOS inverter (not shown), and sources connected to a ground potential (not shown). . These connections are realized by contact holes arranged in the ohmic region.

  Gate electrodes G1 to Gn are arranged between the sources and drains of N channel MOS transistors NC1 to NCn, respectively. As shown in FIG. 4, the gate electrodes G <b> 1 to Gn have a T shape, and have regions that intersect the power supply voltage wiring 50 and the control signal wiring 40. This region forms the enabling switch circuits SW1 to SWn shown in FIG. That is, in the delay unit DCUi, when the gate electrode Gi and the control signal wiring 40 are in a conductive state, the control signal CNT1 is validated. On the other hand, when the gate electrode Gi and the power supply voltage wiring 50 are in a conductive state, the control signal CNT1 is invalidated.

  These valid / invalid settings are controlled by contact holes C1 to Cn arranged in the intersection region. For example, in the N channel MOS transistor NC1, since the contact hole C1 is arranged on the control signal wiring 40 side, the gate electrode G1 and the control signal wiring 40 are electrically coupled, and the control signal CNT1 is validated. The On the other hand, in N channel MOS transistor NC2, since contact hole C2 is arranged on the side of power supply voltage wiring 50, gate electrode G2 and power supply voltage VDD are electrically coupled, and control signal CNT1 is invalidated. . Therefore, in the manufacturing process, the delay amount can be adjusted by determining the arrangement of the contact holes C1 to Cn of the enabling switch circuits SW1 to SWn based on the characteristics of the constituent elements.

  FIG. 5 is a diagram showing the relationship between the delay amount generated in the delay generation circuits 21 and 22 of FIG. 3 and the power supply voltage VDD. As an example, the relationship between the delay amount d generated in the delay generation circuit 21 and the power supply voltage VDD is shown.

  Referring to FIG. 5, characteristics (1) to (3) are power supply voltage dependences of the delay amount d that occurs when the ratio of the enabling switch circuits SW <b> 1 to SWn is set to be valid. Characteristic (1) indicates a delay amount d generated when all of the n enable switch circuits SW1 to SWn are set to be effective. Characteristic (2) is a delay amount d generated when n / 2, which is equivalent to half of n enable switch circuits SW1 to SWn, are set to be effective. Characteristic (3) is a delay amount d generated when all the n enable switch circuits SW1 to SWn are set to be invalid.

  The characteristic (4) in FIG. 5 is the power supply voltage dependence of the delay amount d generated in other sub-blocks included in the circuit block BL1 in which the delay generation circuit 21 is arranged.

  As apparent from FIG. 5, in the characteristic (1) (when all the n enable switch circuits SW1 to SWn are enabled), the delay amount d is determined by the control signal CNT1 from the delay adjustment circuit 10 according to the power supply voltage. Regardless of the change, it is always held at a constant amount.

  On the other hand, in the characteristic (3) (when all the n enable switch circuits SW1 to SWn are disabled), the delay amount d shows a dependency that decreases as the power supply voltage increases.

  Further, in the characteristic (2) (when n / 2 enabling switch circuits are effective), the delay amount d shows power supply voltage dependency corresponding to the middle between the characteristic (1) and the characteristic (3).

  When the above characteristics (1) to (3) are compared with the power supply voltage dependency of the delay amount d of the sub-block shown in the characteristic (4), the characteristic (2) shows the power supply voltage dependency equal to the characteristic (4). Is recognized. Therefore, if the delay generation circuit 21 is controlled so that the generated delay amount d has the power supply voltage dependency shown in the characteristic (2), the operation margin of the circuit block BL1 on which the delay generation circuit 21 is mounted is maximized. It is judged that it can be done. That is, if half of the enabling switch circuits SW1 to SWn are set to be valid and the remaining half are set to be invalid, the operation margin can be stably secured regardless of fluctuations in the power supply voltage.

  Similarly, in the circuit block BL2, the validity / invalidity of the activation switch circuits SW1 to SWn of the delay generation circuit 22 is set in accordance with the power supply voltage dependency of the delay amount generated in the sub-blocks included therein. A delay amount that maximizes the operation margin can be generated.

  FIG. 6 is an operation waveform diagram for explaining operation timing in the semiconductor integrated circuit device shown in FIG. 6A and 6B are operation waveform diagrams when the power supply voltage VDD is 1.0 V and 1.2 V, respectively.

  6A and 6B is compared, the cycle d1 of the input clock CLKIN is unchanged, so that the control signals CNT1 and CNT2 output from the delay control circuits 31 and 32 shown in FIG. In both cases, the power supply voltage is equal to 1.0 V and the power supply voltage is 1.2 V.

  On the other hand, in the delay generation circuit 21, since the enable / disable of the enable switch circuits SW1 to SWn is set in accordance with the power supply voltage dependency of the elements constituting the circuit block BL1, when the power supply voltage is 1.0V The delay amount d2 is different from the delay amount d6 when the power supply voltage is 1.2V.

  Also in the delay generation circuit 22, the enable / disable switches of the enabling switch circuits SW1 to SWn are set in accordance with the power supply voltage dependency of the elements constituting the circuit block BL2, and therefore when the power supply voltage is 1.0V. The delay amount d3 is different from the delay amount d7 when the power supply voltage is 1.2V.

  Therefore, if the delay amount generated in the delay generation circuits 21 and 22 is adjusted so as to ensure the operation margin according to the power supply voltage dependency of the corresponding circuit blocks BL1 and BL2, regardless of the fluctuation of the power supply voltage, The stable operation of the semiconductor integrated circuit device can be maintained.

  As described above, according to the first embodiment of the present invention, there is provided a semiconductor integrated circuit device including a plurality of circuit blocks having different power supply voltage dependency and temperature dependency from each other, and a delay arranged in each circuit block. In the delay adjustment circuit for adjusting the delay amount of the generation circuit, a delay generation circuit and a delay control circuit are arranged for each circuit block, and the delay generation circuit arranged in the circuit block and in the delay adjustment circuit corresponds to the circuit block. By configuring with the same element, the delay amount can be adjusted with high accuracy in each circuit block.

  In addition, a switch circuit for enabling / disabling a control signal for adjusting the delay amount is provided in each delay generation circuit arranged in each circuit block, and the power supply voltage dependency and temperature dependency of the corresponding circuit block are provided. By generating the reflected delay amount, it is possible to provide the optimum operation timing for each circuit block.

  From the above, according to the semiconductor integrated circuit device according to the first embodiment, even when a plurality of circuit blocks having different power supply voltage dependency and temperature dependency are provided, the operating environment such as the power supply voltage and the ambient temperature is provided. Since the optimum operation timing is provided regardless of the fluctuation of the operation, the operation margin is maintained and the stable operation is guaranteed.

Embodiment 2. FIG.
In the semiconductor integrated circuit device according to the first embodiment, an enabling switch circuit is arranged in each delay unit constituting the delay generating circuit, and the control signal is made effective in accordance with the power supply voltage dependency and temperature dependency of the circuit block. By changing the ratio to be realized, it is possible to secure a stable operating margin that does not depend on fluctuations in the power supply voltage or temperature.

  The present embodiment further proposes a second configuration example of the delay generation circuit arranged in each circuit block. The semiconductor integrated circuit according to the present embodiment has the same configuration as that of the semiconductor integrated circuit device of the first embodiment except for the delay generation circuit described below. Therefore, a detailed description of the overall configuration and overlapping parts of the semiconductor integrated circuit device is omitted.

  FIG. 7 shows a structure of delay generation circuit 21 included in the semiconductor integrated circuit device according to the second embodiment of the present invention. Since the delay generation circuit 22 and the delay generation circuits 31 and 32 (not shown) have the same configuration as the delay generation circuit 21 as in the first embodiment, the delay generation circuit 21 will be representatively described below. explain.

  Referring to FIG. 7, delay generation circuit 21 includes n delay units DCU1 to DCUn (n is a natural number of 2 or more) connected in series between an input node and an output node.

  Delay unit DCU1 includes an inverter formed of P channel MOS transistor P1 and N channel MOS transistor N1, and N channel MOS transistors NC1 and NE1 coupled in parallel between the source of N channel MOS transistor N1 and the ground potential. Have.

  N-channel MOS transistor NC1 has a gate coupled to control signal line 40, and receives control signal CNT1 output from delay adjustment circuit 11 (not shown).

  N channel MOS transistor NE1 has a gate coupled to an enable signal generation unit (not shown). N-channel MOS transistor NE1 is turned on / off according to the potential of enable signal CE1 from the enable signal generator.

  The enable signals CE1 to CEn have a function of enabling / disabling the control signal CNT1 in the same manner as the enable switch circuits SW1 to SWn shown in FIG. The enable signals CE1 to CEn are set to a potential state of either “H” level or “L” level in an enable signal generation unit described later.

  When enable signal CE1 is at "H" level, corresponding N channel MOS transistor NE1 is turned on, and the source of N channel MOS transistor N1 of the inverter is electrically coupled to the ground potential. As a result, the control signal CNT1 input to the N-channel MOS transistor NC1 is invalidated. At this time, the delay characteristic of the delay unit DCU1 reflects the element characteristics of the transistors constituting the delay unit DCU1.

  On the other hand, when enable signal CE1 is at "L" level, corresponding N-channel MOS transistor NE1 is turned off. At this time, the control signal CNT1 is validated. That is, the delay amount of the delay unit DCU1 increases or decreases as the channel resistance of the N-channel MOS transistor NC1 changes according to the potential of the control signal CNT1.

  Similarly for delay units DCU2 to DCUn, N channel MOS transistors NC2 to NCn and NE2 to NEn are coupled in parallel between N channel MOS transistors N2 to Nn and the ground potential, respectively. Activation signals CE2 to CEn are input to the gates of N channel MOS transistors NE2 to NEn, respectively. In each of the delay units DCU2 to DCUn, the control signal CNT1 is set to be valid / invalid according to the enable signals CE2 to CEn, and the delay amount is adjusted.

  Further, although not shown, the delay generation circuit 22 arranged in the circuit block BL2 has the same configuration, and the control signal CNT2 is set to be valid / invalid by the validation signals CE1 to CEn.

  As described above, the enable signals CE1 to CEn input to the delay units DCU1 to DCUn are individually set, and the control signals CNT1 and CNT2 are set to be valid / invalid, thereby adjusting the delay amount for each delay unit. be able to. As in the first embodiment, delay is generated by changing the ratio of the enable signal that is set to the “L” level so that the control signals CNT1 and CNT2 become effective among the n enable signals CE1 to CEn. The amount of delay generated in the entire circuits 21 and 22 can be adjusted.

  In contrast to the first embodiment in which the control signals CNT1 and CNT2 are set to be valid / invalid during the manufacturing process, the present embodiment can be arbitrarily set by inputting the validation signals CE1 to CEn even after chip formation. Therefore, it is possible to measure the fluctuation of the power supply voltage dependency caused by the variation in the characteristics generated in the manufacturing process at the time of the test, and reflect the measurement result in the adjustment of the delay amount. As a result, the operation margin of the semiconductor integrated circuit device can be further improved.

  FIG. 8 is a diagram showing a configuration of an enabling signal generation unit that generates the enabling signals CE1 to CEn shown in FIG.

  Referring to FIG. 8, the enable signal generation unit includes a shift register including n flip-flop circuits FF1 to FFn.

  The shift register sequentially shifts the stored n-bit input signal Din to the adjacent flip-flop circuit FF in synchronization with the clock TCLK input from the outside of the semiconductor integrated circuit device.

  At this time, each of the flip-flop circuits FF1 to FFn shifts the stored data and outputs the inverted data in parallel. The output inverted data is further inverted by inverters I1 to In and output as enable signals CE1 to CEn. By n clock pulses, n-bit enable signals CE1 to CEn are generated in parallel with n-bit data being stored in the shift register.

  FIG. 9 is a timing chart in the enabling signal generation unit of FIG.

  Referring to FIG. 9, n-bit input signals Din (= Dn, Dn−1,..., D2, D1) are sequentially shifted by a shift register in synchronization with a clock TCLK having a fixed period. Specifically, in clock 1, data Dn is input to flip-flop circuit FF1. At clock 2, the data Dn of the flip-flop circuit FF1 is shifted to the flip-flop circuit FF2, and the data Dn-1 is input to the flip-flop circuit FF1. At this time, data Dn is output from Q1 as the enabling signal CE1 in parallel with the shift operation.

  Similarly, in clock 3, data Dn of Q2 is shifted to Q3, data Dn-1 of Q1 is shifted to Q2, and data Dn-2 is input to Q1. At this time, data Dn-1 and Dn are output from Q1 and Q2 as enable signals CE1 and CE2.

  As described above, the enable signals CE1 to CEn are generated together with the shift operation in synchronization with the clock TCLK. As shown in FIG. 9, at the clock n, n-bit enable signals CE1 to CEn (= D1, D2 to Dn) are output from the shift register. Activation signals CE1-CEn are input in parallel to the gates of N-channel MOS transistors NE1-NEn in FIG. In each of the N channel MOS transistors NE1 to NEn, as described above, the control signal CNT1 is set to be enabled / disabled by the enable signals CE1 to CEn, and the delay amount is adjusted.

  As described above, according to the second embodiment of the present invention, in the delay generation circuit arranged in each circuit block, the input of the enabling signal for setting the control signal for adjusting the delay amount to be valid / invalid By providing the means and generating the delay amount reflecting the power supply voltage dependency and the temperature dependency of the corresponding circuit block, it is possible to provide the optimum timing for each circuit block.

  In addition, since the enabling signal can be input even after chip formation, fluctuations in power supply voltage dependency caused by variations in characteristics that occur in the manufacturing process are measured during testing, and the measurement results are used to adjust the delay amount. It can be reflected. As a result, the operational margin of the semiconductor integrated circuit can be further improved.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

1 schematically shows a configuration of a semiconductor integrated circuit device according to a first embodiment of the invention. FIG. It is a figure which shows the structure of the delay adjustment circuit 10 shown in FIG. FIG. 2 is a diagram showing a configuration of a delay generation circuit 21 shown in FIG. FIG. 4 is a layout diagram illustrating an arrangement example of enabling switch circuits SW <b> 1 to SWn of FIG. 3. It is a figure which shows the relationship between the delay amount which generate | occur | produces in the delay generation circuit 21 of FIG. 3, and a power supply voltage. FIG. 2 is an operation waveform diagram for illustrating operation timing in the semiconductor integrated circuit device shown in FIG. 1. It is a figure which shows the structure of the delay generation circuit 21 contained in the semiconductor integrated circuit device according to Embodiment 2 of this invention. It is a figure which shows the structure of the validation signal production | generation part which generate | occur | produces the validation signals CE1-CEn shown in FIG. FIG. 9 is a timing chart in the enabling signal generation unit of FIG. 8. It is a figure which shows schematically the structure of the semiconductor integrated circuit device provided with the conventional delay adjustment circuit. FIG. 11 illustrates a configuration of a delay generation circuit 201 illustrated in FIG. 10. FIG. 11 is an operation waveform diagram for describing operation timings of circuit blocks BL1 and BL2 included in the semiconductor integrated circuit device of FIG. FIG. 11 is an operation waveform diagram for illustrating operation timing in the semiconductor integrated circuit device of FIG. 10.

Explanation of symbols

  BL1, BL2 circuit block, 10,100 delay adjustment circuit, 21, 22, 31, 32, 120, 201, 202 delay generation circuit, 11, 12, 110 delay control circuit, CLKIN input clock, PC1, PC2, PC10 phase comparison C1, C2, C10 charge pump circuit, L1, L2, L10 filter circuit, SB1, SB2 sub-block, LG1, LG2 logic gate, P1-Pn, P1-P2m P-channel MOS transistors, N1-Nn, NC1-NCn , NE1 to NEn, N1 to N2m N channel MOS transistor, SW1 to SWn enabling switch circuit, G1 to Gn gate electrode, 40 control signal wiring, 50 power supply voltage wiring, CNT1, CNT2, CNT control signal, CE1 to CEn enabling Signal, FF1 to FFn Flop circuit, I1~In inverter.

Claims (5)

A plurality of circuit blocks having different power supply voltage dependency and temperature dependency of the delay amount generated by the constituent elements;
A delay adjustment circuit that adjusts an amount of delay given to the input signal by each of the plurality of circuit blocks;
The delay adjustment circuit includes:
A plurality of first delay generation circuits which are arranged for each of the plurality of circuit blocks and each have a plurality of stages of first delay elements that output an input clock with a delay amount corresponding to a control signal. When,
A plurality of delay controls arranged for each of the plurality of first delay generation circuits and generating the control signal in response to a phase comparison result between the input clock and the output signal of the corresponding first delay generation circuit Circuit and
Each of the plurality of circuit blocks is
A sub-block that executes a predetermined operation in response to the input signal;
A second delay generation circuit having a plurality of stages of second delay elements that output the input signal with a delay amount corresponding to the control signal generated by the corresponding delay control circuit;
In each of the plurality of circuit blocks, the first delay element and the second delay element have a power supply voltage dependency and a temperature dependency with a delay amount equal to that of the elements constituting the sub-block. .   The second delay generation circuit adjusts the delay amount in response to the validated control signal and means for validating / invalidating the control signal in each of the plurality of second delay elements. The semiconductor integrated circuit device according to claim 1, further comprising: means.   The means for validating / invalidating the control signal is characterized in that a delay amount generated by the second delay generation circuit is equal to a delay amount generated by the sub-block arranged in the corresponding circuit block and has a power supply voltage dependency and temperature dependency The semiconductor integrated circuit device according to claim 2, wherein the control signal is set to be valid / invalid so as to have performance.   4. The semiconductor according to claim 3, wherein the means for enabling / disabling the control signal includes a plurality of switch circuits that electrically couple / separate the control signal and each of the plurality of stages of second delay elements. 5. Integrated circuit device.   The means for validating / invalidating the control signal electrically connects the control signal and each of the plurality of stages of second delay elements in accordance with an validation signal applied to the plurality of stages of second delay elements. The semiconductor integrated circuit device according to claim 3, wherein the semiconductor integrated circuit device is coupled / separated with each other.

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