JP2005051270A - Semiconductor integrated circuit device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To enhance the switching speed and the transfer efficiency of a MOS transistor by designing the structure of the gate electrode of the MOS transistor used in a semiconductor integrated circuit device as the output transistor such that the distributed constant like wiring resistance of the gate electrode is easily reduced, and to increase the operable time of an equipment using the semiconductor integrated circuit device by reducing the loss in the semiconductor integrated circuit device. <P>SOLUTION: In the semiconductor integrated circuit device which uses a MOS transistor T1 as a transistor for outputting large current, the source and drain of the transistor T1 are formed such that a plurality of source regions 1a and drain regions 1b surrounded by gate electrodes 2 are connected to each other in parallel. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor integrated circuit device, and more particularly to a configuration of a transistor used as an output circuit thereof.

  In a drive circuit of a portable device powered by a battery or a switch circuit of a switching power supply, a large current such as an output is used to reduce the current consumption of the semiconductor integrated circuit device and lengthen the operable time of the device as much as possible. As shown in the circuit diagram of FIG. 2, a MOS transistor (hereinafter abbreviated as “MOS transistor”) is often used as the flowing transistor. That is, since the MOS transistor operates under voltage control and does not need to pass a base current unlike a bipolar transistor, the operating time of the device can be extended by at least the power consumed as the base current. In particular, in the case of an output transistor with a large driving current, the loss due to the base current is often not negligible.

  The output circuit shown in FIG. 2 includes N-type MOS transistors T1 and T2 connected in series between a first power supply voltage (VDD1) and a reference potential (GND), and a wiring S1 at the gate of the MOS transistor T1. And a P-type MOS transistor T3 and an N-type MOS transistor T4 to which the drain is connected. The source of the MOS transistor T3 is connected to the second power supply voltage (VDD2) having a voltage value higher than VDD1, the source of the MOS transistor T4 is connected to GND, and the gates of the MOS transistors T2, T3 and T4 are shown in the figure. Control signals from other circuits that are not connected are connected, and the connection point of the MOS transistors T1 and T2 is connected to the output terminal (OUT). The N-type semiconductor substrate (also referred to as “substrate”) of the MOS transistor T3 is connected to VDD2, the P-type wells of the MOS transistors T2 and T4 are connected to GND, and the P-type well of the MOS transistor T1 is It is connected to the same potential as OUT.

  The resistors R1 to R4 in each MOS transistor indicate the ON resistance when each MOS transistor is conductive (ON), and the resistor R5 indicates the resistance of the gate of the MOS transistor T1. The gate resistance of the MOS transistors other than the MOS transistor T1 is omitted because its driving capability is relatively small and the influence of the gate resistance is small.

  A conventional structure of the MOS transistor T1 of the output circuit as shown in FIG. 2 will be described with reference to the layout diagram of FIG. The MOS transistor T1 ′ in FIG. 3 includes a plurality of diffusion regions formed by introducing N-type impurities into the semiconductor substrate and serving as a source region 1a and a drain region 1b, and a source region 1a and a drain region 1b. Aluminum for connecting the gate 2 made of polysilicon or the like formed in parallel with the source region 1a and the drain region 1b to form one source electrode and drain electrode and to connect to other circuits and output terminals. The metal wiring layers 3a and 3b made of the like, and the connection holes (also referred to as “contacts”) 4 for electrically connecting the diffusion regions and the metal wiring layers are shown. Since each manufacturing process may be formed by a general MOS process, detailed description of the manufacturing method is omitted.

  However, as shown in FIG. 3, the structure for increasing the driving capability of a conventional MOS transistor is a MOS transistor having a unit channel width (W ′) several tens to several hundred times the channel length (L). Since a plurality of transistors are connected in parallel to form one MOS transistor T1 ', there are the following problems.

  That is, although the resistance value (specific resistance) per unit area of the polysilicon serving as the gate 2 is generally several tens of ohms, it is only connected by the metal wiring layer 3c outside the diffusion region. The gate 2 at a position away from the metal wiring layer 3c having a low resistance value is delayed in signal transmission due to its distributed constant resistance and parasitic capacitance and the ON resistances R3 and R4 of the MOS transistors T3 and T4. Since the switching speed (referred to as “switching speed”) of conduction and cutoff of the transistor T1 ′ becomes slow, the switching speed cannot be increased too much. Also, if the switching speed is slow, a through current flows between the power supply lines at the time of switching, resulting in a large loss. Therefore, it has been difficult to further increase the operating time of the device by increasing the transmission efficiency.

  In view of this, the present invention provides a semiconductor integrated circuit device using a MOS transistor as an output transistor so that the switching speed and transmission efficiency can be increased by adopting a structure in which the distributed constant wiring resistance of the gate can be easily reduced. It is an object of the present invention to reduce the loss of a semiconductor integrated circuit device and to easily extend the operable time of a device using the semiconductor device.

In order to solve the above problems, the invention according to claim 1 is a semiconductor integrated circuit device using a MOS transistor as a transistor for outputting a large current.
The source and drain of the transistor are formed by connecting a plurality of source and drain regions surrounded by a gate electrode in parallel,
The gate electrode is formed in a lattice shape to reduce its distributed constant resistance, and three or more total drain regions and source regions are provided around each source region or each drain region,
Each source region of the transistor is provided with a diffusion region for connecting the well region formed in the semiconductor substrate to a predetermined potential in order to reduce the distributed constant resistance value of the well region. A semiconductor integrated circuit device.

The invention according to claim 2 is a semiconductor integrated circuit device using a MOS transistor as a transistor for outputting a large current.
The source and drain of the transistor are formed by connecting a plurality of source and drain regions surrounded by a gate electrode in parallel,
The gate electrode is formed in a lattice shape to reduce its distributed constant resistance, and three or more total drain regions and source regions are provided around each source region or each drain region,
Of the plurality of source regions of the transistor, the wells formed in the semiconductor substrate in order to reduce the resistance of the distributed constant of the well regions in some of the source regions that are not all the source regions. A semiconductor integrated circuit device is provided with a diffusion region for connecting the region to a predetermined potential. According to this embodiment, for example, since a well region is provided for one of a plurality of source regions, the area can be reduced as compared with the case where a well region is provided for each source region. For example, an embodiment in which a well region is provided or not provided in a source region in units of columns along the gate electrode is given as an example.

  Since the semiconductor integrated circuit device according to the present invention can easily reduce the distributed constant resistance value of the gate at a position away from the connection with the metal wiring layer having a low resistance compared to the polysilicon layer. The switching speed and transmission efficiency can be easily increased, and it is possible to reduce the loss of the semiconductor integrated circuit device and to easily extend the operable time of equipment using the semiconductor device. Further, since the distributed constant resistance value of the semiconductor substrate or the well region formed in the semiconductor substrate can be easily reduced and the potential can be stabilized, it can be as large as an output MOS transistor. Even in the case of a transistor element having an area, the layout is facilitated and the layout period can be easily shortened, and the withstand voltage when the MOS transistor is ON can be kept high.

  Hereinafter, an embodiment of the present invention will be described in detail with reference to FIG. In the present specification, the same or similar parts are denoted by the same reference numerals throughout the drawings to simplify the description. FIG. 1 shows the structure of an output N-type MOS transistor T1 used in the semiconductor integrated circuit device of the present invention. FIG. 1 (a) is a top view of the main part, and FIG. 1 (b) is the FIG. FIG. 1C is a cross-sectional view taken along Y1-Y4 in FIG. 1A. For easy understanding, the same main part in each drawing is given the same oblique line, and the thickness of each layer in the sectional view is schematically represented.

  The output MOS transistor T1 shown in the layout diagram viewed from the upper surface of FIG. 1A includes a gate 2 made of polysilicon or the like arranged in a lattice pattern, and an N-type impurity in a region surrounded by the gate 2 A plurality of, for example, hundreds to thousands of source regions 1a and drain regions 1b formed by thermal diffusion or ion implantation are formed in parallel on the source region 1a and a plurality of source regions 1a are connected in parallel. A metal wiring layer 3a made of aluminum or the like for forming one source electrode, and a metal wiring layer 3b formed on the drain region 1b and connected to the plurality of drain regions 1b in parallel to form one drain electrode; , The metal wiring layer 3c for connecting the end portions of the gate 2 to reduce the distributed constant resistance value, and the connection holes ("" for electrically connecting each diffusion region and each metal wiring layer Also called Ntakuto ") and a 4.

  That is, a large number of unit MOS transistors having a channel length of L and a unit channel width of W are formed around each source region 1a and drain region 1b, and the total of the unit channel widths is the driving capability of the MOS transistor T1. The total channel width that prescribes Further, since the gate 2 is formed in a lattice shape, the resistance of the distributed constant can be easily reduced as compared with the conventional case.

  The configuration of the MOS transistor T1 will be further described based on the cross-sectional views of FIGS. 1B and 1C. As shown in a cross-sectional view along Y1-Y2 of FIG. 1A in FIG. 1B, a part of an N-type semiconductor substrate (also referred to as “substrate”) 5 is selectively oxidized (“LOCOS”). P-type impurities are introduced into a region surrounded by 7 (referred to as “active area”) to form a well 6, and a plurality of diffusion regions 1 a into which N-type impurities are introduced are formed in the well 6. A gate 2 made of a polysilicon layer is formed at the upper peripheral portion of the diffusion region 1a, a metal wiring layer 3a is formed above each diffusion region 1a and the gate 2, and an oxide film or nitride is formed on the gate 2 and the metal wiring layer 3a. A protective film 8 made of a film or the like is formed.

  Further, at the center of each diffusion region 1a, a diffusion region (referred to as a "batting contact") 1c for introducing a P-type impurity so as to penetrate the diffusion region 1a and connecting the well 6 to a predetermined potential is provided. The formed diffusion regions 1a and 1c are respectively connected to an output terminal OUT (not shown) through a metal wiring layer 3a. With this configuration, the distributed constant resistance of the well 6 can be easily reduced to a low resistance, and the potential can be kept stable.

  On the other hand, the drain of the MOS transistor T1 is the same as the diffusion region 1a except that there is nothing corresponding to the diffusion region 1c, as shown in the sectional view along Y3-Y4 of FIG. A plurality of drain regions 1b are formed, and each drain region 1b is connected to a power supply voltage line VDD1 through a metal wiring layer 3b.

  In the above description, only the layout in the case of a one-layer wiring using an N-type semiconductor substrate is shown, but it can be formed in the same manner even in a semiconductor integrated circuit device using a P-type semiconductor substrate. In addition, the semiconductor integrated circuit device using the multilayer wiring technique having two or more metal wiring layers can be used similarly. In addition, the layout in which the diffusion layer 1c for connecting a predetermined potential to the well 6 is provided in all the source regions is shown. However, the diffusion layer 1c may be provided for each of the source regions or only in the peripheral part of the gate. Alternatively, the diffusion region 1c may be provided in a region other than the central portion of the diffusion region 1a. For example, a configuration in which a well region is provided or not provided in a source region in units of columns along the gate electrode is an example of this. In addition, well regions can be provided only in some of the plurality of source regions. As a result, a MOS transistor having the same current driving capability can be realized with a small area while reducing the resistance of the distributed constant of the well region. In addition, only the case where the shape of each source region 1a, drain region 1b, and connection hole 4 is a square is shown, but some invalid regions are formed even if the shape is a polygon other than a square such as a hexagon. The same effect can be expected just by ending up.

  Although only the output circuit of FIG. 2 is shown, the MOS transistor of the present invention may be used as the MOS transistor T2, an output circuit using a bipolar transistor instead of the MOS transistors T2 to T4, and other configurations. The output circuit may be used.

Explanatory drawing which shows the structure of the MOS transistor of the semiconductor integrated circuit device of this invention Circuit diagram showing output circuit example using MOS transistor Explanatory drawing showing a layout example of a conventional MOS transistor

Explanation of symbols

1a: diffusion region (source region)
1b: diffusion region (drain region)
1c: Diffusion region (backing contact)
2: Gate (polysilicon layer)
3a-3c: Metal wiring layer (aluminum layer)
4: Connection hole (contact)
5: Semiconductor substrate (substrate)
6: Well (P well)
7: Insulating film (LOCOS)
8: Protective film

Claims (2)

In a semiconductor integrated circuit device using a MOS transistor as a transistor for outputting a large current,
The source and drain of the transistor are formed by connecting a plurality of source and drain regions surrounded by a gate electrode in parallel,
The gate electrode is formed in a lattice shape to reduce its distributed constant resistance, and three or more total drain regions and source regions are provided around each source region or each drain region,
Each source region of the transistor is provided with a diffusion region for connecting the well region formed in the semiconductor substrate to a predetermined potential in order to reduce the distributed constant resistance value of the well region. A semiconductor integrated circuit device. In a semiconductor integrated circuit device using a MOS transistor as a transistor for outputting a large current,
The source and drain of the transistor are formed by connecting a plurality of source and drain regions surrounded by a gate electrode in parallel,
The gate electrode is formed in a lattice shape to reduce its distributed constant resistance, and three or more total drain regions and source regions are provided around each source region or each drain region,
Of the plurality of source regions of the transistor, the wells formed in the semiconductor substrate in order to reduce the resistance of the distributed constant of the well regions in some of the source regions that are not all the source regions. A semiconductor integrated circuit device, wherein a diffusion region for connecting the region to a predetermined potential is provided.

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