JP2005051170A - Group iii nitride compound semiconductor light emitting element - Google Patents

Group iii nitride compound semiconductor light emitting element Download PDF

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JP2005051170A
JP2005051170A JP2003284093A JP2003284093A JP2005051170A JP 2005051170 A JP2005051170 A JP 2005051170A JP 2003284093 A JP2003284093 A JP 2003284093A JP 2003284093 A JP2003284093 A JP 2003284093A JP 2005051170 A JP2005051170 A JP 2005051170A
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Tetsuya Taki
瀧  哲也
Kazuki Nishijima
和樹 西島
Masanobu Senda
昌伸 千田
Masaki Kojima
勝紀 小島
Yasuhisa Ushida
泰久 牛田
Takashi Ohashi
貴志 大橋
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Toyoda Gosei Co Ltd
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Abstract

<P>PROBLEM TO BE SOLVED: To improve electrostatic withstand voltage without lowering light emission property of a group III nitride compound semiconductor light emitting element. <P>SOLUTION: An n side multilayer (electrostatic withstand voltage improvement layer) 105 wherein five pairs of a 3 nm-thick layer 1051 consisting of nondoped In<SB>0.03</SB>Ga<SB>0.97</SB>N and a 20 nm-thick layer 1052 consisting of nondoped GaN are laminated is formed in a negative electrode side of a light emitting layer 106 of a multilayer quantum well structure wherein three pairs of a 3 nm-thick well layer 1061 consisting of nondoped In<SB>0.2</SB>Ga<SB>0.8</SB>N and a 20 nm-thick barrier layer 1062 consisting of nondoped GaN are laminated. In a positive electrode side of the light emitting layer 106, a p side multilayer (electrostatic withstand voltage improvement layer) 108 wherein a 3 nm-thick layer 1081 consisting of nondoped In<SB>0.03</SB>Ga<SB>0.97</SB>N and a 20 nm-thick layer 1082 consisting of nondoped GaN are laminated is formed. The n side multilayer 105 and the p side multilayer 108 allow an applied voltage to extend in a wide range of an n electrode side and a p electrode side of a light emitting layer without concentrating on a part of the n electrode side and the p electrode side of the light emitting layer. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

本発明はIII族窒化物系化合物半導体発光素子に関する。本発明は静電耐圧の高いIII族窒化物系化合物半導体発光素子構造を提供するものである。   The present invention relates to a group III nitride compound semiconductor light emitting device. The present invention provides a group III nitride compound semiconductor light emitting device structure having a high electrostatic withstand voltage.

緑、青乃至紫外領域の発光素子としてIII族窒化物系化合物半導体発光素子は汎用されつつあるが、発光強度以外のIII族窒化物系化合物半導体発光素子の諸特性は尚改善の余地がある。特に静電耐圧については、ガリウム・ヒ素系の発光素子やインジウム・リン系の発光素子に比較して格段に低く、大幅な静電耐圧の向上が期待されている。ここにおいて、III族窒化物系化合物半導体発光素子の静電耐圧の向上のため、下記のような提案がされている。
特開平11−191639号公報 特開2000−68594号公報 特開2000−244072号公報 特開2001−203385号公報
Although group III nitride compound semiconductor light emitting devices are being widely used as light emitting devices in the green, blue to ultraviolet region, there are still room for improvement in various characteristics of group III nitride compound semiconductor light emitting devices other than the emission intensity. In particular, the electrostatic withstand voltage is much lower than that of gallium / arsenic light emitting elements and indium / phosphorous light emitting elements, and a significant improvement in electrostatic withstand voltage is expected. Here, in order to improve the electrostatic withstand voltage of the group III nitride compound semiconductor light emitting device, the following proposals have been made.
Japanese Patent Laid-Open No. 11-191639 JP 2000-68594 A Japanese Patent Laid-Open No. 2000-244072 JP 2001-203385 A

これらの技術を以てしても尚III族窒化物系化合物半導体発光素子の静電耐圧は十分でなく、また、発光強度や駆動電圧に対し、静電耐圧はトレードオフの関係にある。   Even with these techniques, the electrostatic withstand voltage of the group III nitride compound semiconductor light emitting device is not sufficient, and the electrostatic withstand voltage is in a trade-off relationship with the light emission intensity and the driving voltage.

そこで本発明は上記従来技術に対し、発光強度や駆動電圧を悪化させることなく静電耐圧を向上させることを目的とする。   Therefore, the present invention has an object to improve the electrostatic withstand voltage without deteriorating the light emission intensity and the driving voltage with respect to the conventional technique.

上記の課題を解決するため、請求項1に記載の手段によれば、多重量子井戸構造の発光層を有するIII族窒化物系化合物半導体発光素子において、発光層のn電極側に、ノンドープのInx1Ga1-x1N(0<x1<1)から成る層とノンドープのGaNから成る層とのn側多重層を有し、発光層のp電極側に、ノンドープのInx2Ga1-x2N(0<x2<1)から成る層とノンドープのGaNから成る層とのp側多重層を有し、多重量子井戸構造の発光層の井戸層は少なくともインジウム(In)を含むIII族窒化物系化合物半導体AlyGa1-y-zInzN(0≦y<1, 0<z≦1)から成り、n側多重層を形成するInx1Ga1-x1N(0<x1<1)から成る層のインジウム(In)の組成x1とp側多重層を形成するInx2Ga1-x2N(0<x2<1)から成る層のインジウム(In)の組成x2は、いずれも、多重量子井戸構造の発光層の井戸層のインジウム(In)の組成zよりも小さいことを特徴とするIII族窒化物系化合物半導体発光素子である。 In order to solve the above-described problem, according to the means of claim 1, in a group III nitride compound semiconductor light emitting device having a light emitting layer having a multiple quantum well structure, a non-doped In region is formed on the n electrode side of the light emitting layer. x1 Ga 1-x1 N (0 <x1 <1) layer and non-doped GaN layer n-side multiple layers, and non-doped In x2 Ga 1-x2 N on the p-electrode side of the light emitting layer A III-nitride group having a p-side multiple layer of a layer made of (0 <x2 <1) and a layer made of non-doped GaN, and the well layer of the light emitting layer of the multiple quantum well structure contains at least indium (In) Compound semiconductor Al y Ga 1-yz In z N (0 ≦ y <1, 0 <z ≦ 1) and In x1 Ga 1-x1 N (0 <x1 <1) forming an n-side multilayer The indium (In) composition x1 of the layer and the indium (In) composition x2 of In x2 Ga 1-x2 N (0 <x2 <1) forming the p-side multilayer are both multiquantum wells. Structure light emitting layer well layer It is a Group III nitride compound semiconductor light-emitting device according to claim less than the composition z of beam (an In).

また、請求項2に記載の手段によれば、n側多重層のノンドープのInx1Ga1-x1N(0<x1<1)から成る層のインジウム(In)の組成x1と、p側多重層のノンドープのInx2Ga1-x2N(0<x2<1)から成る層のインジウム(In)の組成x2は、いずれも、0.02以上0.07以下であることを特徴とする。また、請求項3に記載の手段によれば、n側多重層のノンドープのInx1Ga1-x1N(0<x1<1)から成る層の厚さと、p側多重層のノンドープのInx2Ga1-x2N(0<x2<1)から成る層の厚さは、いずれも、0.5nm以上6nm以下であることを特徴とする。 According to the second aspect of the present invention, the composition x1 of indium (In) in the layer made of non-doped In x1 Ga 1 -x1 N (0 <x1 <1) in the n-side multilayer, and the p-side multiple The composition x2 of indium (In) in the layer made of non-doped In x2 Ga 1-x2 N (0 <x2 <1) in the multilayer is 0.02 or more and 0.07 or less. According to the third aspect of the present invention, the thickness of the n-side multilayer non-doped In x1 Ga 1-x1 N (0 <x1 <1) and the p-side multilayer non-doped In x2 The thickness of each layer made of Ga 1-x2 N (0 <x2 <1) is 0.5 nm or more and 6 nm or less.

また、請求項4に記載の手段によれば、n側多重層のノンドープのInx1Ga1-x1N(0<x1<1)から成る層の厚さの発光層の井戸層の厚さに対する比と、p側多重層のノンドープのInx2Ga1-x2N(0<x2<1)から成る層の厚さの発光層の井戸層の厚さに対する比は、いずれも、0.1以上2以下であることを特徴とする。また、請求項5に記載の手段によれば、n側多重層のノンドープのGaNから成る層の厚さの発光層の障壁層の厚さに対する比と、p側多重層のノンドープのGaNから成る層の厚さの発光層の障壁層の厚さに対する比は、いずれも、0.5以上4以下であることを特徴とする。また、請求項6に記載の手段によれば、n側多重層のノンドープのInx1Ga1-x1N(0<x1<1)から成る層の数と、p側多重層のノンドープのInx2Ga1-x2N(0<x2<1)から成る層の数は、いずれも、1以上7以下であることを特徴とする。 According to the fourth aspect of the present invention, the thickness of the layer composed of non-doped In x1 Ga 1 -x1 N (0 <x1 <1) in the n-side multilayer is relative to the thickness of the well layer of the light emitting layer. And the ratio of the thickness of the p-side multi-layered non-doped In x2 Ga 1-x2 N (0 <x2 <1) to the thickness of the well layer of the light emitting layer are both 0.1 or more and 2 or less It is characterized by being. According to the means of claim 5, the ratio of the thickness of the n-side multilayer non-doped GaN layer to the thickness of the light-emitting barrier layer and the p-side multilayer non-doped GaN The ratio of the thickness of the light emitting layer to the thickness of the barrier layer is 0.5 to 4 in all cases. According to the means of claim 6, the number of layers of non-doped In x1 Ga 1-x1 N (0 <x1 <1) in the n-side multilayer, and the non-doped In x2 in the p-side multilayer. The number of layers made of Ga 1-x2 N (0 <x2 <1) is 1 or more and 7 or less.

また、請求項7に記載の手段によれば、発光層とn側多重層の間に、ドナー不純物がドープされた層を有することを特徴とする。また、請求項8に記載の手段によれば、ドナー不純物がドープされた層は、各々が5nm以下の厚さであって組成の異なる2種類以上のIII族窒化物系化合物半導体層が積層された超格子層であることを特徴とする。   According to a seventh aspect of the present invention, a layer doped with a donor impurity is provided between the light emitting layer and the n-side multilayer. According to the eighth aspect of the present invention, the layer doped with the donor impurity is formed by stacking two or more group III nitride compound semiconductor layers each having a thickness of 5 nm or less and different compositions. It is a superlattice layer.

また、請求項9に記載の手段によれば、発光層とp側多重層の間に、アクセプタ不純物がドープされた層を有することを特徴とする。また、請求項10に記載の手段によれば、アクセプタ不純物がドープされた層は、各々が5nm以下の厚さであって組成の異なる2種類以上のIII族窒化物系化合物半導体層が積層された超格子層であることを特徴とする。   According to a ninth aspect of the present invention, a layer doped with an acceptor impurity is provided between the light emitting layer and the p-side multilayer. According to the means of claim 10, the layers doped with acceptor impurities are laminated with two or more types of group III nitride compound semiconductor layers each having a thickness of 5 nm or less and different compositions. It is a superlattice layer.

以下の実施例に示す通り、本願発明の発光層を形成するインジウム(In)を含むIII族窒化物系化合物半導体AlyGa1-y-zInzN(0≦y<1, 0<z≦1)から成る井戸層の、インジウム(In)組成zよりもインジウム(In)の組成の小さいノンドープのInx1Ga1-x1N(0<x1<1)から成る層とノンドープのGaNから成る層との多重層(n側多重層)を発光層のn電極側に設け、インジウム(In)組成zよりもインジウム(In)の組成の小さいノンドープのInx2Ga1-x2N(0<x2<1)から成る層とノンドープのGaNから成る層との多重層(p側多重層)を発光層のp電極側に設けることで、静電耐圧が著しく向上し、発光強度や駆動電圧の悪化しないIII族窒化物系化合物半導体発光素子を得ることができた。このような効果を生ずる作用については、印加電圧が発光層のn電極側の一部やp電極側の一部に集中することなく、発光層のn電極側及びp電極側のそれぞれの広い範囲に広がる作用を本願発明の多重層が奏するものと考えられる。 As shown in the following examples, the group III nitride compound semiconductor Al y Ga 1-yz In z N (0 ≦ y <1, 0 <z ≦ 1 containing indium (In) forming the light emitting layer of the present invention. ), A layer made of non-doped In x1 Ga 1-x1 N (0 <x1 <1) having a smaller indium (In) composition than the indium (In) composition z, and a layer made of non-doped GaN, A non-doped In x2 Ga 1-x2 N (0 <x2 <1) in which the indium (In) composition z is smaller than the indium (In) composition z. ) And a non-doped GaN layer (p-side multi-layer) on the p-electrode side of the light-emitting layer, the electrostatic withstand voltage is remarkably improved, and the light emission intensity and drive voltage do not deteriorate III A group nitride compound semiconductor light emitting device could be obtained. With respect to the action that produces such an effect, the applied voltage is not concentrated on a part of the light emitting layer on the n electrode side or a part of the p electrode side, and a wide range on each of the n electrode side and the p electrode side of the light emitting layer. It is considered that the multi-layer of the present invention has an effect spreading to the above.

発光層とn側多重層の間にn型層を設けても良く、発光層とp側多重層の間にp型層を設けても良い。これらの層を設けた場合は、各々、いわゆるクラッド層やガイド層の働きをさせることができる。これらの層は多重層や超格子層で形成しても良い。   An n-type layer may be provided between the light emitting layer and the n-side multiple layer, and a p-type layer may be provided between the light-emitting layer and the p-side multiple layer. When these layers are provided, the so-called clad layer and guide layer can each function. These layers may be formed of multiple layers or superlattice layers.

本発明の好ましい実施の形態について説明する。まず、本願で用いる「ノンドープ」の語は、意図的に当該層を形成する際にドーパント不純物を導入しないの意に留まり、何らかの技術的理由で「ドーパント」が混入するものを排除するものではない。当該技術的理由としては近接する層からのマイグレーションや、異なる層を形成する境界時における導入原料の切り替えが完全でないことによるコンタミネーション、或いは製造装置の洗浄不良等により「常に」微量に生成するコンタミネーションがあげられる。これら意図的でなく「ドーパント」が混入した層は、実質的には本願で言う「ノンドープ層」に包含されるものとする。   A preferred embodiment of the present invention will be described. First of all, the term “non-doped” used in the present application does not mean that dopant impurities are not introduced when intentionally forming the layer, and does not exclude the case where “dopant” is mixed for some technical reason. . The technical reason is that contamination is always generated in a very small amount due to contamination from adjacent layers, contamination due to incomplete switching of the raw material introduced at the boundary where different layers are formed, or defective cleaning of the manufacturing equipment. Nation is given. These unintentionally mixed layers containing “dopants” are substantially included in the “non-doped layer” referred to in the present application.

発光層を構成する多重量子井戸構造は、少なくともインジウム(In)を含むIII族窒化物系化合物半導体AlyGa1-y-zInzN(0≦y<1, 0<z≦1)から成る井戸層を含むものである。発光層の構成は、例えばドープされた、又はアンドープのGa1-zInzN(0<z≦1)から成る井戸層と、当該井戸層よりもバンドギャップの大きい任意の組成のIII族窒化物系化合物半導体AlGaInNから成る障壁層が挙げられる。好ましい例としてはアンドープのGa1-zInzN(0<z≦1)の井戸層とアンドープのGaNから成る障壁層である。 The multiple quantum well structure constituting the light emitting layer is a well composed of a group III nitride compound semiconductor Al y Ga 1-yz In z N (0 ≦ y <1, 0 <z ≦ 1) containing at least indium (In) Includes layers. The structure of the light emitting layer includes, for example, a well layer made of doped or undoped Ga 1-z In z N (0 <z ≦ 1), and a group III nitride having an arbitrary composition having a larger band gap than the well layer. Examples thereof include a barrier layer made of a physical compound semiconductor AlGaInN. A preferable example is an undoped Ga 1-z In z N (0 <z ≦ 1) well layer and a barrier layer made of undoped GaN.

本発明の主たる特徴である発光層のn電極側に設けられるn側多重層と、p電極側に設けられるp側多重層は、次のように形成される。発光層を形成する少なくともインジウム(In)を含むIII族窒化物系化合物半導体AlyGa1-y-zInzN(0≦y<1, 0<z≦1)から成る井戸層のインジウム(In)の組成zよりも小さいインジウム(In)の組成x1のノンドープのInx1Ga1-x1N(0<x1<1)から成る層とノンドープのGaNから成る層によりn側多重層は形成される。また、同じく、発光層を形成する井戸層のインジウム(In)の組成zよりも小さいインジウム(In)の組成x2のノンドープのInx2Ga1-x2N(0<x2<1)から成る層とノンドープのGaNから成る層によりp側多重層は形成される。このとき、n側多重層を形成するノンドープのInx1Ga1-x1N(0<x1<1)から成る層のインジウム(In)の組成x1と、p側多重層を形成するノンドープのInx2Ga1-x2N(0<x2<1)から成る層のインジウム(In)の組成x2は、いずれも、0.02以上0.07以下が好ましく、0.03以上0.05以下がより好ましい。 The n-side multiple layer provided on the n-electrode side of the light emitting layer and the p-side multiple layer provided on the p-electrode side, which are the main features of the present invention, are formed as follows. Group III nitride compound semiconductor Al y Ga 1-yz In z N (0 ≦ y <1, 0 <z ≦ 1) containing at least indium (In) forming the light emitting layer Indium (In) in the well layer An n-side multiple layer is formed by a layer made of non-doped In x1 Ga 1 -x1 N (0 <x1 <1) having a composition x1 of indium (In) smaller than the composition z of and a layer made of non-doped GaN. Similarly, a layer composed of non-doped In x2 Ga 1-x2 N (0 <x2 <1) having an indium (In) composition x2 smaller than the indium (In) composition z of the well layer forming the light emitting layer, The p-side multilayer is formed by a layer made of non-doped GaN. At this time, the composition x1 of indium (In) of the layer made of non-doped In x1 Ga 1-x1 N (0 <x1 <1) that forms the n-side multilayer, and the non-doped In x2 that forms the p-side multilayer. The indium (In) composition x2 of the layer composed of Ga 1-x2 N (0 <x2 <1) is preferably 0.02 or more and 0.07 or less, and more preferably 0.03 or more and 0.05 or less.

発光層のn電極側に設けられるn側多重層のノンドープのInx1Ga1-x1N(0<x1<1)から成る層の膜厚と発光層のp電極側に設けられるp側多重層のノンドープのInx2Ga1-x2N(0<x2<1)から成る層の膜厚は、いずれも、0.5nm以上6nm以下であることが好ましく、0.5nm以上4nm以下であることがより好ましい。以下に発光特性を記すが、ノンドープのInx1Ga1-x1N(0<x1<1)から成る層の膜厚が6nmを越えると駆動電圧Vfが大幅に上昇することが判明している。これはノンドープのInx2Ga1-x2N(0<x2<1)から成る層の膜厚についても同様と考えられる。これらの膜厚が0.5nm未満となると、その膜厚の調整が困難となるので、避けるべきである。 Film thickness of non-doped In x1 Ga 1-x1 N (0 <x1 <1) in the n-side multi-layer provided on the n-electrode side of the light-emitting layer and p-side multi-layer provided on the p-electrode side of the light-emitting layer The thickness of the non-doped In x2 Ga 1-x2 N (0 <x2 <1) layer is preferably 0.5 nm or more and 6 nm or less, and more preferably 0.5 nm or more and 4 nm or less. . The light emission characteristics are described below. It has been found that the drive voltage Vf significantly increases when the thickness of the layer made of non-doped In x1 Ga 1-x1 N (0 <x1 <1) exceeds 6 nm. This is considered to be the same for the film thickness of the layer made of non-doped In x2 Ga 1 -x2 N (0 <x2 <1). If these film thicknesses are less than 0.5 nm, it is difficult to adjust the film thickness, and should be avoided.

一方、n側多重層のノンドープのGaNから成る層の膜厚は、少なくとも10〜40nmの範囲では素子特性に大きな変化を生じないことが判明している。これはp側多重層のノンドープのGaNから成る層の膜厚についても同様と考えられる。   On the other hand, it has been found that the film thickness of the n-side multi-layered layer made of non-doped GaN does not significantly change the device characteristics in the range of at least 10 to 40 nm. This is considered to be the same for the film thickness of the p-side multi-layered layer made of non-doped GaN.

n側多重層のノンドープのInx1Ga1-x1N(0<x1<1)から成る層の厚さの発光層の井戸層の厚さに対する比と、p側多重層のノンドープのInx2Ga1-x2N(0<x2<1)から成る層の厚さの発光層の井戸層の厚さに対する比は、いずれも、0.1以上2以下とすることが望ましい。より望ましくは発光層の井戸層の厚さ以下に、n側多重層のノンドープのInx1Ga1-x1N(0<x1<1)から成る層の厚さと、p側多重層のノンドープのInx2Ga1-x2N(0<x2<1)から成る層の厚さを調節する。一方、n側多重層とp側多重層のノンドープのGaNから成る層の厚さの発光層の障壁層の厚さに対する比は、いずれも、0.5以上4以下であることが望ましい。より望ましくは発光層の障壁層の厚さ以上にn側多重層とp側多重層のノンドープのGaNから成る層の厚さを調節することが望ましい。 The ratio of the layer thickness of the non-doped In x1 Ga 1-x1 N (0 <x1 <1) of the n-side multilayer to the thickness of the well layer of the light-emitting layer and the non-doped In x2 Ga of the p-side multilayer The ratio of the thickness of the layer made of 1-x2 N (0 <x2 <1) to the thickness of the well layer of the light emitting layer is preferably 0.1 or more and 2 or less. More preferably, the thickness of the n-side multi-layer non-doped In x1 Ga 1-x1 N (0 <x1 <1) and the p-side multi-layer non-doped In are less than the thickness of the well layer of the light-emitting layer. adjusting the x2 Ga 1-x2 N thickness of the layer made of (0 <x2 <1). On the other hand, the ratio of the thickness of the non-doped GaN layer of the n-side multilayer and the p-side multilayer to the thickness of the barrier layer of the light emitting layer is preferably 0.5 or more and 4 or less. More preferably, it is desirable to adjust the thicknesses of the non-doped GaN layers of the n-side multilayer and the p-side multilayer to be greater than the thickness of the barrier layer of the light emitting layer.

発光層のn電極側に設けられるn側多重層のノンドープのInx1Ga1-x1N(0<x1<1)から成る層の数とp電極側に設けられるp側多重層のノンドープのInx2Ga1-x2N(0<x2<1)から成る層の数は1以上7以下とすることが望ましく、より好ましくは1以上5以下とすると良い。 The number of layers of non-doped In x1 Ga 1-x1 N (0 <x1 <1) in the n-side multilayer provided on the n-electrode side of the light emitting layer and the non-doped In of the p-side multilayer provided on the p-electrode side x2 Ga 1-x2 N number of layers made of (0 <x2 <1) is preferably set to be 1 to 7, more preferably equal to 1 to 5.

発光層とn側多重層の間、発光層とp側多重層の間にクラッドとして働くドナーを添加した層、アクセプタを添加した層を設けても良い。nクラッド層としてはAlGaN:Si、pクラッド層としてはAlGaN:Mgの単層を両方、又はいずれか一方を設けても良い。一般的にIII族窒化物系化合物半導体は、電子濃度に比べ、ホール濃度を高くすることが困難であるので、pクラッド層を設けることが適当である。尚、n側のクラッド層は、n側多重層の発光層とは反対側であるよりn電極に近い側に設けても良く、p側のクラッド層は、p側多重層の発光層とは反対側であるよりp電極に近い側に設けても良い。   Between the light-emitting layer and the n-side multilayer, a layer added with a donor acting as a clad or a layer added with an acceptor may be provided between the light-emitting layer and the p-side multilayer. Both or one of AlGaN: Si as the n-cladding layer and AlGaN: Mg as the p-cladding layer may be provided. Generally, it is difficult to increase the hole concentration of a group III nitride compound semiconductor as compared with the electron concentration. Therefore, it is appropriate to provide a p-cladding layer. The n-side cladding layer may be provided on the side closer to the n-electrode than the light-emitting layer of the n-side multilayer, and the p-side cladding layer is different from the light-emitting layer of the p-side multilayer. It may be provided on the side closer to the p-electrode than on the opposite side.

発光層とn側多重層の間に設けるnクラッド層は超格子層とすることができる。例えば1〜5nm厚のAlGaN:Siと1〜5nm厚のInGaN:Siを積層して形成することができる。同様に、発光層とp側多重層の間に設けるpクラッド層を、例えば1〜5nm厚のAlGaN:Mgと1〜5nm厚のInGaN:Mgを積層して超格子層として形成することができる。   The n clad layer provided between the light emitting layer and the n-side multilayer can be a superlattice layer. For example, AlGaN: Si having a thickness of 1 to 5 nm and InGaN: Si having a thickness of 1 to 5 nm can be stacked. Similarly, the p-cladding layer provided between the light-emitting layer and the p-side multilayer can be formed as a superlattice layer by laminating, for example, 1 to 5 nm thick AlGaN: Mg and 1 to 5 nm thick InGaN: Mg. .

本発明に係るIII族窒化物系化合物半導体発光素子は、上記の発明の主たる構成に係る限定の他は、任意の構成を取ることができる。また、発光素子は発光ダイオード(LED)、レーザダイオード(LD)、フォトカプラその他の任意の発光素子として良い。特に本発明に係るIII族窒化物系化合物半導体発光素子の製造方法としては任意の製造方法を用いることができる。   The group III nitride compound semiconductor light-emitting device according to the present invention can have any configuration other than the limitation related to the main configuration of the present invention. The light emitting element may be a light emitting diode (LED), a laser diode (LD), a photocoupler, or any other light emitting element. In particular, any manufacturing method can be used as a method for manufacturing a group III nitride compound semiconductor light emitting device according to the present invention.

具体的には、結晶成長させる基板としては、サファイヤ、スピネル、Si、SiC、ZnO、MgO或いは、III族窒化物系化合物単結晶等を用いることができる。III族窒化物系化合物半導体層を結晶成長させる方法としては、分子線気相成長法(MBE)、有機金属気相成長法(MOVPE)、ハイドライド気相成長法(HVPE)、液相成長法等が有効である。   Specifically, sapphire, spinel, Si, SiC, ZnO, MgO, a group III nitride compound single crystal, or the like can be used as a substrate for crystal growth. As a method for crystal growth of the group III nitride compound semiconductor layer, molecular beam vapor phase epitaxy (MBE), metalorganic vapor phase epitaxy (MOVPE), hydride vapor phase epitaxy (HVPE), liquid phase epitaxy, etc. Is effective.

電極形成層等のIII族窒化物半導体層は、少なくともAlxGayIn1-x-yN(0≦x≦1, 0≦y≦1, 0≦x+y≦1)にて表される2元系、3元系若しくは4元系の半導体から成るIII族窒化物系化合物半導体で形成することができる。また、これらのIII族元素の一部は、ボロン(B)、タリウム(Tl)で置き換えても良く、また、窒素(N)の一部をリン(P)、砒素(As)、アンチモン(Sb)、ビスマス(Bi)で置き換えても良い。 Group III nitride semiconductor layer of the electrode forming layer and the like is expressed by at least Al x Ga y In 1-xy N (0 ≦ x ≦ 1, 0 ≦ y ≦ 1, 0 ≦ x + y ≦ 1) 2 A group III nitride compound semiconductor made of a ternary, ternary, or quaternary semiconductor can be used. Some of these group III elements may be replaced by boron (B) and thallium (Tl), and part of nitrogen (N) may be phosphorus (P), arsenic (As), antimony (Sb ) Or bismuth (Bi).

更に、これらの半導体を用いてn型のIII族窒化物系化合物半導体層を形成する場合には、n型不純物として、Si、Ge、Se、Te、C等を添加し、p型不純物としては、Zn、Mg、Be、Ca、Sr、Ba等を添加することができる。   Further, when an n-type group III nitride compound semiconductor layer is formed using these semiconductors, Si, Ge, Se, Te, C, etc. are added as n-type impurities, and p-type impurities are used as p-type impurities. Zn, Mg, Be, Ca, Sr, Ba and the like can be added.

以上の本発明の手段により、前記の課題を効果的、或いは合理的に解決することができる。   By the above means of the present invention, the above-mentioned problem can be effectively or rationally solved.

図1に、本発明の実施例に係る半導体発光素子100の模式的な断面図を示す。半導体発光素子100では、図1に示す様に、厚さ約300μmのサファイヤ基板101の上に、窒化アルミニウム(AlN)から成る膜厚約15nmのバッファ層102が成膜され、その上にノンドープのGaNから成る膜厚約500nmの層103が成膜され、その上にシリコン(Si)を1×1018/cm3ドープしたGaNから成る膜厚約5μmのn型コンタクト層104(高キャリヤ濃度n+層)が形成されている。 FIG. 1 is a schematic cross-sectional view of a semiconductor light emitting device 100 according to an embodiment of the present invention. In the semiconductor light emitting device 100, as shown in FIG. 1, a buffer layer 102 made of aluminum nitride (AlN) and having a thickness of about 15 nm is formed on a sapphire substrate 101 having a thickness of about 300 μm. A layer 103 made of GaN having a thickness of about 500 nm is formed, and an n-type contact layer 104 having a thickness of about 5 μm made of GaN doped with silicon (Si) at 1 × 10 18 / cm 3 (high carrier concentration n). + Layer) is formed.

また、このn型コンタクト層104の上には、膜厚3nmのノンドープIn0.03Ga0.97Nから成る層1051と膜厚20nmのノンドープGaNから成る層1052とを5ペア積層したn側多重層(静電耐圧向上層)105が形成されている。更にその上には、膜厚3nmのノンドープIn0.2Ga0.8Nから成る井戸層1061と膜厚20nmのノンドープGaNから成る障壁層1062とを3ペア積層して多重量子井戸構造の発光層106が形成されている。 Further, on this n-type contact layer 104, an n-side multiple layer (static structure) in which five pairs of a layer 1051 made of non-doped In 0.03 Ga 0.97 N with a thickness of 3 nm and a layer 1052 made of non-doped GaN with a thickness of 20 nm are stacked. An electric withstand voltage improvement layer) 105 is formed. Further thereon, three pairs of a well layer 1061 made of non-doped In 0.2 Ga 0.8 N with a thickness of 3 nm and a barrier layer 1062 made of non-doped GaN with a thickness of 20 nm are stacked to form a light emitting layer 106 having a multiple quantum well structure. Has been.

更に、この発光層106の上には、Mgを2×1019/cm3ドープした膜厚25nmのp型Al0.15Ga0.85Nから成るp型層107が形成されている。p型層107の上には、膜厚3nmのノンドープIn0.03Ga0.97Nから成る層1081と膜厚20nmのノンドープGaNから成る層1082とを5ペア積層したp側多重層(静電耐圧向上層)108が形成されている。p側多重層(静電耐圧向上層)108の上には、Mgを8×1019ドープした膜厚100nmのp型GaNから成るp型コンタクト層109を形成した。 Further, a p-type layer 107 made of p-type Al 0.15 Ga 0.85 N having a thickness of 25 nm doped with Mg 2 × 10 19 / cm 3 is formed on the light emitting layer 106. On the p-type layer 107, a p-side multiple layer (an electrostatic breakdown voltage improving layer) in which five pairs of a layer 1081 made of non-doped In 0.03 Ga 0.97 N with a thickness of 3 nm and a layer 1082 made of non-doped GaN with a thickness of 20 nm are stacked. ) 108 is formed. A p-type contact layer 109 made of 100-nm-thick p-type GaN doped with 8 × 10 19 Mg was formed on the p-side multilayer (electrostatic withstand voltage improving layer) 108.

又、p型コンタクト層108の上には金属蒸着による透光性薄膜p電極110が、n型コンタクト層104上にはn電極140が形成されている。透光性薄膜p電極110は、p型コンタクト層109に直接接合する膜厚約1.5nmのコバルト(Co)より成る第1層111と、このコバルト膜に接合する膜厚約6nmの金(Au)より成る第2層112とで構成されている。   Further, a light-transmitting thin film p-electrode 110 formed by metal vapor deposition is formed on the p-type contact layer 108, and an n-electrode 140 is formed on the n-type contact layer 104. The translucent thin film p-electrode 110 includes a first layer 111 made of cobalt (Co) having a thickness of about 1.5 nm directly bonded to the p-type contact layer 109 and a gold (Au) having a thickness of about 6 nm bonded to the cobalt film. ) And the second layer 112.

厚膜p電極120は、膜厚約18nmのバナジウム(V)より成る第1層121と、膜厚約15μmの金(Au)より成る第2層122と、膜厚約10nmのアルミニウム(Al)より成る第3層123とを透光性薄膜p電極110の上から順次積層させることにより構成されている。   The thick p-electrode 120 includes a first layer 121 made of vanadium (V) having a thickness of about 18 nm, a second layer 122 made of gold (Au) having a thickness of about 15 μm, and aluminum (Al) having a thickness of about 10 nm. The third layer 123 is formed by sequentially laminating the translucent thin film p-electrode 110 from above.

多層構造のn電極140は、n型コンタクト層104の一部露出された部分の上から、膜厚約18nmのバナジウム(V)より成る第1層141と膜厚約100nmのアルミニウム(Al)より成る第2層142とを積層させることにより構成されている。   The n-electrode 140 having a multilayer structure is formed from a first layer 141 made of vanadium (V) having a thickness of about 18 nm and aluminum (Al) having a thickness of about 100 nm from above a part of the n-type contact layer 104 which is partially exposed. It is comprised by laminating | stacking the 2nd layer 142 which consists.

また、最上部には、SiO2膜より成る保護膜130が形成されている。サファイヤ基板101の底面に当たる外側の最下部には、膜厚約500nmのアルミニウム(Al)より成る反射金属層150が、金属蒸着により成膜されている。尚、この反射金属層150は、Rh、Ti、W等の金属の他、TiN、HfN等の窒化物でも良い。 A protective film 130 made of a SiO 2 film is formed on the top. A reflective metal layer 150 made of aluminum (Al) having a thickness of about 500 nm is formed by metal vapor deposition on the outermost lowermost portion corresponding to the bottom surface of the sapphire substrate 101. The reflective metal layer 150 may be a metal such as Rh, Ti, or W, or a nitride such as TiN or HfN.

このような構造の図1の半導体発光素子100を数固作成し、静電耐圧をマシーンモデル式により0Ω、200F、30nsのパルス電圧により測定しところ、その静電耐圧は400乃至600Vであった。この結果を図3の右側(「n側及びp側」と示したもの)に示す。
〔比較例〕
比較のため、図2に示す半導体発光素子900を数固作成した。図2の半導体発光素子900は、図1の半導体発光素子100の構成から、p型層107とp型コンタクト層109の間のp側多重層(静電耐圧向上層)108を除いたものであり、他の構成は同一である。半導体発光素子900の静電耐圧をマシーンモデル式により0Ω、200F、30nsのパルス電圧により測定しところ、その静電耐圧は130乃至200Vであった。この結果を図3の左側(「n側のみ」と示したもの)に示す。ここから、静電耐圧向上層は、n側のみではなく、n側とp側両方に設けることが効果的であり、且つ極めて高い静電耐圧が得られることがわかった。
〔実施例に対する他の多重層構成との比較〕
上記実施例についての静電耐圧、駆動電圧Vf、全放射束(発光強度)を、多重層構成を一部変更した場合と比較して以下、図に説明する。尚、静電耐圧はマシーンモデル式により0Ω、200F、30nsのパルス電圧により測定した。尚、測定に用いた半導体発光素子の構成は図2の半導体発光素子900の構成とし、静電耐圧向上層としてn側多重層105 の層構成を種々替えて行った。
Several semiconductor light emitting devices 100 of FIG. 1 having such a structure were prepared, and the electrostatic withstand voltage was measured with a pulse voltage of 0Ω, 200F, 30 ns by a machine model equation, and the electrostatic withstand voltage was 400 to 600V. . The results are shown on the right side of FIG. 3 (shown as “n side and p side”).
[Comparative Example]
For comparison, several semiconductor light emitting devices 900 shown in FIG. 2 were prepared. The semiconductor light emitting device 900 of FIG. 2 is obtained by removing the p-side multi-layer (electrostatic withstand voltage improving layer) 108 between the p-type layer 107 and the p-type contact layer 109 from the configuration of the semiconductor light emitting device 100 of FIG. Yes, the other configurations are the same. The electrostatic withstand voltage of the semiconductor light emitting device 900 was measured with a pulse voltage of 0Ω, 200F, and 30 ns by a machine model equation, and the electrostatic withstand voltage was 130 to 200V. The results are shown on the left side of FIG. 3 (shown as “n side only”). From this, it was found that it is effective to provide the electrostatic withstand voltage improving layer not only on the n side but on both the n side and the p side, and an extremely high electrostatic withstand voltage can be obtained.
[Comparison with other multi-layer configurations for Examples]
The electrostatic withstand voltage, the driving voltage Vf, and the total radiant flux (emission intensity) for the above embodiment will be described below with reference to the drawings in comparison with the case where the multilayer structure is partially changed. The electrostatic withstand voltage was measured with a pulse voltage of 0Ω, 200F, and 30 ns by a machine model equation. The configuration of the semiconductor light emitting device used for the measurement was the same as the configuration of the semiconductor light emitting device 900 of FIG. 2, and the layer configuration of the n-side multi-layer 105 was variously changed as the electrostatic breakdown voltage improving layer.

図4(a)、(b)、(c)はそれぞれ、上記実施例の素子についての静電耐圧、駆動電圧Vf、全放射束を、膜厚3nmのノンドープIn0.03Ga0.97Nから成る層1051の膜厚に関し、1.5nmから10nmの場合を示した図である。ノンドープIn0.03Ga0.97Nから成る層1051は、膜厚を1.5nmから3nmとした素子の場合に静電耐圧を高く、駆動電圧Vfを低くできるが、膜厚を10nmとした素子の場合は静電耐圧が若干低く、駆動電圧Vfが高くなってしまう結果が得られた。一方、全放射束(発光強度)については膜厚に対して大きく左右されなかった。 FIGS. 4A, 4B, and 4C show a layer 1051 made of non-doped In 0.03 Ga 0.97 N having a film thickness of 3 nm for the electrostatic breakdown voltage, drive voltage Vf, and total radiant flux of the device of the above-described embodiment. FIG. 5 is a diagram showing a case where the film thickness is 1.5 nm to 10 nm. The layer 1051 composed of non-doped In 0.03 Ga 0.97 N has a high electrostatic withstand voltage and a low driving voltage Vf in the case of an element having a film thickness of 1.5 to 3 nm, but is static in the case of an element having a film thickness of 10 nm. As a result, the withstand voltage was slightly low and the drive voltage Vf was high. On the other hand, the total radiant flux (luminescence intensity) was not greatly affected by the film thickness.

図5(a)、(b)、(c)はそれぞれ、上記実施例の素子についての静電耐圧、駆動電圧Vf、全放射束を、膜厚3nmのノンドープIn0.03Ga0.97N(In組成3%)から成る層1051のIn組成に関し、0.01(1%)から0.08(8%)の場合を示した図である。ノンドープInGaNから成る層1051は、In組成を0.03(3%)から0.05(5%)とした素子の場合に駆動電圧Vfを低くできるが、In組成を0.01(1%)又は0.08(8%)とした素子の場合は駆動電圧Vfが高くなってしまう結果が得られた。一方、全放射束(発光強度)については膜厚に対して大きく左右されなかった。静電耐圧については駆動電圧Vfが好適な範囲で、若干向上した。 5A, 5B, and 5C show the electrostatic withstand voltage, drive voltage Vf, and total radiant flux for the element of the above example, respectively, for non-doped In 0.03 Ga 0.97 N (In composition 3 It is the figure which showed the case of 0.01 (1%) to 0.08 (8%) regarding In composition of the layer 1051 which consists of%). The layer 1051 made of non-doped InGaN can reduce the driving voltage Vf in the case of an element having an In composition of 0.03 (3%) to 0.05 (5%), but the In composition is 0.01 (1%) or 0.08 (8%). In the case of the element, the result that the drive voltage Vf was high was obtained. On the other hand, the total radiant flux (luminescence intensity) was not greatly affected by the film thickness. With respect to the electrostatic withstand voltage, the driving voltage Vf was slightly improved within a suitable range.

図6(a)、(b)、(c)はそれぞれ、上記実施例の素子についての静電耐圧、駆動電圧Vf、全放射束を、膜厚20nmのノンドープGaNから成る層1052にシリコン(Si)を1×1018/cm3ドープした素子の場合とともに示した図である。GaNから成る層1052はノンドープとした素子の場合に駆動電圧を低くできるが、シリコンを(Si)を1×1018/cm3ドープした素子の場合は駆動電圧Vfが高くなってしまう結果が得られた。一方、静電耐圧と全放射束(発光強度)は、ドープ/ノンドープの違いに対して大きく左右されなかった。 FIGS. 6A, 6B, and 6C show the electrostatic withstand voltage, drive voltage Vf, and total radiant flux for the device of the above-described embodiment in a silicon layer (Si) (Si) ) Along with the case of a device doped with 1 × 10 18 / cm 3 . The GaN layer 1052 can reduce the driving voltage in the case of a non-doped element, but the driving voltage Vf is increased in the case of an element doped with silicon (Si) at 1 × 10 18 / cm 3. It was. On the other hand, the electrostatic withstand voltage and the total radiant flux (emission intensity) were not greatly affected by the difference between doped / non-doped.

図7(a)、(b)、(c)はそれぞれ、上記実施例の素子についての静電耐圧、駆動電圧Vf、全放射束を、膜厚3nmのノンドープIn0.03Ga0.97Nから成る層1051にシリコン(Si)を1×1018/cm3ドープした素子の場合とともに示した図である。In0.03Ga0.97Nから成る層1051はノンドープとした場合に静電耐圧を高く、駆動電圧を低くできるが、シリコン(Si)を1×1018/cm3ドープした素子の場合は静電耐圧が低く、駆動電圧Vfが高くなってしまう結果が得られた。一方、全放射束(発光強度)は、ドープ/ノンドープの違いに対して大きく左右されなかった。 FIGS. 7A, 7B and 7C respectively show the electrostatic withstand voltage, the driving voltage Vf, and the total radiant flux of the element of the above-described embodiment, and a layer 1051 made of non-doped In 0.03 Ga 0.97 N having a thickness of 3 nm. FIG. 5 is a diagram showing the case of an element doped with silicon (Si) at 1 × 10 18 / cm 3 . The layer 1051 composed of In 0.03 Ga 0.97 N has a high electrostatic withstand voltage when it is not doped, and can reduce the driving voltage. However, in the case of an element doped with silicon (Si) 1 × 10 18 / cm 3 , the electrostatic withstand voltage is low. As a result, the driving voltage Vf was increased. On the other hand, the total radiant flux (luminescence intensity) was not greatly affected by the difference between doped and non-doped.

図8(a)、(b)、(c)はそれぞれ、上記実施例の素子についての静電耐圧、駆動電圧Vf、全放射束を、膜厚3nmのノンドープIn0.03Ga0.97Nから成る層1051と膜厚20nmのノンドープGaNから成る層1052のペア数を3ペアから10ペアとした素子の場合について示した図である。多重層105は、その構成が3ペア、5ペアのときに静電耐圧を高く、駆動電圧Vfを低くできるが、その構成を10ペアとした素子の場合は静電耐圧が低く、駆動電圧Vfが高くなってしまう結果が得られた。一方、全放射束(発光強度)は、ペア数の違いに対して大きく左右されなかった。 FIGS. 8A, 8B, and 8C show a layer 1051 made of non-doped In 0.03 Ga 0.97 N having a film thickness of 3 nm for the electrostatic breakdown voltage, drive voltage Vf, and total radiant flux for the device of the above-described embodiment. FIG. 5 is a diagram showing a case where the number of pairs of layers 1052 made of non-doped GaN having a thickness of 20 nm is changed from 3 pairs to 10 pairs. The multi-layer 105 has a high electrostatic withstand voltage and a low drive voltage Vf when the configuration is 3 pairs and 5 pairs, but the electrostatic withstand voltage is low in the case of an element having the configuration of 10 pairs, and the drive voltage Vf. The result that became high was obtained. On the other hand, the total radiant flux (luminescence intensity) was not greatly affected by the difference in the number of pairs.

図9(a)、(b)、(c)はそれぞれ、上記実施例の素子についての静電耐圧、駆動電圧Vf、全放射束を、膜厚3nmのノンドープIn0.03Ga0.97Nから成る層1051と膜厚20nmのノンドープGaNから成る層1052の構成を膜厚3nmのノンドープIn0.03Ga0.97Nから成る層と膜厚20nmのノンドープAl0.2Ga0.8Nから成る層とした素子の場合、及び膜厚3nmのノンドープGaNから成る層と膜厚20nmのノンドープAl0.2Ga0.8Nとした素子の場合とともに示した図である。多重層105は、その構成が膜厚3nmのノンドープIn0.03Ga0.97Nから成る層1051と膜厚20nmのノンドープGaNから成る層1052の構成のときに静電耐圧を高く、駆動電圧を低くできるが、上記他の2構成とした素子の場合は静電耐圧が低く、駆動電圧Vfが高くなってしまう結果が得られた。一方、全放射束(発光強度)は、多重層105を構成する2層の組成の違いに対して大きく左右されなかった。 FIGS. 9A, 9B, and 9C show a layer 1051 made of non-doped In 0.03 Ga 0.97 N with a thickness of 3 nm for the electrostatic breakdown voltage, drive voltage Vf, and total radiant flux for the device of the above-described embodiment. And a layer 1052 composed of non-doped GaN having a thickness of 20 nm and a layer made of non-doped In 0.03 Ga 0.97 N having a thickness of 3 nm and a layer composed of non-doped Al 0.2 Ga 0.8 N having a thickness of 20 nm, and the thickness FIG. 5 is a diagram showing a case where a layer made of 3 nm non-doped GaN and a 20 nm-thick non-doped Al 0.2 Ga 0.8 N element are used. The multi-layer 105 can have a high electrostatic withstand voltage and a low driving voltage when the multi-layer 105 is composed of a layer 1051 made of non-doped In 0.03 Ga 0.97 N with a thickness of 3 nm and a layer 1052 made of non-doped GaN with a thickness of 20 nm. In the case of the other two elements, the electrostatic withstand voltage was low and the drive voltage Vf was high. On the other hand, the total radiant flux (emission intensity) was not greatly affected by the difference in the composition of the two layers constituting the multi-layer 105.

図4乃至図9の結果は、図2に示す、n側多重層105のみを有する半導体発光素子200についてのものであるが、図1に示す半導体発光素子100のn側多重層105については勿論、図1に示す半導体発光素子100のp側多重層108に対しても同様の効果を有するものと考えられる。   The results of FIGS. 4 to 9 are for the semiconductor light emitting device 200 having only the n-side multi-layer 105 shown in FIG. 2, but of course the n-side multi-layer 105 of the semiconductor light-emitting device 100 shown in FIG. 1 is considered to have the same effect on the p-side multilayer 108 of the semiconductor light emitting device 100 shown in FIG.

図10に、本発明の他の実施例に係る半導体発光素子200の模式的な断面図を示す。図2の半導体発光素子200は、図1の半導体発光素子100に対し次の2つの点を変更した構成の発光素子である。まず第1点は、n側多重層(静電耐圧向上層)105と多重量子井戸構造の発光層106の間に、超格子層から成るnクラッド層107nを設けたことである。第2点は、多重量子井戸構造の発光層106とp側多重層(静電耐圧向上層)108の間のp型層107を、超格子層から成るpクラッド層107pに変更したことである。図2の半導体発光素子200は、これらの2点以外は図1の半導体発光素子100と同様の構成であり、対応する同一の構成要素は同じ符号を付した。   FIG. 10 is a schematic cross-sectional view of a semiconductor light emitting device 200 according to another embodiment of the present invention. The semiconductor light emitting device 200 of FIG. 2 is a light emitting device having a configuration in which the following two points are changed with respect to the semiconductor light emitting device 100 of FIG. The first point is that an n-cladding layer 107n made of a superlattice layer is provided between the n-side multilayer (electrostatic withstand voltage improving layer) 105 and the light-emitting layer 106 having a multiple quantum well structure. The second point is that the p-type layer 107 between the light emitting layer 106 having a multiple quantum well structure and the p-side multilayer (electrostatic withstand voltage improving layer) 108 is changed to a p-cladding layer 107p made of a superlattice layer. . The semiconductor light emitting device 200 of FIG. 2 has the same configuration as the semiconductor light emitting device 100 of FIG. 1 except for these two points, and the same corresponding components are denoted by the same reference numerals.

超格子層から成るnクラッド層107nは、膜厚1nm、Siを1×1018/cm3ドープしたGaNと、膜厚1nm、Siを1×1018/cm3ドープしたIn0.15Ga0.85Nを6ペア積層させたものである。超格子層から成るpクラッド層107pは、膜厚1nm、Mgを1×1019/cm3ドープしたAl0.2Ga0.8Nと、膜厚1nm、Mgを1×1019/cm3ドープしたIn0.05Ga0.95Nを7ペア積層させたものである。 The n-cladding layer 107n made of a superlattice layer has a thickness of 1 nm, Si doped with 1 × 10 18 / cm 3, and a thickness of 1 nm and Si doped with 1 × 10 18 / cm 3 In 0.15 Ga 0.85 N. Six pairs are stacked. P-cladding layer 107p made of super lattice layer has a film thickness 1 nm, and Al 0.2 Ga 0.8 N was 1 × 10 19 / cm 3 doped with Mg, thickness 1 nm, an In 0.05 was 1 × 10 19 / cm 3 doped with Mg Seven pairs of Ga 0.95 N are laminated.

このような構造の図10の半導体発光素子200の静電耐圧等は、図1の半導体発光素子200の静電耐圧等と同等であった。また、他の素子特性のうち、発光強度は1割増加した。   The electrostatic withstand voltage and the like of the semiconductor light emitting device 200 of FIG. 10 having such a structure is equivalent to the electrostatic withstand voltage and the like of the semiconductor light emitting device 200 of FIG. Among other device characteristics, the emission intensity increased by 10%.

本発明は、上記実施例に限定されるものではなく他に様々な変形が考えられる。例えば、各III族窒化物系化合物半導体層として、任意の混晶比の2元乃至4元系のAlGaInNとしても良い。より具体的には、「AlxGayIn1-x-yN(0≦x≦1,0≦y≦1,0≦x+y≦1)」成る一般式で表される2元、3元(GaInN,AlInN,AlGaN)或いは4元(AlGaInN)のIII族窒化物系化合物半導体等を用いることもできる。また、そられの化合物のNの一部をP、As等のV族元素で置換しても良い。また、上記実施例では保護膜130を形成したが、保護膜130は省略しても良い。また、本例ではサファイア基板裏面に反射金属層を形成し、p電極側に透光性薄膜p電極を設けたが、フリップチップタイプとするためには、サファイア基板裏面から光を取り出す構造とするために、サファイア基板裏面の反射金属層を形成せず、p電極側を光反射層を兼ねる電極層を設けても良い。 The present invention is not limited to the above embodiments, and various other modifications are possible. For example, each group III nitride compound semiconductor layer may be a binary to quaternary AlGaInN having an arbitrary mixed crystal ratio. More specifically, "Al x Ga y In 1-xy N (0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ x + y ≦ 1) " made general formula binary represented, ternary (GaInN , AlInN, AlGaN) or a quaternary (AlGaInN) group III nitride compound semiconductor can also be used. Further, a part of N of the compound may be substituted with a group V element such as P or As. In the above embodiment, the protective film 130 is formed, but the protective film 130 may be omitted. In this example, a reflective metal layer is formed on the back surface of the sapphire substrate and a light-transmitting thin film p-electrode is provided on the p-electrode side. However, in order to obtain a flip chip type, the light is extracted from the back surface of the sapphire substrate. Therefore, the reflective metal layer on the back surface of the sapphire substrate may not be formed, and an electrode layer that doubles as the light reflecting layer may be provided on the p electrode side.

本発明の実施例1に係る半導体発光素子100の断面図。1 is a cross-sectional view of a semiconductor light emitting device 100 according to Example 1 of the present invention. 比較例に係る半導体発光素子900の断面図。Sectional drawing of the semiconductor light-emitting device 900 which concerns on a comparative example. 半導体発光素子100及び900の静電耐圧特性の結果を示す特性図。The characteristic view which shows the result of the electrostatic withstand voltage characteristic of the semiconductor light-emitting devices 100 and 900. (a)、(b)、(c)はそれぞれ、ノンドープIn0.03Ga0.97Nから成る層1051の膜厚と静電耐圧、駆動電圧Vf、全放射束の関係を示した特性図。(A), (b), (c) is a characteristic diagram showing the relationship between the film thickness of the layer 1051 made of non-doped In 0.03 Ga 0.97 N, electrostatic withstand voltage, drive voltage Vf, and total radiant flux, respectively. (a)、(b)、(c)はそれぞれ、ノンドープInGaNから成る層1051のIn組成と静電耐圧、駆動電圧Vf、全放射束の関係を示した特性図。(A), (b), (c) is a characteristic diagram showing the relationship between the In composition of the layer 1051 made of non-doped InGaN, electrostatic withstand voltage, drive voltage Vf, and total radiant flux, respectively. (a)、(b)、(c)はそれぞれ、GaNから成る層1052にシリコンをドープした場合としない場合についての静電耐圧、駆動電圧Vf、全放射束の関係を示した特性図。(A), (b), (c) is a characteristic diagram showing the relationship between electrostatic withstand voltage, drive voltage Vf, and total radiant flux when the GaN layer 1052 is doped with silicon and when it is not doped. (a)、(b)、(c)はそれぞれ、In0.03Ga0.97Nから成る層1051にシリコンをドープした場合としない場合についての静電耐圧、駆動電圧Vf、全放射束の関係を示した特性図。(A), (b), and (c) show the relationship between electrostatic withstand voltage, drive voltage Vf, and total radiant flux when the layer 1051 made of In 0.03 Ga 0.97 N is doped with silicon or not. Characteristic diagram. (a)、(b)、(c)はそれぞれ、多重層105のペア数と静電耐圧、駆動電圧Vf、全放射束の関係を示した特性図。(A), (b), (c) is a characteristic diagram showing the relationship between the number of pairs of the multilayer 105, electrostatic withstand voltage, drive voltage Vf, and total radiant flux, respectively. (a)、(b)、(c)はそれぞれ、多重層105を構成する2層の組成と静電耐圧、駆動電圧Vf、全放射束の関係を示した特性図。(A), (b), (c) is a characteristic diagram showing the relationship between the composition of the two layers constituting the multi-layer 105, the electrostatic withstand voltage, the driving voltage Vf, and the total radiant flux, respectively. 本発明の実施例2に係る半導体発光素子200の断面図。Sectional drawing of the semiconductor light-emitting device 200 which concerns on Example 2 of this invention.

符号の説明Explanation of symbols

100:半導体発光素子
101:サファイヤ基板
102:バッファ層
103:ノンドープGaN層
104:高キャリア濃度n+
105:n側多重層(静電耐圧向上層)
106:発光層
107:p型半導体層
108:p側多重層(静電耐圧向上層)
109:p型コンタクト層
110:透光性薄膜p電極
120:p電極
130:保護膜
140:n電極
150:反射金属層
DESCRIPTION OF SYMBOLS 100: Semiconductor light-emitting device 101: Sapphire substrate 102: Buffer layer 103: Non-doped GaN layer 104: High carrier concentration n + layer 105: n side multiple layer (electrostatic withstand voltage improvement layer)
106: Light-emitting layer 107: p-type semiconductor layer 108: p-side multilayer (electrostatic withstand voltage improvement layer)
109: p-type contact layer 110: translucent thin film p-electrode 120: p-electrode 130: protective film 140: n-electrode 150: reflective metal layer

Claims (10)

多重量子井戸構造の発光層を有するIII族窒化物系化合物半導体発光素子において、
発光層のn電極側に、ノンドープのInx1Ga1-x1N(0<x1<1)から成る層とノンドープのGaNから成る層とのn側多重層を有し、
発光層のp電極側に、ノンドープのInx2Ga1-x2N(0<x2<1)から成る層とノンドープのGaNから成る層とのp側多重層を有し、
前記多重量子井戸構造の発光層の井戸層は少なくともインジウム(In)を含むIII族窒化物系化合物半導体AlyGa1-y-zInzN(0≦y<1, 0<z≦1)から成り、
前記n側多重層を形成するInx1Ga1-x1N(0<x1<1)から成る層のインジウム(In)の組成x1と前記p側多重層を形成するInx2Ga1-x2N(0<x2<1)から成る層のインジウム(In)の組成x2は、いずれも、前記多重量子井戸構造の発光層の井戸層のインジウム(In)の組成zよりも小さいことを特徴とするIII族窒化物系化合物半導体発光素子。
In a group III nitride compound semiconductor light emitting device having a light emitting layer having a multiple quantum well structure,
On the n-electrode side of the light emitting layer, there is an n-side multiple layer of a layer made of non - doped In x1 Ga 1-x1 N (0 <x1 <1) and a layer made of non-doped GaN,
On the p-electrode side of the light emitting layer, there is a p-side multiple layer of a layer made of non - doped In x2 Ga 1-x2 N (0 <x2 <1) and a layer made of non-doped GaN,
The well layer of the light emitting layer having the multiple quantum well structure is composed of a group III nitride compound semiconductor Al y Ga 1-yz In z N (0 ≦ y <1, 0 <z ≦ 1) containing at least indium (In). ,
In x1 Ga 1-x1 N (0 <x1 <1) forming the n-side multilayer, the composition x1 of indium (In) and In x2 Ga 1-x2 N (forming the p-side multilayer) The indium (In) composition x2 of the layer consisting of 0 <x2 <1) is smaller than the indium (In) composition z of the well layer of the light emitting layer of the multiple quantum well structure. Group nitride compound semiconductor light emitting device.
前記n側多重層のノンドープのInx1Ga1-x1N(0<x1<1)から成る層のインジウム(In)の組成x1と、前記p側多重層のノンドープのInx2Ga1-x2N(0<x2<1)から成る層のインジウム(In)の組成x2は、いずれも、0.02以上0.07以下であることを特徴とする請求項1に記載のIII族窒化物系化合物半導体発光素子。 Non-doped In x1 Ga 1-x1 N (0 <x1 <1) composition x1 of the n-side multilayer and non-doped In x2 Ga 1-x2 N of the p-side multilayer 2. The group III nitride compound semiconductor light-emitting device according to claim 1, wherein the composition x2 of indium (In) in the layer composed of (0 <x2 <1) is 0.02 or more and 0.07 or less. 前記n側多重層のノンドープのInx1Ga1-x1N(0<x1<1)から成る層の厚さと、前記p側多重層のノンドープのInx2Ga1-x2N(0<x2<1)から成る層の厚さは、いずれも、0.5nm以上6nm以下であることを特徴とする請求項1又は請求項2に記載のIII族窒化物系化合物半導体発光素子。 The thickness of the n-side multilayer non-doped In x1 Ga 1-x1 N (0 <x1 <1) and the p-side multilayer non-doped In x2 Ga 1-x2 N (0 <x2 <1 3. The group III nitride compound semiconductor light-emitting element according to claim 1, wherein a thickness of each of the layers is 0.5 nm or more and 6 nm or less. 前記n側多重層のノンドープのInx1Ga1-x1N(0<x1<1)から成る層の厚さの前記発光層の井戸層の厚さに対する比と、前記p側多重層のノンドープのInx2Ga1-x2N(0<x2<1)から成る層の厚さの前記発光層の井戸層の厚さに対する比は、いずれも、0.1以上2以下であることを特徴とする請求項1乃至請求項3のいずれか1項に記載のIII族窒化物系化合物半導体発光素子。 The ratio of the thickness of the non-doped In x1 Ga 1-x1 N (0 <x1 <1) of the n-side multilayer to the thickness of the well layer of the light-emitting layer, and the non-doped of the p-side multilayer The ratio of the thickness of the layer made of In x2 Ga 1-x2 N (0 <x2 <1) to the thickness of the well layer of the light emitting layer is 0.1 or more and 2 or less, respectively. The group III nitride compound semiconductor light-emitting device according to any one of claims 1 to 3. 前記n側多重層のノンドープのGaNから成る層の厚さの前記発光層の障壁層の厚さに対する比と、前記p側多重層のノンドープのGaNから成る層の厚さの前記発光層の障壁層の厚さに対する比は、いずれも、0.5以上4以下であることを特徴とする請求項1乃至請求項4のいずれか1項に記載のIII族窒化物系化合物半導体発光素子。 The ratio of the thickness of the non-doped GaN layer of the n-side multilayer to the thickness of the barrier layer of the light-emitting layer, and the barrier of the light-emitting layer of the thickness of the non-doped GaN layer of the p-side multilayer 5. The group III nitride compound semiconductor light-emitting element according to claim 1, wherein the ratio of the thickness to the layer is 0.5 or more and 4 or less. 前記n側多重層の前記ノンドープのInx1Ga1-x1N(0<x1<1)から成る層の数と、前記p側多重層のノンドープのInx2Ga1-x2N(0<x2<1)から成る層の数は、いずれも、1以上7以下であることを特徴とする請求項1乃至請求項5のいずれか1項に記載のIII族窒化物系化合物半導体発光素子。 The number of layers of the non-doped In x1 Ga 1-x1 N (0 <x1 <1) in the n-side multilayer and the non-doped In x2 Ga 1-x2 N (0 <x2 <in the p-side multilayer) The group III nitride compound semiconductor light-emitting device according to any one of claims 1 to 5, wherein the number of layers comprising 1) is 1 or more and 7 or less. 前記発光層と前記n側多重層の間に、ドナー不純物がドープされた層を有することを特徴とする請求項1乃至請求項6のいずれか1項に記載のIII族窒化物系化合物半導体発光素子。 The group III nitride compound semiconductor light emitting device according to any one of claims 1 to 6, further comprising a layer doped with a donor impurity between the light emitting layer and the n-side multilayer. element. 前記ドナー不純物がドープされた層は、各々が5nm以下の厚さであって組成の異なる2種類以上のIII族窒化物系化合物半導体層が積層された超格子層であることを特徴とする請求項7に記載のIII族窒化物系化合物半導体発光素子。 The layer doped with the donor impurity is a superlattice layer in which two or more types of group III nitride compound semiconductor layers each having a thickness of 5 nm or less and different compositions are stacked. Item 8. The group III nitride compound semiconductor light-emitting device according to item 7. 前記発光層と前記p側多重層の間に、アクセプタ不純物がドープされた層を有することを特徴とする請求項1乃至請求項8のいずれか1項に記載のIII族窒化物系化合物半導体発光素子。 9. The group III nitride compound semiconductor light-emitting device according to claim 1, further comprising a layer doped with an acceptor impurity between the light emitting layer and the p-side multilayer. 10. element. 前記アクセプタ不純物がドープされた層は、各々が5nm以下の厚さであって組成の異なる2種類以上のIII族窒化物系化合物半導体層が積層された超格子層であることを特徴とする請求項9に記載のIII族窒化物系化合物半導体発光素子。 The layer doped with the acceptor impurity is a superlattice layer in which two or more group III nitride compound semiconductor layers each having a thickness of 5 nm or less and different compositions are stacked. Item 13. A group III nitride compound semiconductor light-emitting device according to Item 9.
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US8420425B2 (en) 2011-05-30 2013-04-16 Toyoda Gosei Co., Ltd. Method for producing a group III nitride semiconductor light-emitting device
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JP2005056922A (en) * 2003-08-06 2005-03-03 Rohm Co Ltd Semiconductor light emitting element
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JP2007221146A (en) * 2006-02-16 2007-08-30 Lg Electronics Inc Vertical light emitting device and its manufacturing method
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JP2012146757A (en) * 2011-01-07 2012-08-02 Sharp Corp Nitride semiconductor light-emitting element and manufacturing method of the same
US8420425B2 (en) 2011-05-30 2013-04-16 Toyoda Gosei Co., Ltd. Method for producing a group III nitride semiconductor light-emitting device
JP2014011187A (en) * 2012-06-27 2014-01-20 Nichia Chem Ind Ltd Nitride semiconductor light-emitting element
CN105140367A (en) * 2015-09-29 2015-12-09 华南师范大学 GaN-based LED epitaxial structure
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