JP2005044454A - Semiconductor storage device and drive control method for same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To maintain an erasure cell and a writing cell at a prescribed threshold voltage. <P>SOLUTION: In the repeated cycles of writing/erasing, the threshold voltage is monitored to determine whether it is in a standard range. When it is out of the standard range, the voltage or the pulse width of a writing pulse or an erasure pulse is adjusted so that it is within the standard range. For example, when Vth after the erasure is higher than the upper limit of the standard electric potential, the voltage of the erasure pulse is lowered or the pulse length is narrowed. When the Vth after the erasure is lower than the lower limit of the standard electric potential, the voltage of the erasure pulse is raised or the pulse length is widened. When the Vth after the writing is higher than the upper limit of the standard electric potential, the writing voltage is lowered or the pulse length is narrowed. When the Vth after the writing is lower than the lower limit of the standard electric potential, the writing voltage is raised or the pulse length is increased. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor memory device such as a rewritable nonvolatile semiconductor memory represented by, for example, an EEPROM (Electrically Erasable and Programmable ROM) and a flash memory, and a write control and a read control for the semiconductor memory device. The present invention also relates to a drive control method for performing erase control. In particular, the present invention relates to a technique for improving endurance characteristics in a semiconductor memory device.

  In a nonvolatile memory cell, a memory having a MONOS (Metal Oxide Nitride Oxide Semiconductor) structure is a typical example of a semiconductor memory in which a carrier storage layer is provided in an insulating film to store information in a nonvolatile manner.

  In the FG (Floating Gate) structure, a defect occurs when trying to reduce the size, and it cannot cope with further miniaturization. On the other hand, the MONOS structure in which the carrier accumulation layer is changed from FG to nitride film has advantages such as downsizing of the memory cell and reduction of the manufacturing process.

  For this reason, in recent years, development of this MONOS type memory cell has been carried out rapidly, and has attracted attention as a next-generation nonvolatile memory. In particular, many proposals of CHE (Channel Hot Electron) injection methods have been made. In 2000 VLSI, a memory cell array having a two-layer gate structure has been proposed by Halo.

  For example, Patent Document 1 proposes an NROM (Nitrided Read Only Memory) cell. The NROM cell is obtained by changing the carrier storage layer from FG to a nitride film and introducing a new multi-valued technology. The NROM cell is lower in cost than the same design rule (for example, 1/2 that of a typical flash EEPROM today). ~ 1/4) There is an advantage that can be.

US Pat. No. 5,768,192

  These nonvolatile memories using an ONO (Oxide Nitride Oxide) film employ a CHE injection method or SSI (Source Side Injection) injection method for writing, and a BTBT (Band To Band Tunneling) injection method for erasing. Yes.

  As these write / erase methods, as shown in FIG. 8, a low voltage pulse is applied, and then a verify operation is performed to check whether the pulse has changed to a predetermined threshold, and the application of the pulse is stopped.

  As a programming / erasing method, for example, a method has been proposed in which the voltage is gradually increased from the starting voltage in the erasing or programming, and the erasing or programming is repeated (see Patent Documents 2 and 3). ).

Japanese Patent Laid-Open No. 9-180481 Korean Published Patent No. 94-18870 Specification

  As shown in FIG. 9, the methods described in Patent Documents 2 and 3 apply a voltage from a certain starting voltage and perform a collation function for checking whether the voltage has changed to a predetermined threshold, that is, a so-called verify operation. Pulse application and verify operation are repeated until it reaches. When applying the pulse, the applied pulse is gradually increased by a predetermined voltage width.

  However, when CHB writing is performed in a nonvolatile memory using an ONO film and BTBT erasing is performed, the write / erase repetition characteristic is measured. As shown in FIG. 10, the threshold value increases as the number of repetitions increases. This causes a disadvantage that ΔVth, which is a difference (window) between the threshold value after erasure and the threshold value after writing, becomes small.

  In addition, since the write and erase pulse application and the verify operation are repeated, charging and discharging are necessary for the circuit for that purpose. This causes the disadvantage that power is consumed and the time required for the write / erase operation becomes longer.

  In any of the CHE injection method, SSI injection method, and BTBT injection method, the distribution of the injection region changes very sensitively depending on the write condition and the erase condition. For this reason, the injection region cannot be made the same unless the write condition and the erase condition are changed minutely.

  In this regard, in the methods described in Patent Documents 2 and 3, since the voltage increase width is constant, it is not possible to accurately match the implantation regions during writing and erasing.

  The present invention has been made in view of the above circumstances, and an object thereof is to provide a semiconductor memory device capable of maintaining an erase cell or a program cell at a predetermined threshold voltage and a method for driving the semiconductor memory device.

  In the semiconductor memory device drive control method according to the present invention, it is determined whether or not the threshold voltage after the drive pulse is applied to the memory cell is within a predetermined range, and when it is outside the predetermined range, it is within the predetermined range. Therefore, at least one of the voltage and the pulse width of the driving pulse for the memory cell is adjusted.

  It should be noted that these drive pulse states after adjustment may be stored in a predetermined storage medium so that they can be referred to at the next adjustment, and read out and used as needed. The drive pulse state includes a pulse voltage state and a pulse width state, both of which are preferably stored in a storage medium for reference. One of them is not necessarily sufficient. In the case where it is allowed, either one may be used.

  Here, in the “adjustment”, a method of adjusting the voltage and pulse width of the drive pulse with an arbitrary adjustment width may be adopted, or a method of adjusting according to a predetermined adjustment width may be adopted. . It should be noted that the adjustment width (adjustment width) for this drive pulse may be stored in a predetermined storage medium so that it can be referred to at the next adjustment, and read and used as needed. The former is a versatile technique that can be applied even when the characteristics of the device cannot be assumed in advance, although it takes time to make adjustments until it is brought to a stable value. On the other hand, the latter is an effective technique that can shorten the adjustment time when the characteristics of the device are assumed in advance.

  The semiconductor memory device according to the present invention has a configuration suitable for implementing the drive control method according to the present invention. For example, as a drive control unit, a comparison determination unit that determines whether or not a threshold voltage after application of a drive pulse to a memory cell is within a predetermined range, and a voltage of the drive pulse to the memory cell based on a determination result of the comparison determination unit And a drive pulse adjustment unit for adjusting at least one of the pulse widths.

  The inventions described in the dependent claims define further advantageous specific examples of the semiconductor memory device and the drive control method thereof according to the present invention.

  For example, in the write / erase characteristics, the write condition and the erase condition are adjusted according to the change of the threshold voltage Vth in order to make the charge distribution and the erase distribution coincide with each other. Specifically, one of the methods 1) and 2) may be adopted.

  Here, the reference potential upper limit indicates a determination threshold having a large difference from the central threshold of the operating threshold, and the reference potential lower limit indicates a determination threshold having a small difference from the central threshold of the operating threshold. .

1) When Vth after erasure> reference potential upper limit, the voltage of the erase pulse is lowered or the pulse length is narrowed.
When Vth after erasure <reference potential lower limit, the voltage of the erase pulse is increased or the pulse length is increased.

2) When Vth after writing> the upper limit of the reference potential, the writing voltage is lowered or the pulse length is narrowed.
When Vth after writing <reference potential lower limit, the writing voltage is increased or the pulse length is increased.

  Further, when the pulse voltage or the pulse length (pulse width) in the same direction is changed following the previous time, the change step may be made smaller than the previous time. For example, the voltage is reduced to half, and the voltage or pulse length of the program pulse (write pulse) or erase pulse is adjusted according to the above 1) and 2).

  When the pulse voltage itself is used, the adjustment direction is reversed between the write drive and the erase drive. That is, first, at the time of write driving, when the threshold voltage after applying the driving pulse to the memory cell is higher than the upper reference threshold, the driving pulse adjusting unit lowers the voltage of the driving pulse by a predetermined adjustment width to drive the memory cell. When the threshold voltage after applying the pulse is lower than the lower reference threshold, adjustment is performed so that the voltage of the drive pulse is increased by the adjustment width.

  On the other hand, at the time of erasure driving, when the threshold voltage after applying the driving pulse to the memory cell is higher than the upper reference threshold, the driving pulse adjusting unit lowers the voltage of the driving pulse by a predetermined adjustment width and applies the driving pulse to the memory cell. When the threshold voltage is lower than the lower reference threshold, adjustment is performed so that the voltage of the drive pulse is increased by the adjustment width.

  Here, it is preferable to store and store at least one of the voltage of the drive pulse and the pulse width of the drive pulse and the adjustment width in the data holding unit and refer to the information at the time of adjustment. When both the pulse voltage and the pulse width are stored in the data holding unit, both the pulse voltage and the pulse width can be adjusted simultaneously.

  On the other hand, when only one of the pulse voltage and the pulse width is stored in the data holding unit, it goes without saying that the adjustment is performed with reference to only the stored information. For example, when the pulse voltage side is stored in the data holding unit, the drive pulse adjustment unit adjusts the voltage of the drive pulse when the threshold voltage after application of the drive pulse to the memory cell is higher than the upper reference threshold. On the other hand, when the threshold voltage after application of the drive pulse to the memory cell is lower than the lower reference threshold, adjustment is performed so that the voltage of the drive pulse is increased by the adjustment width. When the pulse width side is stored in the data holding unit, the drive pulse adjustment unit narrows the pulse length of the drive pulse when the threshold voltage after application of the drive pulse to the memory cell is higher than the upper reference threshold. On the other hand, when the threshold voltage after applying the drive pulse to the memory cell is lower than the lower reference threshold, adjustment is performed so as to widen the pulse length of the drive pulse.

  In the above configuration according to the present invention, whether or not the erase cell or the program cell is at a predetermined threshold voltage is monitored in a repeated write / erase cycle, and when it is in a state exceeding the reference range, it is within the reference range. The drive state of write pulse and erase pulse was adjusted.

  As a result, it is possible to make the charge distribution and the erase distribution coincide with each other so that the threshold voltage Vth converges to a certain value. As a result, it is possible to improve the degradation of the ΔVth threshold value (window) in the Endurance characteristic.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

<< Configuration of Semiconductor Memory Device >>
FIG. 1 is a circuit block diagram showing an embodiment of a semiconductor memory device according to the present invention. The semiconductor memory device 1 programs a selected memory cell with a memory cell array unit 3 having a plurality of memory cell units (also simply referred to as memory cells), that is, stores predetermined data or reads stored data. And a drive control unit 5 for driving the memory cell array unit 3 as a main component.

  Although not shown, the memory cell array unit 3 has a large number of memory cells arranged in a matrix of rows and columns. As the memory cell, a charge storage layer having a structure in which a carrier storage layer is provided in an insulating film is preferable. As the charge storage layer, in the case of the control gate separation type, an insulating film structure including a floating gate (FG) or a nitride film may be used. In particular, a MONOS (or MNOS) type may be used. Considering the writing speed, a source side injection type MONOS (NMOS) transistor that injects injection charge from the source side may be applied.

As the memory cell, a high dielectric insulating film having a charge trap in which a charge trap layer is provided in the insulating film can also be used. As the high dielectric insulating film, for example, Al ₂ O ₃ (alumina oxide) or HfO ₂ (hafnium oxide) can be used. Although the charge retention mechanism is a carrier accumulation layer, for example, since it is used as a gate oxide film, a preparation condition may be created in such a direction that it is thin and does not have a carrier accumulation effect. In this case, carrier accumulation may not be clearly analyzed. In this respect, the one using a high dielectric insulating film can be considered to have a different concept from the charge storage layer having the structure in which the carrier storage layer is provided. However, regardless of whether or not this is the case, by using a high dielectric insulating film, the barrier height on the channel formation region side and the gate electrode side can be adjusted. And improvement of data retention characteristics can be expected.

  Prior to memory cell programming, that is, data writing, the drive control unit 5 applies an erase pulse having a predetermined voltage (erase voltage) and a predetermined pulse width to a predetermined line or well of a predetermined number of memory cells. The erase process is performed by applying the data, and for example, data “1” is stored in the erase memory cell.

  When the erasing is finished, the drive control unit 5 selects a word line to be written, and executes programming of a large number of memory cells connected thereto, that is, writing of data “0”. In this program, a write pulse having a predetermined voltage (write voltage or program voltage) and a predetermined pulse width is applied to a selected word line to drive a memory cell to which data “0” is to be written.

  At the time of such erasure or programming (programming), the erase cell or the program cell must be at a predetermined threshold voltage. In the semiconductor memory device 1 of the present embodiment, a drive pulse optimization processing unit 90 described later is provided in order to perform a function of maintaining the erase cell and the program cell at a predetermined threshold voltage.

  For example, with the increase in memory capacity, the size and size of memory cells such as the width and thickness of gate oxide films and intermediate dielectric films and channel dimensions have also been reduced. It is difficult to ensure uniformity such as channel size, and the threshold voltage of the memory cell tends to vary accordingly. If even one of the memory cells to be programmed does not reach the desired threshold voltage, error data is generated, so it is important to manage the threshold voltage at a constant level.

  In addition, paying attention to the fact that a MONOS (MNOS) type memory transistor can inject charges into a part of a discrete trap by the CHE injection method, binary information is written independently on the source side and the drain side of the charge storage layer. Is possible. Thereby, 2 bits can be recorded per memory cell. In this case, for example, a so-called “reverse read” method is used in which 2-bit information is written by CHE injection by switching the voltage application direction between the source and drain, and when reading, a predetermined voltage is applied between the source and drain in the reverse direction to the writing. Thus, even when the writing time is short and the amount of accumulated charge is small, 2-bit information can be read reliably. In order to cope with writing / erasing of 2-bit information, management of the threshold voltage becomes more important.

  Note that there is a possibility that an appropriate control value is different for each memory cell constituting the memory cell array unit 3, that is, for each address. For this reason, in the memory cell array unit 3, one memory cell to be erased from the same write unit is selected, or one dummy cell is arranged in the same write unit. Thereby, the memory cell from which the representative value for setting the control value is obtained is determined. When dummy cells are provided, the memory size is increased by that amount. However, in terms of determining an appropriate control value, it may be considered that there is no great difference in accuracy regardless of which of the above is used.

  The drive control unit 5 includes a row decoder unit 20, a column decoder unit 30, an input / output IF (interface) unit 40, and a drive control unit 50. The input / output IF unit 40 includes all the circuits on the bit line side necessary for writing or reading, such as the column selection circuit CS, the sense amplifier SA, the writing unit WR, and the input / output buffer I / OBUF.

  The drive control unit 50 controls each unit in the semiconductor memory device 1 to program the selected memory cell. For example, the operation mode is switched in response to a read, write, or erase permission signal, or the operation timing is controlled based on the clock. Further, the drive control unit 50 has a function as a drive pulse adjustment unit, and in cooperation with the drive pulse optimization processing unit 90 described later, the erase cell and the program cell are set to a predetermined threshold voltage at the time of erasing and writing. The voltage level and pulse width of the write pulse and the erase pulse (collectively referred to as drive pulse) are adjusted so as to be maintained, and the memory cell array unit 3 is driven using the adjusted drive pulse. Program or read the programmed data.

  The drive control unit 5 of the semiconductor memory device 1 includes an address setting unit 60, a data input / output unit 70, and a voltage generation unit 80.

  The address setting unit 60 sets addresses in the row decoder unit 20 and the column decoder unit 30 with the address signal ADR. The data input / output unit 70 takes in data from the outside and passes it to the input / output IF unit 40, and conversely outputs the data passed from the input / output IF unit 40 to the outside. The voltage generation unit 80 supplies a predetermined voltage to each unit in the semiconductor memory device 1.

  Further, the semiconductor memory device 1 includes a drive pulse optimization processing unit 90 having a verify unit 92 and a register unit 94 in addition to the functional unit similar to the conventional configuration described above as a characteristic part of the present embodiment. The register unit 94 stores the upper and lower reference threshold values of the drive pulse, the measured threshold value (measurement threshold value) of the drive pulse, the write voltage (program voltage) and the erase voltage, the adjustment width value, and the address. Hereinafter, the write voltage (or program voltage) and the erase voltage are collectively referred to as W / E voltage (or P / E voltage). The verify unit 92, which is an example of the comparison determination processing unit, compares the reference threshold value with the measurement threshold value so that the threshold voltage of the drive pulse is maintained in an appropriate range.

  The row decoder unit 20 receives the address signal ADR from the address setting unit 60, selects any or all of the plurality of word lines arranged in the memory cell array unit 3 in accordance with the address signal ADR, and reads the selected word line It is activated by changing the voltage according to the writing or erasing.

  The column decoder unit 30 receives the address signal ADR from the address setting unit 60 and controls the column selection circuit CS in the input / output IF unit 40 according to the address signal ADR, and selects a plurality of bit lines arranged in the memory cell array unit 3. For example, it selects every predetermined number. The column selection circuit CS connects all of the selected bit lines to the sense amplifier SA at the time of reading, and connects all of the selected bit lines to the writing unit WR at the time of writing.

  At the time of reading, the storage data in the memory cell array unit 3 is detected by the sense amplifier SA from the selected bit line through the column selection circuit CS. When the data to be read at once is discrete every predetermined bit, the detection result is temporarily stored at a predetermined address of the input / output buffer I / OBUF. When all of the data stored in one row is obtained after a plurality of readings, it is output to an external data bus as read data Dout, for example, in predetermined word units. Alternatively, the discretely read data may be handled as one line of stored data without being buffered and output to an external data bus or the like.

  Further, at the time of writing, input data Din from the outside is temporarily stored in the input / output buffer I / OBUF, and a plurality of write operations are performed in units of a plurality of bit lines discretely selected by the column selection circuit CS. Thus, data in one row is written into the memory cell array unit 3 while converting from the bit line voltage to the threshold voltage of the memory transistor. Alternatively, when input data Din from the outside is sent as one line of storage data to be written discretely, the input data may be sequentially written in the memory cell array unit 3 without buffering.

  The drive control unit 50 drives the control gates of the memory transistors in the memory cell array unit 3 to control data writing and reading. At this time, driving is performed with an appropriate voltage and an appropriate pulse width with reference to conditions for appropriately maintaining the threshold voltage obtained by the drive pulse optimization processing unit 90.

  Next, a method for optimizing the erase pulse voltage and the write pulse voltage in the semiconductor memory device 1 having the above configuration will be described.

<< First Embodiment >>
<Optimization method for erase voltage in drive control during erase>
FIG. 2 is a flowchart showing an example of a procedure for optimizing the erase pulse voltage during erase drive control. The outline is as follows.

  Here, the drive control operation at the time of erasure will be described in detail, and the drive control unit 50 sets the upper and lower reference thresholds after erasure in the register unit 94 in advance (S100). Thereafter, control is performed to apply a write pulse (S102), and various operations such as reading are performed (S104).

  Thereafter, the drive control unit 50 controls to apply the erase pulse (S110), measures the threshold value after the erase (S112), and stores the measured threshold value in the register unit 94 as the measurement threshold value (S114). Then, the drive control unit 50 compares the threshold after erasure with the upper and lower limits of the threshold after erasure set in the register unit 94.

  For example, the drive control unit 50 first determines whether or not the measured threshold value after erasure is higher than the upper reference threshold value after erasure (S120). When it is high, the erase pulse voltage is decreased by an arbitrary width, and the process returns to step S100 (S120-YES, S122).

  On the other hand, when the measured threshold value after erasing is lower than the upper reference threshold value after erasing, the drive control unit 50 determines whether the measured threshold value after erasing is lower than the lower threshold threshold value after erasing. Is determined (S120-NO, S124). When it is low, the erase voltage is increased by an arbitrary width, and the process returns to step S100 (S124-YES, S126).

  On the other hand, when the measured threshold value after erasure is higher than the lower reference threshold value after erasure, that is, within the range between the lower reference threshold value and the upper reference threshold value, the measured erase pulse voltage is the same as the stored value. A value is set (S124-NO, S128). Thereafter, the drive control unit 50 performs various operations such as reading, and returns to step S100 (S130).

  FIG. 3 is a diagram for explaining the effect of the above processing, and is a diagram showing the relationship between charge injection regions in writing and erasing. The principle that the above method is effective is as follows. In the nonvolatile semiconductor memory device, the CHE injection or the SSI injection is used for the writing method, and the BTBT injection is used for the erasing because the injection mechanism is different between the writing and erasing. It is common to be different.

  Therefore, if writing and erasing are repeated, charges are accumulated in the injection region where the writing charge distribution 204 and the erasing charge distribution 205 do not overlap, and sufficient writing and erasing are not performed. For this reason, the threshold width ΔVth after writing and erasing fluctuates and increases or conversely decreases.

  On the other hand, by adjusting the erase pulse voltage using the above method, the implantation regions can be made to be the same. For this reason, even if writing and erasing are repeated, charges are sufficiently canceled in the injection region, so that sufficient writing and erasing are performed without accumulating charges. For this reason, the threshold width ΔVth after erasure can be kept constant.

  In the CHE injection method, the SSI injection method, and the BTBT injection method, the distribution of the injection region changes very sensitively depending on the write condition and the erase condition. For this reason, the injection region cannot be made the same unless the write condition and the erase condition are changed minutely.

  For this reason, in order to match the implantation regions, the following method may be employed. That is, when the threshold value after erasing again becomes higher than the upper reference threshold value after erasing, or when the threshold value after erasing becomes lower than the lower threshold threshold value after erasing, the erasing voltage Is set to be smaller than the previously set arbitrary width of the erase voltage. If the upper and lower limits of the reference threshold are exceeded, it means that the voltage adjustment range is narrowed. Thereby, the distribution of the injected charge at the time of erasing can be adjusted so as to match the injected charge distribution at the time of writing.

  In this case, it is desirable that the width of the voltage set to be small is, for example, about half of the previously set voltage adjustment width. In addition, the upper reference threshold and the lower reference threshold are not fixed values, but may be set to values obtained by adding or subtracting an arbitrary width from the previously measured threshold.

  FIG. 4 is a conceptual diagram of the write / erase repetition characteristic when the erase pulse voltage is optimized by applying the above method. As shown in FIG. 4, the upper and lower reference thresholds are set in advance after erasing, and when the threshold after erasing is higher than the upper reference threshold after erasing (point P1), the erasing pulse voltage is set. Is reduced by a predetermined voltage adjustment width ΔV. When the threshold value after erasure is lower than the lower reference threshold value after erasure (point P2), the erase pulse voltage is increased by a predetermined voltage adjustment width ΔV.

  In addition, regarding the voltage adjustment width of the erase pulse voltage at that time, the threshold value after erasing again becomes higher than the reference threshold value of the upper limit of the threshold value after erasing, or the threshold value after erasing is the reference value of the lower limit of the threshold value after erasing. When it becomes lower than the threshold, it is set smaller than the voltage adjustment width ΔV of the erase pulse voltage set last time. As a typical example, as shown in the figure, it may be set to half the previous voltage adjustment width ΔV, that is, 1 / 2ΔV. By doing so, the distribution of the injected charge at the time of erasing can be adjusted to match the injected charge distribution at the time of writing.

<Optimization method of write voltage in drive control during writing>
FIG. 5 is a flowchart showing an example of a procedure for optimizing the write pulse voltage during write drive control.

  Here, the drive control operation at the time of writing will be described in detail, and the drive control unit 50 sets the upper and lower reference threshold values after writing in the register unit 94 in advance (S200). Thereafter, control is performed to apply an erase pulse (S202), and various operations such as reading are performed (S204).

  Thereafter, the drive control unit 50 controls to apply a write pulse (S210), measures a threshold value after writing (S212), and stores the measured threshold value in the register unit 94 as a measurement threshold value (S214). Then, the drive control unit 50 compares the threshold after writing with the upper and lower limits of the threshold after writing set in the register unit 94.

  For example, first, the drive control unit 50 determines whether or not the measured threshold value after writing is higher than the upper reference threshold value of the threshold value after writing (S220). When it is high, the write pulse voltage is decreased by an arbitrary width, and the process returns to step S200 (S220-YES, S222).

  On the other hand, when the measured threshold value after writing is lower than the upper threshold reference threshold value after writing, the drive control unit 50 determines whether the measured threshold value after writing is lower than the lower threshold threshold value after writing. (S220-NO, S224). When it is low, the write voltage is increased by an arbitrary width, and the process returns to step S200 (S224-YES, S226).

  On the other hand, when the measured threshold value after writing is higher than the lower reference threshold value after writing, that is, within the range between the lower reference threshold value and the upper reference threshold value, the measured writing pulse voltage is the same as the stored value. A value is set (S224-NO, S228). Thereafter, the drive control unit 50 performs various operations such as reading, and returns to Step S200 (S230).

  As can be seen from the above processing procedure, it is basically the same as the method for optimizing the erase pulse voltage shown in FIG. 2 except that there is a difference in operation mode between “erase” and “write”. It is. Therefore, also in the method for optimizing the write pulse voltage, by adjusting the magnitude of the write pulse voltage as described above, it is possible to make the implantation regions the same as in the method for optimizing the erase pulse voltage. For this reason, even if writing and erasing are repeated, charges are sufficiently canceled in the injection region, so that sufficient writing and erasing are performed without accumulating charges. Therefore, the threshold width ΔVth after writing can be kept constant.

  Similarly to the case of erasing, when the threshold value after writing becomes higher than the upper reference threshold value after writing, or after writing, the threshold value after writing becomes lower than the lower reference threshold value after writing. At this time, an arbitrary width of the write voltage is set smaller than the voltage adjustment width of the write voltage set previously. Thereby, the distribution of the injected charge at the time of writing can be adjusted so as to match the injected charge distribution at the time of erasing.

  In addition, if the above method is applied to both erasing and writing, that is, by combining the two, the magnitude of the pulse voltage is adjusted in both writing and erasing, so that the injection region is made the same, and after writing and erasing. Can be kept constant.

  For example, when the write / erase repetition characteristics are measured, the threshold value changes as the number of repetitions increases, and there is no inconvenience that ΔVth, which is the difference between the threshold value after erase and the threshold value after write, becomes small. , Can contribute to performance improvement.

  In addition, by changing the write pulse voltage and erase pulse voltage adjustment width arbitrarily in a step rather than a fixed value, the charge injection region at the time of writing and the charge injection region at the time of erasing can be made coincident. A stable threshold width can be obtained in the erasure repetition characteristic.

  In addition, since there is a single write / erase pulse, power consumption is small, and write / erase can be performed in a short time.

  In addition, since the semiconductor memory device is configured to automatically adjust, the write condition and the erase condition are optimized for each chip in the write / erase environment. In particular, it is possible to follow a change in temperature), to stabilize the threshold value, and to contribute to the improvement of reliability.

  The processing procedures shown in FIG. 2 and FIG. 5 are effective for conventional floating gate (FG) type memory cells. In particular, a plurality of procedures can be performed by controlling injected carriers for each location in one cell. When applied to a MONOS type memory cell capable of writing bits (for example, 2 bits), the effect is high. In a MONOS type memory cell capable of writing a plurality of bits, a residual charge appears remarkably in writing / erasing, which is effective as a means for performing writing / erasing with the same distribution. That is, the method for optimizing the threshold voltage as described above is effective as a measure for writing / erasing the multi-bit information.

<< Second Embodiment >>
FIG. 6 is a diagram for explaining a modified example (second embodiment) of the technique of the first embodiment. Here, the measured values of the write / erase repetition characteristics when the erase pulse voltage is optimized by applying the modification are shown.

  In this modified example, the upper reference threshold or the lower reference threshold is not a fixed value, but is a value obtained by adding a value of an arbitrary width for the lower limit to the previously measured threshold, and for the upper limit. It is characterized by setting to a subtracted value. The register unit 94 updates the stored reference threshold value to the upper limit or lower limit value after the change. By doing so, the reference range can be narrowed sequentially, and the adjustment can be directed toward the convergence direction. In a narrower range, the fluctuation of the threshold value with an arbitrary width can be detected, and more stable characteristics can be obtained. The change in the threshold value can be captured at an earlier stage, and a more stable write / erase repetition characteristic can be obtained.

  Further, the erase voltage is changed to the voltage shown in FIG. 6, and the change width is set to be small step by step. For this reason, the distribution of injected charges at the time of erasing can be matched with the injected charge distribution at the time of writing.

  In the above-described embodiment, the drive pulse voltage is adjusted according to a preset adjustment range. However, this is not always necessary. For example, the drive pulse voltage is adjusted by an arbitrary adjustment range. A technique may be adopted. The same applies to the case of controlling the pulse width of the drive pulse described later.

  By using a preset adjustment range, the adjustment time can be shortened. In other words, if the adjustment width is arbitrarily set, the width must be made large at the beginning of the adjustment. For example, in the example shown in FIG. The erasure and write conditions that can secure the threshold width are not met. For this reason, when the manufacturing conditions are stabilized and the characteristics of the element are predicted in advance, the adjustment width is set to be as small as, for example, about 0.2 V, so that a stable threshold width can be secured quickly. I can expect. On the other hand, when using a preset adjustment range, there may be cases where the adjustment range assumed cannot be dealt with. In such a case, conversely, if a method of adjusting with an arbitrary adjustment width is adopted, it is possible to cope with the case where the device characteristics cannot be assumed in advance although the adjustment time is required.

<< Third Embodiment; Development to Pulse Width Control >>
In the above description, the mechanism realized by adjusting the magnitudes of the erase voltage pulse and the write voltage pulse has been described. However, the pulse application time (pulse length) may be adjusted, that is, the pulse width control may be used. Similarly, the implantation regions can be made identical. For this reason, even if it is a mechanism for adjusting the pulse application time, or even if writing / erasing is repeated, charges are sufficiently canceled out in the injection region, so that sufficient writing and erasing can be performed without accumulating charges. It is. For this reason, the threshold width ΔVth after writing and erasing can be kept constant.

<< 4th Embodiment; Management development by current value >>
FIG. 7 is a diagram for explaining a modified example (fourth embodiment) of the management method for optimizing the erase pulse voltage and the write pulse voltage.

  In the above description, when adjusting the magnitude of the erase voltage pulse or the write voltage pulse, the threshold value after erasing or after writing is measured, and the measured threshold value is compared with the upper limit or lower limit of the threshold value set in the register unit 94. However, in this modification, a current value is used instead of the threshold value.

  In the above description, the specific procedure for obtaining the threshold value Vth has not been described. However, in order to obtain the threshold value Vth, the gate voltage of the memory cell transistor is changed little by little, and the measurement is performed several times. It is difficult to obtain without judging from the change characteristics of the voltage Vg. That is, it is practically impossible to obtain the threshold value Vth by one measurement.

  On the other hand, for example, as shown in the characteristic line of Vg (gate voltage) -Ids (drain-source current) as shown in FIG. 7, the operating current of the memory cell, that is, the drain-source current Ids is measured once. Then, by determining whether the measured current value is larger or smaller than the reference value corresponding to the threshold value Vth, it is possible to determine whether the current drive pulse is an appropriate voltage. Therefore, in the processing of FIGS. 2 and 5, the processing speed can be increased by using the processing step using the operating current of the memory cell as the determination index value instead of the step using the threshold voltage as the determination index value.

  As mentioned above, although this invention was demonstrated using embodiment, the technical scope of this invention is not limited to the range as described in the said embodiment. Various changes or improvements can be added to the above-described embodiment without departing from the gist of the invention, and embodiments to which such changes or improvements are added are also included in the technical scope of the present invention.

  Further, the above embodiments do not limit the invention according to the claims (claims), and all combinations of features described in the embodiments are not necessarily essential to the solution means of the invention. Absent. The embodiments described above include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. Even if some constituent requirements are deleted from all the constituent requirements shown in the embodiment, as long as an effect is obtained, a configuration from which these some constituent requirements are deleted can be extracted as an invention.

  For example, when the semiconductor memory device is shipped from a factory or the like, the above-described adjustment (tuning) may be performed before shipment and the conditions may be held in the memory. In actual use, information indicating the voltage and pulse width of the adjusted drive pulse may be read from the memory and driven under the conditions. Thus, the semiconductor memory device can be driven in an optimal state from the start of use.

  Further, the adjustment is not limited to each write / erase cycle, but may be performed by checking every predetermined cycle. As for the reference threshold value, instead of holding the upper limit and lower limit information, a median value may be held, and an appropriate width may be given thereto. That is, only the median value may be held, and the upper and lower limits may be determined as appropriate.

1 is a circuit block diagram showing an embodiment of a semiconductor memory device according to the present invention. It is a flowchart which shows an example of the procedure which optimizes the erase pulse voltage at the time of erase drive control. It is a figure for demonstrating the effect of the said process, Comprising: It is the figure which showed the relationship of the charge injection area | region in writing and erasing. It is a conceptual diagram of the write / erase repetition characteristic when the erase pulse voltage is optimized by applying the above method. It is a flowchart which shows an example of the procedure which optimizes the write pulse voltage at the time of write drive control. It is a figure explaining the modification (2nd Embodiment) of 1st Embodiment. It is a figure explaining the modification (4th Embodiment) of the management method at the time of optimizing an erase pulse voltage and a write pulse voltage. It is a figure explaining general verification operation | movement. It is a figure explaining the verify operation | movement of patent document 2, 3. FIG. It is a figure which shows the conventional write / erase repetition characteristic.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Semiconductor memory device, 3 ... Memory cell array part, 5 ... Drive control part, 20 ... Row decoder part, 30 ... Column decoder part, 40 ... Input-output IF part, 50 ... Drive control part, 60 ... Address setting part, 70 Data input / output unit, 80 Voltage generation unit, 90 Drive pulse optimization processing unit, 92 Verification unit, 94 Register unit

Claims (26)

In a semiconductor memory device comprising a plurality of memory cells, a method for driving the memory cells,
It is determined whether or not a threshold voltage after application of the drive pulse to the memory cell is within a predetermined range. When the threshold voltage is outside the predetermined range, the voltage and pulse of the drive pulse to the memory cell are within the predetermined range. A drive control method for a semiconductor memory device, wherein at least one of the widths is adjusted. The drive control method for a semiconductor memory device according to claim 1, wherein the adjustment is performed according to a preset adjustment range. Information indicating the voltage and pulse width of the adjusted drive pulse is held in a predetermined storage medium, and the memory cell is driven with a drive pulse based on the voltage and pulse width read from the storage medium. The drive control method according to claim 1, wherein: The drive control method according to claim 1, wherein information indicating the adjustment width is held in a predetermined storage medium, and the adjustment is performed with reference to the adjustment width read from the storage medium. A semiconductor memory device comprising a plurality of memory cells and a drive control unit for driving a plurality of selected memory cells,
The drive control unit is configured to determine whether or not a threshold voltage after application of the drive pulse to the memory cell is within a predetermined range;
And a drive pulse adjusting unit that adjusts at least one of a voltage and a pulse width of the drive pulse for the memory cell based on a determination result of the comparison / determination unit. The semiconductor memory device according to claim 5, wherein the drive pulse adjustment unit performs the adjustment according to a preset adjustment range. The drive control unit
A data holding unit for holding information indicating an appropriate range of the threshold voltage after the drive pulse is applied to the memory cell;
The semiconductor memory device according to claim 5, wherein the comparison determination unit performs the determination with reference to information indicating the appropriate range held in the data holding unit. A data holding unit that holds at least one of the voltage of the driving pulse, the pulse width of the driving pulse, and the width of the adjustment;
The semiconductor memory device according to claim 5, wherein the drive pulse adjustment unit performs the adjustment with reference to information held in the data holding unit. The data holding unit holds information indicating each reference threshold value of the upper limit and the lower limit of the threshold voltage after application of the drive pulse as information indicating the appropriate range,
The semiconductor memory device according to claim 5, wherein the comparison determination unit determines a relationship between a threshold voltage after the drive pulse is applied to the memory cell and the upper reference threshold and the lower reference threshold. . The drive pulse adjustment unit lowers the voltage of the drive pulse by an arbitrary width when the threshold voltage after application of the drive pulse to the memory cell is higher than the upper reference threshold, and the threshold after application of the drive pulse to the memory cell 6. The semiconductor memory device according to claim 5, wherein when the voltage is lower than the lower reference threshold, the adjustment is performed so that the voltage of the drive pulse is increased by an arbitrary width. The drive pulse adjustment unit lowers the voltage of the drive pulse by a preset adjustment width when a threshold voltage after application of the drive pulse to the memory cell is higher than the upper reference threshold, and drives the drive pulse for the memory cell. 6. The semiconductor memory according to claim 5, wherein when the threshold voltage after application is lower than the lower reference threshold, the adjustment is performed such that the voltage of the drive pulse is increased by a preset adjustment range. apparatus. A data holding unit for holding at least one of the voltage of the driving pulse and the pulse width of the driving pulse, and the adjustment width;
The drive pulse adjustment unit refers to the information held in the data holding unit, and when the threshold voltage after applying the drive pulse to the memory cell is higher than the upper reference threshold, the drive pulse adjustment unit When the threshold voltage after application of the drive pulse to the memory cell is lower than the lower reference threshold, the drive pulse voltage is increased by the adjustment width or the pulse length is decreased while the adjustment width is decreased or the pulse length is reduced. The semiconductor memory device according to claim 11, wherein the adjustment is performed so as to expand. The semiconductor according to claim 5, wherein the drive pulse adjustment unit makes an adjustment width for the drive pulse used at the time of the current adjustment smaller than the adjustment width used at the time of the previous adjustment. Storage device. When the threshold voltage after applying the drive pulse to the memory cell is higher than the upper reference threshold, the drive pulse adjustment unit narrows the width of the drive pulse by an arbitrary adjustment width or a preset adjustment width, When the threshold voltage after applying the drive pulse to the memory cell is lower than the lower reference threshold, the adjustment is performed so that the width of the drive pulse is increased by an arbitrary adjustment width or a preset adjustment width. 6. The semiconductor memory device according to claim 5, wherein: The semiconductor memory device according to claim 5, wherein the drive pulse adjustment unit makes the adjustment width used at the time of the current adjustment smaller than the adjustment width used at the time of the previous adjustment. The semiconductor memory device according to claim 5, wherein the drive control unit adjusts the predetermined range in a convergence direction according to a threshold voltage after applying a drive pulse to the memory cell. The data holding unit adjusts and updates the upper reference threshold and the lower reference threshold held in a convergence direction in accordance with a threshold voltage after the drive pulse is applied to the memory cell. The semiconductor memory device according to claim 9. The comparison determination unit obtains a plurality of drive parameters by driving the memory cell under different drive conditions, obtains a threshold voltage after applying a drive pulse to the memory cell based on the plurality of drive parameters, and obtains this 6. The semiconductor memory device according to claim 5, wherein it is determined whether or not a threshold voltage is within the predetermined range. The said comparison determination part acquires the operating current value of the said memory cell, and determines whether the drive conditions corresponding to this operating current value are in the said predetermined range. Semiconductor memory device. The drive pulse adjustment unit performs the adjustment with respect to any one of a drive pulse for writing data to the memory cell and a drive pulse for erasing data of the memory cell. Item 6. The semiconductor memory device according to Item 5. The said drive pulse adjustment part performs the said adjustment about both the drive pulse for the data writing to the said memory cell, and the drive pulse for the data erasure of the said memory cell. The said adjustment is characterized by the above-mentioned. Semiconductor memory device. The semiconductor memory device according to claim 5, wherein the memory cell has a structure in which a carrier storage layer is provided in an insulating film. The semiconductor memory device according to claim 22, wherein the memory cell has a MONOS (Metal Oxide Nitride Oxide Semiconductor) structure. The semiconductor memory device according to claim 22, wherein the memory cell is configured to be able to write data of a plurality of bits by controlling injected carriers for each location in the cell. The semiconductor memory device according to claim 5, wherein the memory cell includes a high dielectric insulating film in which a charge trap layer is provided in the insulating film. 26. The semiconductor memory device according to claim 25, wherein the memory cell is configured to be able to write data of a plurality of bits by controlling injected carriers for each location in the cell.

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