JP2005039292A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor having a thin film capacitor where the worsening of the morphology caused by the oxidation of an electrode/dielectric interface, the deterioration of the capacitor characteristics caused by the electrode material and the deterioration of the characteristics of the electrode material per se are prevented. <P>SOLUTION: The semiconductor device is of such the semiconductor device provided with the thin capacitor 3 where a dielectric film 5 comprising a perovskite oxide and an upper electrode 6 are laminated and disposed on a lower electrode 4. At least any of the lower electrode 4 and the upper electrode 6 has a laminated layer of an electrode layer 8 comprising a conductive perovskite oxide disposed so as to contact the laminated layer of conductive perovskite oxides of at least two kinds, for example, the dielectric thin film 5 and an electrode buffer layer 7 comprising the conductive perovskite oxide which is different from the conductive perovskite oxide comprising the electrode layer 8 and is stable at a low oxygen partial pressure. A perovskite oxide with the deficiency of oxygen and constituent element substitution or the like is used for the electrode buffer layer 7. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device such as a semiconductor memory device having a thin film capacitor as a charge storage layer.

In recent years, research on high-dielectric materials and ferroelectric materials, as well as device structure, has been actively conducted on thin-film capacitors mounted on large-capacity DRAMs and nonvolatile ferroelectric memories (FRAMs). Yes. For example, in a thin film capacitor using a perovskite oxide such as SrTiO ₃ (hereinafter referred to as STO) or Ba _1-x Sr _x TiO ₃ (hereinafter referred to as BSTO), noble metals such as Pt and Ru, Ru, etc. The use of noble metal oxides or laminated films of these as electrodes has been studied. Among these, Ru has been considered to be excellent as a capacitor electrode for DRAM or FRAM because it has particularly good workability and can be finely processed by RIE or the like.

  However, in a thin film capacitor using a noble metal such as Ru or an oxide thereof as an electrode as described above, a large amount of interface states are generated due to ion deficiency due to mismatch of the interface between the dielectric and the electrode, This causes problems such as an increase in leakage current and a decrease in dielectric breakdown resistance.

  On the other hand, the use of a conductive perovskite oxide having the same crystal structure as STO or BSTO described above as an electrode material has also been studied. When a conductive perovskite oxide is used as an electrode, high interface matching can be obtained at the interface between the dielectric and the electrode, and generation of defects and interface states can be suppressed. As a result, it is expected that a thin film capacitor exhibiting excellent electrical characteristics such as high dielectric constant and low leakage current, high reliability due to high dielectric breakdown resistance, and long life can be obtained.

  In a so-called epitaxial capacitor in which a conductive perovskite oxide as described above is epitaxially grown on Si via a conductive buffer layer such as TiAlN and further a dielectric such as BSTO is epitaxially grown thereon, By utilizing the lattice strain of the dielectric material caused by the lattice mismatch between the electrode and the electrode, extremely high dielectric constant and strain-induced ferroelectricity can be expressed. By utilizing these characteristics, it is possible to manufacture an ultra-highly integrated DRAM having a paraelectric capacitor having a very high charge accumulation amount and a nonvolatile ferroelectric memory (FRAM) having a ferroelectric capacitor.

  However, when the conductive perovskite oxide is used as the lower electrode, it is important to perform the formation in an oxygen-containing atmosphere. Here, the lower electrode is usually formed on a plug made of polysilicon, or in the case of an epitaxial capacitor, a plug made of epitaxially grown single crystal Si or the like. When the lower electrode made of a conductive perovskite oxide is formed in a normal oxygen-containing atmosphere, an oxide is generated at the interface with the Si plug, resulting in excessive contact. In some cases, this reaction causes the morphology of the electrode surface. It is known that a problem such as the occurrence of roughness and a capacitor short circuit occurs.

  In order to prevent oxidation of the plug surface, a conductive buffer layer made of TiAlN or the like having high oxidation resistance is provided on Si, and further, between a conductive buffer layer such as TiAlN and an electrode made of a conductive perovskite oxide. Although a second conductive buffer layer made of Pt or the like is also provided, problems such as a decrease in morphology due to oxidation of TiAlN or Si and a rough morphology of Pt due to high-temperature deposition of dielectrics and electrodes are solved. Not.

Furthermore, in order to prevent the above-described morphological roughness due to oxidation, it is possible to form a conductive perovskite oxide such as SrRuO ₃ under a low oxygen partial pressure, but many conductive perovskite oxides are If the film is formed at a low oxygen partial pressure, the crystallinity is deteriorated, and the film quality of the electrode and the dielectric is deteriorated, resulting in an increase in leakage.

On the other hand, SrTiO ₃ having oxygen deficiency or or a deposition to the electrode on the Nb and rare earth elements such as SrTiO ₃ was replaced directly with Si, using these as the electrodes fabricated on Si via a TiAlN, Is also possible. However, when a BSTO dielectric or the like is formed on such an electrode, it is necessary to produce it in an atmosphere containing oxygen at a high concentration in order to improve the dielectric properties. For this reason, SrTiO ₃ used as an electrode is required. Oxygen deficiency disappears and conductivity is lost, and Nb and rare earth elements in the electrode diffuse into the dielectric and the capacitor performance deteriorates.

  In addition, these conductive perovskite-type oxides can introduce oxygen vacancies in the bulk or obtain complete metal conductivity by substitution with Nb or rare earth elements. In this case, the electronic state cannot be said to be a complete metal due to the poor crystallinity and the stress applied to the crystal, and it can be said that it is described by a semiconductor having a high carrier concentration. When such a substance is directly laminated with a dielectric such as BSTO as an electrode material, a depletion layer is formed on the electrode side of the electrode / dielectric interface by electron transfer from the electrode to the dielectric. Such a depletion layer has a problem in that the capacitance of the dielectric is connected in series with the capacitance of the dielectric and the capacitance of the depletion layer, so that the overall capacitance is significantly reduced.

  The present invention has been made to cope with such problems, and a thin film capacitor that prevents deterioration of morphology due to oxidation of the electrode / dielectric interface, deterioration of capacitor characteristics due to the electrode material, deterioration of characteristics of the electrode material itself, and the like. An object of the present invention is to provide a semiconductor device.

  According to a first aspect of the present invention, there is provided a semiconductor device comprising: a lower electrode; a dielectric thin film made of a perovskite oxide disposed on the lower electrode; and an upper portion disposed on the dielectric thin film. In the semiconductor device including a thin film capacitor having an electrode, the lower electrode is formed of a laminated film of at least two kinds of conductive perovskite oxides, and through a buffer layer made of a non-oxide having conductivity. It is characterized by being connected to Si.

  In the semiconductor device of the present invention, as described in claim 2, the lower electrode includes, for example, an electrode layer made of a conductive perovskite acid oxide disposed so as to be in contact with the dielectric thin film, and the electrode layer. Unlike the conductive perovskite oxide, the electrode buffer layer is made of a conductive perovskite oxide that is stable under a low oxygen partial pressure.

Furthermore, the lower electrode is disposed so as to be in contact with the dielectric thin film, for example, as described in claim 3, and SrRuO ₃ , Sr _1-x Ba _x RuO _3, and Sr _1-y RE _y CoO ₃ (RE Is at least one element selected from La, Pr, Sm and Nd, and x and y are those satisfying 0 <x <1 and 0 <y <1). An electrode layer made of a lobskite oxide, AETiO _3-d having oxygen deficiency (AE represents at least one element selected from Sr and Ba), and a part of the constituent elements are M elements (M is Nb and rare earth) An electrode buffer layer comprising at least one conductive perovskite oxide selected from AETiO ₃ substituted with at least one element selected from elements) is doing.

  In the present invention, at least one of the lower electrode and the upper electrode of the thin film capacitor is composed of a laminated film of two or more kinds of conductive perovskite oxides. That is, a general conductive perovskite oxide layer showing metal conductivity is disposed on the dielectric thin film side as an electrode layer, and the electrode buffer layer is stable under low oxygen partial pressure on the side in contact with the Si plug or the like. A conductive perovskite oxide layer is disposed.

For example, conductive perovskite type oxide such as AETiO ₃ a portion of AETiO _3-d and constituent elements was replaced by element M having an oxygen deficiency can be easily formed by sputtering of hypoxia partial pressure It can be done and there is no loss of morphology at high temperatures. Further, these perovskite oxides exhibit semiconductor characteristics and metal conductivity. These oxides may exhibit semiconductor properties, but there are conductive perovskite oxides that exhibit the above-mentioned metal conductivity between the dielectric thin films, so there is a problem of capacity reduction due to the formation of a depletion layer, etc. Does not occur.

Furthermore, since a general conductive perovskite type oxide exists as an electrode layer between the conductive perovskite type oxide as the electrode buffer layer and the dielectric thin film as described above, this electrode layer is By serving as a barrier, oxidation of AETiO _3-d having oxygen vacancies can be mitigated, and diffusion of the substitution element M of AETiO ₃ into the dielectric thin film can be prevented.

A conductive perovskite oxide having oxygen vacancies as described above or a conductive perovskite oxide in which some of the constituent elements are replaced with M element is used as an electrode buffer layer, and further laminated with it. By forming a conductive perovskite oxide such as SrRuO ₃ , Sr _1-x Ba _x RuO ₃ , or Sr _1-y REy CoO ₃ as an electrode layer, the deterioration of morphology due to oxidation of the electrode / dielectric interface is prevented. In addition, it is possible to prevent deterioration of capacitor characteristics due to the electrode material, deterioration of characteristics of the electrode material itself, and the like.

  As described above, according to the semiconductor device of the present invention, it is possible to prevent the interface reaction and the surface oxidation that occur when the conductive perovskite is used as the capacitor electrode, as well as the deterioration of the capacitor characteristics due to the surface roughness and diffusion based thereon. be able to. Accordingly, it is possible to provide a semiconductor device such as a semiconductor memory device having a capacitor having good dielectric characteristics and high reliability.

Hereinafter, modes for carrying out the present invention will be described.
FIG. 1 is a sectional view showing a basic structure of a thin film capacitor portion in a semiconductor device of the present invention. In the figure, reference numeral 1 denotes a semiconductor substrate having a plug 2 made of, for example, polysilicon (poly-Si) or single crystal Si, and a thin film capacitor 3 is formed on the plug 2. The capacitor structure is not particularly limited, and thin film capacitors having various structures can be applied.

  The thin film capacitor 3 is used as a charge storage unit of a semiconductor memory device such as a DRAM or FRAM. That is, a transistor (not shown) provided under the plug 2 and the thin film capacitor 3 constitute a semiconductor memory device such as a DRAM or FRAM as an embodiment of the semiconductor device of the present invention. Note that the positional relationship between the transistor and the thin film capacitor is not particularly limited, and it is also possible to dispose the transistor above the thin film capacitor as shown in an embodiment described later.

As the perovskite oxide as the dielectric thin film 5, various perovskite oxides having a function as a dielectric can be used depending on the purpose of use of the thin film capacitor 3. For example, when applying a thin film capacitor 3 to the _{DRAM, Ba 1-x Sr x TiO} 3 as a dielectric thin film _{5 (BSTO), SrTiO 3 (} STO), CaTiO 3, PbTiO 3, BaZrO 3, BaSnO 3, PbZrO High dielectric perovskite oxide such as ₃ is used.

When the thin film capacitor 3 is applied to an FRAM, for example, Ba-rich Ba _1-x Sr _x TiO ₃ , BaTiO _3, or the like is used to cause strain-induced ferroelectricity due to lattice mismatch with the lower electrode 4. It is possible to configure a charge storage unit of an FRAM using the above. Ferroelectricity such as Pb (Zr, Ti) O ₃ (PZT), (Pb, La) (Zr, Ti) O ₃ (PLZT), Bi—Sr—Ta—O, Bi—Sr—Ti—O, etc. Perovskite type oxides can also be used. The film thickness of the dielectric thin film 5 is not particularly limited, and can be about 10 to 100 nm as in the case of a normal thin film capacitor.

  In the thin film capacitor 3 described above, a lower electrode 4 is formed on the plug 2. The lower electrode 4 is made of a laminated film of at least two kinds of conductive perovskite oxides, and a dielectric thin film 5 made of a perovskite oxide having a thickness of about 5 to 100 nm is formed on the lower electrode 4. Yes. Further, an upper electrode 6 is provided thereon, and the thin film capacitor 3 is constituted by these.

  In this embodiment, the lower electrode 4 composed of a laminated film of two or more kinds of conductive perovskite oxides is specifically composed of a conductive perovskite oxide that is disposed on the plug 2 side and is stable under a low oxygen partial pressure. And an electrode layer 8 made of a general conductive perovskite oxide disposed so as to be in contact with the dielectric thin film 5. In addition, the electrode buffer layer 7 and the electrode layer 8 can further be composed of a plurality of conductive perovskite oxide layers.

  In the lower electrode 4 made of the above laminated film, the electrode buffer layer 7 made of a conductive perovskite oxide that is stable under a low oxygen partial pressure is oxidized at the interface between the plug 2 and the lower electrode 4, morphological roughness based on the oxidation, etc. Is to prevent. Furthermore, the electrode layer 8 made of a normal conductive perovskite oxide is stacked on the electrode buffer layer 7 to reduce the capacitor characteristics due to the electrode material and the characteristics of the electrode buffer layer 7 as the electrode material. We prevent decline.

As the constituent material of the electrode buffer layer 7 described above, for example, AETiO _3-d having oxygen vacancies (AE represents at least one element selected from Sr and Ba), or a part of the constituent elements is M element (M Is a conductive perovskite oxide such as AETiO ₃ substituted with at least one element selected from Nb and rare earth elements.

Specific examples of the conductive perovskite oxide having oxygen vacancies include SrTiO _{3 -d} , BaTiO _{3 -d} , and Sr _1-x Ba _x TiO _{3 -d} (x = 0 to 1). Some of the constituent elements are M elements, and conductive perovskite oxides include (Sr _1-a , Ma) TiO _3-d , (Ba _1-a , Ma) TiO _3-d (a = 0.1 to 0.5 ) And the like. Note that a conductive perovskite oxide in which some of these constituent elements are substituted with M element may have an oxygen deficiency.

Perovskite oxides represented by AETiO _3-d having oxygen vacancies and (AE _1-a , Ma) TiO _{3 in} which some of the constituent elements are substituted with M elements are sputtered at a low oxygen partial pressure. It can be easily formed by film formation, etc., and relatively good crystallinity can be obtained, and the conductivity required for the electrode material, specifically, the conductivity of about 10 Ω · cm or less is satisfied. It exhibits semiconductor characteristics and metal conductivity. In other words, these conductive perovskite oxides have the characteristics required for electrode materials, are stable under a low oxygen partial pressure, and do not deteriorate in morphology at high temperatures. is doing.

  By applying the electrode buffer layer 7 made of such a conductive perovskite oxide, it is possible to prevent morphological roughness due to oxidation at the interface between the plug 2 and the lower electrode 4, thereby causing a capacitor short circuit and leakage current. An increase or the like can be suppressed. The thickness of the electrode buffer layer 7 is preferably about 1 to 20 nm, for example. If the thickness of the electrode buffer layer 7 is too thin, the above-described effects may not be stably obtained. On the other hand, if the electrode buffer layer 7 is too thick, no further effects can be obtained.

Here, in the conductive perovskite oxide represented by AETiO _3-d having oxygen vacancies, oxygen vacancies play an important role in obtaining the conductivity, and the oxygen deficiency d is 0.01 to 0.4. It is preferable to set it as the range. However, when the electrode layer 8 or the dielectric thin film 5 needs to be formed at a high temperature in an oxygen-containing atmosphere after the electrode buffer layer 7 is formed, the oxygen deficiency of the electrode buffer layer 7 may disappear and the conductivity may be lost. There is. In such a case, it is preferable to use a perovskite oxide represented by (AE _1-a , M _a ) TiO _{3 in} which _a part of the constituent elements is substituted with M element.

As described above, SrTiO ₃ , BaTiO ₃ , Sr _1-x Ba _x TiO _3, etc., in which some of the constituent elements are replaced with M element exhibit conductivity even in the absence of oxygen vacancies, and the electrode buffer layer 7 Can function as. Of course, oxygen deficiency may be present by forming a film under a low oxygen partial pressure. Perovskite-type oxides in which some of the constituent elements are replaced with M elements can obtain even better conductivity by the presence of oxygen vacancies ((AE _1-a , M _a ) TiO _3-d ). Can do.

  In the conductive perovskite oxide used as the electrode buffer layer 7, La, Pr, Sm, Nd, or the like is used as the rare earth element as the M element. The substitution amount a with these rare earth elements and Nb is preferably in the range of 0.1 to 0.5. If the amount of substitution by the M element is too small, good conductivity cannot be obtained, while if it is too much, the crystallinity is lowered and good dielectric properties and low leakage properties may not be obtained.

The ratio of Ba and Sr as AE elements in AETiO _3-d having oxygen vacancies and perovskite oxides represented by (AE _1-a , Ma) TiO ₃ with some of the constituent elements substituted with M elements Can be set arbitrarily. For example, the lattice constant of the electrode buffer layer 7 and the plug 2 (or substrate 1) made of poly-Si, single crystal Si, or the like, or a non-oxide buffer layer made of TiN, Ti _1-x Al _x N, etc., which will be described later, In order to match the lattice constant, the composition ratio x of Ba can be set as appropriate.

  At this time, the electrode layer 8 formed on the electrode buffer layer 7 may also have the same in-plane lattice constant as that of the electrode buffer layer 7, in order to set a lattice constant mismatch between the lower electrode 4 and the dielectric thin film 5. For this, it is preferable to appropriately select the composition of the electrode buffer layer 7, the electrode layer 8, and the dielectric thin film 5.

As the electrode buffer layer 7, various conductive perovskite oxides that are stable in a low oxygen partial pressure such as SrVO ₃ , ReO ₃ , AWO ₃ (A is an alkali metal) can be used. Perovskite oxides represented by (AE _1-a , Ma) TiO _{3 in} which some of the constituent elements are substituted with M element are contained in AETiO _3-d having oxygen deficiency and containing elements harmful to semiconductor devices In particular, when similar Sr _1-x Ba _x TiO ₃ is used as the dielectric, it has various advantages such as being able to share the film forming apparatus. Therefore, the electrode buffer layer 7 in the present invention is represented by AETiO _3-d having oxygen vacancies or (AE _1-a , M _a ) TiO _{3 in} which _a part of the constituent elements is substituted with M element. It is desirable to use a perovskite oxide.

  In the thin film capacitor 3 according to the present invention, an electrode layer made of a different conductive perovskite oxide is formed on the electrode buffer layer 7 made of a conductive perovskite oxide that is stable at a low oxygen partial pressure as described above. 8 are laminated and the lower electrode 4 is constituted by these laminated films. Here, a normal conductive perovskite oxide that does not have oxygen deficiency or M element substitution is used for the electrode layer 8.

The conductive perovskite oxide used for the electrode layer 8 is SrRuO ₃ , Sr _1-x Ba _x RuO ₃ , Sr _1-y RE _y CoO ₃ (RE is at least 1 selected from La, Pr, Sm and Nd) Examples of seed elements are x and y, which are numbers satisfying 0 <x <1, 0 <y <1). The thickness of the electrode layer 8 is preferably about 5 to 100 nm, for example.

As described above, only the perovskite oxide represented by AETiO _3-d having oxygen vacancies and (AE _1-a , Ma) TiO _{3 in} which some of the constituent elements are substituted with M element is used as the lower electrode 4. When used, when the dielectric thin film 5 is produced in an oxygen-containing atmosphere, the oxygen deficiency of the electrode material disappears and the conductivity is lost, or Nb and rare earth elements in the electrode material diffuse into the dielectric thin film 5. As a result, there is a problem that the capacitor performance is degraded. Furthermore, a conductive perovskite oxide having oxygen deficiency or M element substitution may exhibit semiconductor characteristics. When the dielectric thin film 5 is formed directly on such an electrode material, the electrode side of the electrode / dielectric interface However, there is a problem that a depletion layer is formed and the entire capacity is remarkably reduced.

In the present invention, an electrode layer 8 made of SrRuO ₃ , Sr _1-x Bax RuO ₃ , Sr _1-y REy CoO ₃ or the like is laminated on the electrode buffer layer 7, and the dielectric thin film 5 is in contact with the electrode layer 8. Therefore, it is possible to prevent a decrease in conductivity accompanying the disappearance of oxygen vacancies and a decrease in capacitor performance due to diffusion of Nb or rare earth elements into the dielectric thin film 5. Further, there is no case where the capacitance of the capacitor is reduced due to the formation of the depletion layer.

  As described above, by forming the lower electrode 4 as the electrode buffer layer 7 and the electrode layer 8 by a laminated film of two or more kinds of conductive perovskite oxides, morphology due to oxidation at the interface of the plug 2 / lower electrode 4 It is possible to prevent the deterioration of the characteristics of the electrode buffer layer 7 as an electrode material and the deterioration of the capacitor performance based thereon, while suppressing the occurrence of roughness and the accompanying occurrence of a capacitor short circuit and an increase in leakage current.

The electrode buffer layer 7 can be directly epitaxially grown on the Si substrate 1 and the single crystal Si plug 2 constituting the semiconductor device, or can be directly formed on the polycrystalline or amorphous Si plug as a polycrystalline film. In some cases, as shown in FIG. 2, a second buffer layer made of non-oxide having conductivity such as Ti _1-x Alx N in which TiN or a part thereof is replaced with Al to improve oxidation resistance is used. 9 may be provided, and the electrode buffer layer 7 may be formed thereon.

Even in such a case, if the second electrode buffer layer 9 made of TiN, Ti _1-x Alx N, or the like is formed as an epitaxial single crystal film, the electrode buffer layer 7 provided thereon, the electrode layer 8 and the dielectric layer A single crystal heteroepitaxial capacitor epitaxially grown up to the body thin film 5 and possibly the upper electrode 6 can be produced.

The upper electrode 6 may be formed of a single layer film of a conductive perovskite oxide such as SrRuO ₃ , Sr _1-x Bax RuO ₃ , Sr _1-y REy CoO ₃ , or the lower electrode Similarly to 4, it may be composed of a laminated film of two or more kinds of conductive perovskite oxides. Furthermore, in this embodiment, the case where the lower electrode 4 is formed of a laminated film of two or more kinds of conductive perovskite oxides has been described. However, only the upper electrode 6 is made of two or more kinds of conductive perovskite type oxides. A laminated film can be used, and the same effect as in the case of the lower electrode 4 can be obtained.

  According to the semiconductor memory device having the thin film capacitor 3 shown in this embodiment, characteristics such as highly integrated DRAM and nonvolatile ferroelectric memory (FRAM) are stabilized, reliability is improved, and characteristics are improved. Can be planned. Note that the semiconductor device of the present invention is not limited to a semiconductor memory device and can be applied to various semiconductor devices having a thin film capacitor.

  Next, a specific example of the thin film capacitor shown in the above embodiment and its evaluation result will be described.

Example 1 In Example 1, the thin film capacitor portion of the semiconductor device shown in FIG. 3 was produced. First, Ti0.7 AlO.sub.2 as a second buffer layer is formed on a substrate 12 completed up to a plug 11 formed of single crystal Si ((100) orientation) using a helicon sputtering apparatus having an ultrahigh vacuum chamber. 8 N film 13 was deposited to 10 nm. Further, as an electrode buffer layer for the lower electrode, an SrTiO _3-d film 14 was deposited to a thickness of 10 nm using an RF sputtering apparatus. The film-forming atmosphere at this time was Ar 0.1 Pa, and a value of d = 0.3 was obtained according to the oxygen deficiency measurement of the SrTiO _3-d film separately performed. The conductivity of the film was 10 mΩ · cm at room temperature.

An SrRuO ₃ film 15 is deposited as an electrode layer of the lower electrode on the SrTiO _3-d film 14 as the electrode buffer layer to a thickness of 30 nm using an RF magnetron sputtering apparatus, and then the surface is planarized using CMP and between the cells. Separated. A Ba _0.2 Sr _0.8 TiO ₃ film 16 as a dielectric thin film was deposited to a thickness of 20 nm on the lower electrode, and an SrRuO 3 film 17 was deposited as an upper electrode to a thickness of 100 nm on the lower electrode to produce a full oxide capacitor for DRAM.

The thin film capacitor thus obtained was subjected to X-ray diffraction. As a result, in Example 1, the Ti _0.7 Al _0.8 N film 13, the SrTiO _{3 -d} film 14, the SrRuO ₃ film 15, and the Ba _0.2 Sr _0.8 TiO ₃ film 16. It was also found that all of the SrRuO ₃ film 17 was epitaxially grown. Further, observation with a cross-sectional electron microscope revealed that the lower electrode / dielectric interface (specifically, the interface between the SrRuO ₃ film 15 and the Ba _0.2 Sr _0.8 TiO ₃ film 16) and Ti _0.7 Al _0.8 associated with the formation of the oxide layer. Roughness of the interface between the N film 13 and the SrTiO _3-d film 14 was not observed.

Further, as a comparative example with the present invention, a thin film capacitor (Comparative Example 1) in which the electrode buffer layer (SrTiO _3-d film 14) of the lower electrode is not provided, and a thin film capacitor having a Pt film with a thickness of 10 nm as the electrode buffer layer (Comparative Example 2) was prepared, and the characteristics of the thin film capacitor according to these comparative examples and the thin film capacitor according to Example 1 were compared.

As a result, the thin film capacitor of Example 1 has a dielectric constant of 990 and a leakage current density of less than 1 × 10-7A / cm ^{2 when} 2.2V is applied. Even if a DC voltage of 10V is applied to this thin film capacitor Dielectric breakdown did not occur. In contrast, in Comparative Example 1, 99% of 260 thin film capacitors could not be measured due to short circuit, and in Comparative Example 2, 90% of 260 thin film capacitors could not be measured due to short circuit. . The remaining thin film capacitors also had a small leakage current, but with a dielectric constant of 390 and DC10V, 80% were destroyed within 1000 seconds.

Example 2 Similar to Example 1, a semiconductor device having a thin film capacitor using an Sr _0.7 La _0.3 TiO _3-d film as an electrode buffer layer was produced. First, a Ti _0.7 Al _0.8 N film is formed as a second buffer layer on a substrate that has been completed up to a plug formed of single crystal Si ((100) orientation) using a helicon sputtering apparatus having an ultra-high vacuum chamber. Deposited 10 nm. Furthermore, as an electrode buffer layer of the lower electrode, an Sr _0.7 La _0.3 TiO _3-d film having a thickness of 10 nm was deposited using an RF sputtering apparatus. The film-forming atmosphere at this time was Ar 0.1 Pa, and a value of d = 0.1 was obtained according to the oxygen deficiency measurement of the Sr _0.7 La _0.3 TiO _3-d film separately performed. The conductivity of the film was 1 mΩ · cm at room temperature.

When depositing the electrode buffer layer made of this Sr _0.7 La _0.3 TiO _3-d film, and further the electrode layer and dielectric thin film described below, in particular, in fabricating an epitaxial capacitor as described in Example 2, The film quality of the initial deposition layer is extremely important for improving the performance of the entire film and hence the thin film capacitor. Therefore, in the initial deposition process of each layer, it is desirable to set the sputtering power low in order to improve the crystallinity by suppressing the film growth rate. Specifically, in Example 2, an initial film equivalent to a thickness of 2 nm is deposited by applying a power of 100 W to an Sr _0.7 La _0.3 TiO _3-d target having an 8 inch diameter, and then the sputtering power is increased to 800 W. The remaining 8 nm is deposited. Such a procedure was similarly performed for each layer deposited on the upper part of the electrode buffer layer.

An SrRuO ₃ film is deposited as an electrode layer of the lower electrode on the Sr _0.7 La _0.3 TiO _3-d film as the electrode buffer layer to a thickness of 30 nm using an RF magnetron sputtering apparatus, and then the surface is planarized using CMP. The cells were separated. A Ba _0.2 Sr _0.8 TiO ₃ film as a dielectric thin film was deposited to a thickness of 20 nm on the lower electrode, and a SrRuO ₃ film was deposited as a top electrode to a thickness of 100 nm on the lower electrode to produce a full oxide capacitor for DRAM.

When X-ray diffraction of the thin film capacitor thus obtained was performed, a Ti _0.7 Al _0.8 N film, a Sr _0.7 La _0.3 TiO _3-d film, a SrRuO ₃ film, a Ba _0.2 Sr _0.8 TiO ₃ film and a SrRuO ₃ film were obtained. All were found to be epitaxially grown. Furthermore, when a cross-sectional electron microscope observation was performed, a lower electrode / dielectric interface (specifically, an interface between a SrRuO ₃ film and a Ba _0.2 Sr _0.8 TiO ₃ film) or a Ti _0.7 Al _0.8 N film accompanying the formation of an oxide layer was observed. No roughening of the interface between the Sr _0.7 La _0.3 TiO _3-d film and the like was observed.

  In the thin film capacitor of Example 2, a dielectric constant of 900 and a leakage current density of 1 × 10 −7 A / cm 2 or less when 2.2 V was applied were obtained. Moreover, dielectric breakdown did not occur even when a DC voltage of 10 V was applied to the thin film capacitor. FIG. 2 shows a measurement result of the relationship between the applied voltage and the dielectric constant of the thin film capacitor according to Example 2, and FIG. 3 shows a measurement result of the relationship between the applied voltage and the leakage current.

  Further, a test circuit of a semiconductor memory device on which the thin film capacitor of Example 2 was mounted was manufactured, and so-called endurance measurement in DRAM operation, that is, change in malfunction rate with respect to refresh time extension was measured. It was found that 90% or more operated normally until a refresh cycle of 20 seconds or more, and the capacitor leak was extremely small.

Example 3 In Example 3, a DRAM having a thin film capacitor having a polycrystalline Sr _0.7 La _0.3 TiO _{3 -d} film as an electrode buffer layer was fabricated as an example of mounting a polycrystalline film capacitor.

First, as shown in FIG. 6, an insulating layer 23 having a thickness of 100 nm was formed by plasma TEOS on a substrate 22 that had been completed up to a plug 21 made of polysilicon. A capacitor trench 24 was formed in the insulating layer 23 by lithography. On the substrate 22 having such a capacitor trench 24, a TiN film 25 having a thickness of 10 nm is deposited as an adhesion layer by DC sputtering, and a Sr _0.7 La _0.3 TiO _3-d film 26 having a thickness of 10 nm is deposited as an electrode buffer layer of the lower electrode. Further, after depositing a SrRuO ₃ film 27 as an electrode layer of the lower electrode to a thickness of 50 nm using RF magnetron sputtering, the surface was flattened using CMP and the cells were separated. A Ba _0.2 Sr _0.8 TiO ₃ film 28 as a dielectric thin film was deposited to 40 nm on the lower electrode, and a SrRuO ₃ film 29 was deposited as an upper electrode to a thickness of 100 nm on the lower electrode, thereby producing a DRAM capacitor. In the thin film capacitor of Example 3, the dielectric constant was 480 and the leakage current when 1.8 V was applied was 1 × 10 −8 A / cm 2 or less. Moreover, dielectric breakdown did not occur even when a DC voltage of 10 V was applied to the thin film capacitor.

  Example 4 In Example 4, a semiconductor memory device having a thin film capacitor not using a TiAlN buffer layer was produced.

First, a helicon sputtering apparatus having an ultrahigh vacuum chamber is used on a substrate that has been completed up to a plug formed of single crystal Si ((100) orientation), and Sr _0.2 Ba _0.5 La _0.3 TiO ₃₋ is used as an electrode buffer layer. _{A d} film was deposited to 10 nm. According to the oxygen deficiency measurement of the Sr _0.2 Ba _0.5 La _0.3 TiO _3-d film separately performed, a value of d = 0.2 was obtained, and the conductivity of the film was 1 mΩ · cm at room temperature.

An SrRuO ₃ film is deposited as an electrode layer of the lower electrode to a thickness of 30 nm by RF magnetron sputtering on the upper part of the Sr _0.2 Ba _0.5 La _0.3 TiO _3-d film as the electrode buffer layer, and then the surface is planarized by CMP. And the cells were separated. On this lower electrode, a Ba _0.2 Sr _0.8 TiO ₃ film as a dielectric thin film was deposited with a thickness of 20 nm, and an SrRuO ₃ film as an upper electrode was deposited thereon with a thickness of 100 nm to produce a full oxide capacitor for DRAM.

When X-ray diffraction was performed on the thin film capacitor thus obtained, it was found that all films were epitaxially grown from the electrode buffer layer of the lower electrode to the upper electrode. Further, observation with a cross-sectional electron microscope revealed that the lower electrode / dielectric interface and the roughness of the Sr _0.2 Ba _0.5 La _0.3 TiO _{3 -d} / Si interface associated with the formation of the oxide layer were not observed.

  In the thin film capacitor of Example 4, a dielectric constant of 930 and a leakage current density of 1 × 10 −7 A / cm 2 or less when 2.2 V was applied were obtained. Moreover, dielectric breakdown did not occur even when a DC voltage of 10 V was applied to the thin film capacitor. Furthermore, when a test circuit for a semiconductor memory device equipped with this thin film capacitor was fabricated and endurance measurement was performed in DRAM operation, 90% or more of 1K test bits operated normally until a refresh cycle of 20 seconds or more. It was found that there was very little capacitor leakage.

  Example 5 In Example 5, a semiconductor memory device having a paraelectric capacitor for DRAM without using a TiAlN buffer layer was produced.

First, a helicon sputtering apparatus having an ultra-high vacuum chamber is used on a substrate that has been completed up to a plug formed of single crystal Si ((100) orientation), and Sr _0.4 Ba _0.3 Nd _0.3 TiO ₃₋ is used as an electrode buffer layer. _{A d} film was deposited to 10 nm. According to the oxygen deficiency measurement of the Sr _0.4 Ba _0.3 Nd _0.3 TiO _3-d film separately performed, a value of d = 0.2 was obtained, and the conductivity of the film was 1 mΩ · cm at room temperature.

An SrRuO ₃ film was deposited as an electrode layer for the lower electrode to a thickness of 30 nm on the electrode buffer layer using RF magnetron sputtering, and the surface was flattened using CMP and the cells were separated. On such a lower electrode, Βa _0.2 Sr _0.8 TiO ₃ was deposited as a dielectric thin film to a thickness of 20 nm, and further SrRuO ₃ as a top electrode was deposited to a thickness of 30 nm to produce a full oxide capacitor for DRAM.

When X-ray diffraction of the thin film capacitor thus obtained was performed, it was found that all the films from the electrode buffer layer of the lower electrode to the upper electrode were epitaxially grown. Further, observation with a cross-sectional electron microscope revealed that the lower electrode / dielectric interface and the roughness of the Sr _0.4 Ba _0.3 Nd _0.3 TiO _{3 -d} film / Si interface accompanying the formation of the oxide layer were not observed.

  In the thin film capacitor of Example 5, a dielectric constant of 950 and a leakage current density of 1 × 10 −7 A / cm 2 or less when 2.2 V was applied were obtained. In addition, dielectric breakdown did not occur even when a DC voltage of 20 V was applied to the thin film capacitor. Furthermore, when a test circuit for a semiconductor memory device equipped with this thin film capacitor was fabricated and endurance measurement was performed in DRAM operation, 90% or more of 1K test bits operated normally until a refresh cycle of 20 seconds or more. It was found that there was very little capacitor leakage.

  Example 6 In Example 6, a semiconductor memory device having a ferroelectric capacitor that does not use a TiAlN buffer layer was produced.

First, a helicon sputtering apparatus having an ultra-high vacuum chamber is used on a substrate that has been completed up to a plug formed of single crystal Si ((100) orientation), and Sr _0.4 Ba _0.3 La _0.3 TiO ₃₋ is used as an electrode buffer layer. _{A d} film was deposited to 10 nm. According to the oxygen deficiency measurement of the Sr _0.4 Ba _0.3 La _0.3 TiO _3-d film separately performed, a value of d = 0.2 was obtained, and the conductivity of the film was 1 mΩ · cm at room temperature.

An SrRuO ₃ film was deposited as an electrode layer of the lower electrode to a thickness of 30 nm on the electrode buffer layer using RF magnetron sputtering, and the surface was planarized and the cells were separated using CMP. On such a lower electrode, a BaTiO ₃ film as a dielectric thin film was deposited with a thickness of 20 nm, and an SrRuO ₃ film as an upper electrode was deposited thereon with a thickness of 100 nm to produce an all oxide capacitor for FRAM.

When the X-ray diffraction of the thin film capacitor for FRAM thus obtained was performed, all of the Sr _0.4 Ba _0.3 La _0.3 TiO _{3 -d} film, SrRuO ₃ film, BaTiO ₃ film and SrRuO ₃ film were epitaxially grown. I understood. Further, observation with a cross-sectional electron microscope revealed that the lower electrode / dielectric interface and the roughness of the Sr _0.4 Ba _0.3 La _0.3 TiO _{3 -d} film / Si interface accompanying the formation of the oxide layer were not observed.

When the ferroelectric characteristics of the thin film capacitor for FRAM according to Example 6 were evaluated, characteristics with a coercive voltage of 2 V and a residual polarization of 0.4 C / m ² were obtained. Furthermore, when a test circuit of a semiconductor memory device (FRAM) equipped with the thin film capacitor for FRAM was manufactured and so-called fatigue characteristics were measured in the FRAM operation, 90% or more of 1K test bits were up to 1012 times. It was found that the capacitor operates normally up to the writing operation and the fatigue of this capacitor is small.

Example 7 In Example 7, a pedestal type three-dimensional capacitor using a La-doped SrTiO ₃ film as an electrode buffer layer was produced. The manufacturing process of this pedestal type three-dimensional capacitor will be described with reference to FIGS.

First, a substrate was prepared by etching back the upper part of the single crystal Si plug 32 formed in the Si oxide film 31 by 10 nm (FIG. 7A). An Sr _0.6 La _0.4 TiO ₃ film 33 was deposited on this surface using helicon sputtering, and the surface was flattened by CMP (FIG. 7B). At this time, Sr _0.6 La _0. 4 TiO ₃ film 33 directly above the single-crystal Si plug 32 is epitaxially grown single-crystal Si plug 32 to form a single crystal electrode buffer layer.

Next, a Si oxide film 34 (60 nm) was formed on the surface, and the portion immediately above the Sr _0.6 La _0.4 TiO ₃ film 33 was removed by etching (FIG. 7C). Further, an SrRuO ₃ film 35 ′ was deposited on the surface as an electrode layer material for the lower electrode so as to be 50 nm on the Si oxide film 34 (FIG. 7D). At this time, the SrRuO ₃ film 35 ′ immediately above the Si plug 32 is a single crystal epitaxial film that inherits the crystal orientation of the Sr _0.6 La _0.4 TiO 3 film 33 as the electrode buffer layer.

The surface of the SrRuO ₃ film 35 ′ is polished by CMP until it reaches the surface of the Si oxide film 34 to form an electrode layer 35 made of the SrRuO ₃ film (FIG. 8A), and further, Si oxide is etched. The film 34 was removed to obtain a single crystal SrRuO ₃ pedestal type solid lower electrode 35 (FIG. 8B).

Further, a Ba _0.3 Sr _0.7 TiO ₃ film 36 is deposited as a dielectric thin film on the single crystal SrRuO ₃ pedestal type three-dimensional lower electrode 35 by a MOCVD method so as to have a film thickness of 20 nm on the electrode side wall. A SrRuO ₃ film 37 (30 nm) was formed as an upper electrode by the same MOCVD method to obtain a capacitor.

By X-ray or transmission electron microscope observation, it was confirmed that the capacitor of Example 7 was a heteroepitaxial all-oxide capacitor that was epitaxially grown from the Si plug 32 to the SrRuO ₃ film 37 as the upper electrode. The effective dielectric constant of this capacitor is 800, and it was confirmed that it has sufficient performance as a capacitor for 0.15 μm generation DRAM.

  Next, another embodiment in which the semiconductor device of the present invention is applied to a semiconductor memory device will be described with reference to FIGS. 9 is a plan view of one bit and its adjacent pattern of the semiconductor memory device of this embodiment, FIG. 10 is a sectional view taken along line XX 'in FIG. 9, and FIG. 11 is a line YY' in FIG. FIG.

In these figures, reference numeral 41 denotes a (100) -oriented p-type silicon substrate (first substrate) having an impurity concentration of about 1 to 5 × 10 15 cm ⁻³ , and is formed on the p-type silicon substrate 41 on the surface thereof. The lower electrode 43 according to the present invention, that is, an electrode buffer layer 44 made of, for example, a Sr _0.7 La _0.3 TiO _2.9 film and an epitaxial electrode layer 45 made of, for example, a SrRuO ₃ film, for example, epitaxially grown (Ba) through the N + diffusion layer 42. , Sr) A capacitor insulating film 46 made of a TiO ₃ film and a thin film capacitor having an upper electrode 47 made of, for example, a SrRuO ₃ film are formed.

  On the SOI layer 48 as the second substrate, a gate electrode 49, a bit line 50, a wiring layer 51, interlayer insulating films 52 and 53 that insulate them, and source / drain diffusion layers in the SOI substrate A transistor having a connection hole poly-Si layer 54 that electrically connects one of the capacitor and the upper electrode 47 of the capacitor is formed. These capacitors and transistors constitute a semiconductor memory device. In FIG. 9, A is an element area (Active Area), C is a capacitor area, and W is a word line.

  The semiconductor memory device shown in FIGS. 9 to 11 can be manufactured as follows, for example. With reference to FIG. 12, the manufacturing process of the semiconductor memory device of this embodiment will be described. 12 corresponds to a cross-sectional view taken along line XX ′ of FIG. 9 shown in FIG.

First, as shown in FIG. 12A, a p-type epitaxial Si layer 41 (or a p-type epitaxial Si layer is formed on the surface of a p-type Si substrate having an impurity concentration of (100) orientation of about 1 to 5 × 10 15 cm ^−3. For example, a p-well (not shown) is formed in the n-channel transistor formation region, and an n-well (not shown) is formed in the p-channel transistor formation region. .

Next, in the case of the DRAM mode, a plate electrode (PL) having a common constant potential (this example is shown in FIG. 11), and in the case of the FRAM mode, in the same direction (parallel) as the bit line. A lower electrode group (an N + diffusion layer 42 in the Si substrate 41 is formed to a depth of about 0.1 μm (may be omitted)) to be a plate line (also called a drive line) for each memory cell to be formed, and For example, a Sr _0.7 La _0.3 TiO _2.9 film having a thickness of about 10 nm is formed as the electrode buffer layer 44, and a SrRuO ₃ film having a thickness of about 20 nm is formed as the electrode layer 45.

For the formation of the N + diffusion layer 42, for example, a resist mask (not shown) and an As + ion implantation method may be used. In addition, the electrode buffer layer 44 and the electrode layer 45 are subjected to substrate ripening at about 600 ° C., and a Sr _0.7 La _0.3 TiO _2.9 film and a SrRuO ₃ film are sequentially formed by sputtering, and sequentially grown epitaxially. If necessary, the film may be annealed at about 700 ° C. after the film is formed and epitaxially formed. The electrode buffer layer 44 of the lower electrode 43 here also has an effect of preventing mutual diffusion between the Si substrate 41 and the capacitor dielectric film 46. In addition, it is important for the application in the DRAM mode to select a material for the lower electrode layer 43 that reduces the leakage current of the dielectric film 46. Here, a SrRuO ₃ film or the like is used as an example.

Next, for example, a (Ba, Sr) TiO ₃ dielectric film is formed as a capacitor insulating film 46 on the entire surface. The dielectric film 46 is formed, for example, by RF magnetron sputtering in a mixed gas atmosphere of Ar and O ₂ at a substrate temperature of 600 ° C. As a sputtering target, a binary target of BaTiO ₃ sintered body and SrTiO ₃ sintered body may be used. The film thickness of the dielectric is about 30 nm, for example.

  Further, the composition of the dielectric film, that is, the ratio of Ba, Sr, and Ti can be adjusted so as to obtain a desired composition ratio by, for example, analysis by ICP emission spectroscopy. It is also important to confirm that the dielectric film thus formed is an epitaxial film oriented in the (100) plane by, for example, X-ray diffraction. In addition to the magnetron sputtering method, the MOCVD method or the like can be used for forming the dielectric film.

Next, the upper electrode 47 is formed on the entire surface. For the formation of the upper electrode 47, the substrate is heated at about 600 ° C., and, for example, SrRuO ₃ is formed to a thickness of, for example, about 50 nm using the sputtering method and epitaxially grown. If necessary, annealing may be performed at about 700 ° C. after film formation to improve interface characteristics and promote epitaxial growth. Next, the upper electrode 47 is processed by normal photolithography and plasma etching (for example, RIE).

The upper electrode 47 corresponds to a storage electrode in the DRAM. Further, a silicon nitride film (Si ₃ N ₄ ) 55 is deposited on the entire surface as a stopper film by about 40 nm. This stopper film 55 serves as an etching stopper film in a later process, and prevents deterioration (composition change, mutual diffusion, etc.) of the dielectric film 46 and the electrode films 44, 45, 47 during annealing in a hydrogen atmosphere, for example. It is effective against.

  Thereafter, an insulating film 56 such as BPSG is deposited on the entire surface, for example, to a thickness of about 500 nm, and is planarized by, for example, a CMP (Chemical Mechanical Polishig) method. This planarization insulating film 56 is an important film used for forming an SOI layer in the next step, and requires flatness within the wafer surface necessary for bonding the Si substrates.

Next, as shown in FIG. 12B, a thermal oxide film (SiO ₂ ) of about 10 nm and a BPSG film (or a CVD-SiO ₂ film) are laminated as an insulating film 57 on the surface of the second Si substrate 48 ′. About 200 nm (can be omitted). Next, the surface side (bonding insulating film 57) of the second Si substrate 48 ′ is bonded together with the planarization insulating film 56 of the first Si substrate 41 on the bonding surface 58. For bonding, a known method such as a heat treatment of about 900 ° C. or a method using a film such as BPSG that can realize adhesiveness at a low temperature as the insulating film to be bonded can be used. Is convenient for stopping at the Si ₃ N ₄ film 55 (described in detail later).

  Next, polishing is performed from the back surface of the second Si substrate 48 ′ to form an SOI substrate (SOI layer) 48 having a thickness of about 150 nm, for example. Other methods for forming various SOI layers such as pasting / polishing may be used. Of course, the surface of the SOI substrate 48 is mirror-polished so as to withstand later transistor formation.

  Here, several cases will be considered regarding the thickness of the SOI layer 48. First, in the case of an SOI layer of about 150 nm to 300 nm, even if STI element isolation of about 0.15 μm is performed, it does not reach the laminated insulating film below the SOI layer. That is, the p-well or n-well (transistor substrate) of the SOI layer is connected. According to such an SOI layer, there is an advantage that leakage of accumulated charges due to a substrate floating effect, which has been a problem in a DRAM using a conventional SOI, can be suppressed.

  In the case of an SOI layer of about 60 nm to 150 nm, the substrate of each SOI transistor is completely separated by STI element separation of about 0.15 μm. That is, the substrate of the SOI layer transistor is in a floating state, but the channel region can be set to be PD (Partial Depletion) by controlling the ion implantation state. Such SOI has a problem that the threshold value cannot be freely set in the conventional SOI structure, but has an advantage that the threshold value can be set relatively easily.

  Furthermore, in the case of an SOI layer of about 60 nm or less, the channel of the SOI transistor is completely depleted, and a so-called FD (Fully Depletion) state is obtained. Such SOI has advantages such as suppressing the short channel effect of the transistor.

Next, as shown in FIG. 12C, a so-called trench type element is formed by digging a groove in the SOI substrate 48 using, for example, reactive ion etching (RIE method) and embedding an insulating film in the groove. An isolation layer 59 (STI (Shallow Trench Isolation) having a trench depth of about 0.15 μm) is formed. At this time, a SiO ₂ film 60 having a thickness of about 5 nm and a Si ₃ N ₄ film 61 having a thickness of about 100 nm are formed in advance on the surface of the SOI layer 48 so as to protect the SOI surface. The surface of the insulating film in which STI is embedded is formed so as to be aligned with the surface of the Si ₃ N ₄ film 61.

Next, the connection hole 62 is opened using plasma etching such as normal photolithography and RIE. As REI conditions at this time, first, etching is performed under the conditions in which both the SOI layer (Si layer) 48 and the SiO ₂ layer of the STI layer 59 are etched, and then the oxide film system etching of the bonding insulating film 57 and the planarizing insulating film 56 is performed. Etching is selectively stopped at the Si ₃ N ₄ film 55. For this, it is preferable to use an etching condition in which the etching rate of the insulating film, for example, the BPSG film is extremely fast (about 15) compared with the etching rate of the Si ₃ N ₄ film.

Next, as shown in FIG. 12D, the Si ₃ N ₄ film 55 at the bottom of the connection hole 62 is selectively removed to expose the surface of the upper electrode 47. At this time, the Si ₃ N ₄ film 61 on the SOI surface is also removed at the same time. Next, a poly-Si film containing N + type impurities is deposited on the entire surface to a thickness of about 200 nm, and the entire surface is etched back by a method such as CMP to form an N + poly-Si layer in the connection hole 62. A buried layer 54 is formed. Thereafter, N + sidewall diffusion layer 63 is formed by annealing at about 800 ° C. for 20 seconds in a nitrogen atmosphere by RTA (Rapid Thermal Anneal) method.

Thereafter, as shown in FIGS. 10 and 11, desired channel ion implantation is performed through the SiO2 film 60 on the surface of the SOI substrate 48, and a channel impurity layer (not shown) for n-channel and p-channel transistors. Form. In the case of an n-channel transistor, for example, in order to set a threshold value (Vth) of about 0.7 V, boron (B +) is ion-implanted, for example, at about 10 KeV, 5 × 10 12 cm ₋₂ and selectively only in the channel region. A p-type channel impurity layer (not shown) is formed. It may be re-form the SiO ₂ film after removing the SiO ₂ film 60.

Next, after removing the SiO ₂ film on the SOI surface to expose the surface of the SOI substrate 48, a gate insulating film (SiO ₂ film) 64 is formed with a film thickness of about 6 nm, for example. Next, an N + poly Si layer 65 (film thickness of about 50 nm), a WSi film (film thickness of about 50 nm) and a cap Si ₃ N ₄ film 66 are sequentially deposited as the gate electrode 49.

Thereafter, the cap Si ₃ N ₄ film 66 is first processed by using, for example, a photolithography method and an RIE method, and the WSi film 49 and the N + poly Si layer 65 are processed using the processed cap Si ₃ N ₄ film 66 as a mask. Is processed into a gate electrode pattern. Here, an example in which WSi / N + poly-Si is used as the gate electrode 49 is shown, but a poly-Si single layer film or another laminated film structure may be used. The cap Si ₃ N ₄ film 66 is a film for use in a self-aligned contact in a later process.

Next, in order to form an LDD (Lightly Doped Drain) structure, for example, phosphorus (P +) ions are implanted into a desired region by photolithography using the gate electrode 49 as a mask at 70 KeV, 4 × 10 13 cm. About -2 is performed to form an n- type source / drain extension layer 67. Next, after depositing the entire surface of the Si ₃ N ₄ film, RIE of a desired region is performed with a resist mask to leave a Si ₃ N ₄ film on the side wall portion of the gate electrode 49, so-called side wall leaving is performed, A Si ₃ N ₄ film having a thickness of about 30 nm (not shown in the figure, existing in a peripheral circuit portion) is formed on the side wall of the electrode 49.

  Then, for example, arsenic (As +) ions are implanted into a desired region by photolithography at 30 KeV, 5 × 10 15 cm −2 to form an n + type diffusion layer (not shown). A so-called LDD structure is formed. Although an LDD structure is used here, a so-called single source / drain method using only an n− type diffusion layer or only an n + type diffusion layer may be used. Here, the source / drain formation in the case of the n channel has been described. However, in the case of the p channel, p @-and p @ + source / drain diffusion layers are formed.

Next, CVD-Si ₃ N ₄ is deposited on the entire surface to a thickness of about 30 nm, for example, to form a stopper Si ₃ N ₄ film 66, and a BPSG film as an interlayer insulating film 52 is deposited on the entire surface to a thickness of about 500 nm. Thereafter, densification is performed for about 30 minutes in an N2 atmosphere at about 800 ° C., for example. This thermal process may also be performed to activate the source / drain ion implantation layer. In order to suppress the depth (Xj) of the diffusion layer, the densify temperature may be lowered to about 750 ° C., and the ion implantation layer may be activated by using an RTA process at 950 ° C. for about 10 seconds.

  Next, the entire surface is planarized by CMP. Next, N @ + poly-Si is buried in the bit line contact region 69, and then contacts (not shown) to the source, drain and gate electrodes, bit line 50, interlayer insulating layer 53, metal wiring layer (Al-Cu). ) 51 are formed sequentially. Further, a passivation film (not shown) is deposited on the entire surface to complete the basic structure of the DRAM.

  In such an element structure, since the high dielectric film (or ferroelectric film) to be the capacitor insulating film 46 can be formed on the flat Si substrate surface, the characteristics of the high dielectric film (or ferroelectric film) are deteriorated. (Increase in leakage current, increase in film fatigue, increase in variation in dielectric constant and polarizability, etc.) can be suppressed.

In addition, since a (100) -oriented Si substrate 41 can be used as a base, doped SrTiO ₃ or SrRuO ₃ that is substantially lattice-matched with Si as an electrode buffer layer 44 or an electrode layer 45 of the lower electrode 43 on the Si substrate 41. Thus, the capacitor insulating film 46 can be stably formed so as not to impair the (220) orientation of the dielectric. Further, since the capacitor is disposed on the lower side of the transistor, the step of the capacitor is eliminated when the wiring layer is formed, and the contact and wiring forming process is facilitated, thereby simplifying the process and simplifying the flattening process. It becomes possible.

  Further, since the high dielectric film (or ferroelectric film) capacitor is formed below the SOI layer 48, it is less susceptible to the influence of subsequent processes (such as plasma damage during contact and wiring formation). In addition, the process damage to the capacitor film can be reduced, and the product yield can be improved. Further, since the capacitor is in the lower region of the transistor, the region below the transistor can be used as the capacitor region, and the area occupied by the capacitor in the memory cell region can be increased without increasing the memory cell area. As a result, the amount of stored charge can be increased, the memory cell operation margin can be increased, and the product yield can be improved.

  In addition, since the (100) oriented lower electrode layers 44 and 45 and the (100) oriented epitaxially grown perovskite crystal structure are formed on the (100) oriented Si substrate, The effect of increasing the ferroelectricity and relative permittivity induced by the constraint with the electrode can be used. This greatly contributes to the solution of the problem of the crystalline dielectric material that the relative dielectric constant and the like are reduced when the film is thinned. As a result, the storage capacity stored in the capacitor can be increased.

  The semiconductor memory device of each of the embodiments described above is an example in which the thin film capacitor having the lower electrode (laminated film of the electrode buffer layer and the electrode layer) according to the present invention is provided on the plug formed on the switching transistor, and the present invention. This is an example in which a substrate provided with a transistor is bonded above a thin film capacitor having a lower electrode (laminated film of an electrode buffer layer and an electrode layer).

  The semiconductor memory device to which the semiconductor device of the present invention is applied is not limited to these, and an electrode buffer layer can be provided on the electrode layer. Hereinafter, an embodiment of a semiconductor memory device having a thin film capacitor having an electrode provided with an electrode buffer layer above the electrode layer according to the present invention and a transistor provided thereabove will be described with reference to FIGS. I will explain.

  FIG. 13 is a cross-sectional view schematically showing a portion corresponding to two unit cells (memory cells) of the DRAM according to this embodiment. In the figure, an epitaxial growth composed of a first electrode 73, a dielectric film 78, and a second electrode 79 is formed on the first main surface side of a thin film silicon layer 84 formed from a p-type Si (100) substrate. A thin film capacitor 96 is formed. The thin film capacitor 96 is formed as a uniformly continuous plane on the first main surface side of the thin film silicon layer 84 in which two adjacent memory cells are formed. Two switching transistors 87A and 87B are formed on the second main surface side facing the first main surface.

  The switching transistor 87A is formed of an n + source region 88, an n + drain region 89, a gate oxide film 90, and a gate electrode 91. The n + drain region 89 of the switching transistor 87A also serves as the n + drain region of the adjacent switching transistor 87B. That is, the switching transistor 87B is formed by the n + drain region 45, the n + source region 88, the gate oxide film 90, and the gate electrode 91.

The gate electrodes 91 of the switching transistors 87A and 87B have a two-layer structure including a doped polysilicon layer 91a and a refractory metal silicide layer 91b such as WSi ₂ , MoSi ₂ , TiSi ₂ . Instead of the refractory metal silicide layer, a refractory metal such as W, Mo, Ti, or Co may be used.

  The gate electrode 91 also serves as a DRAM word line. An n + drain region 89 common to the switching transistors 87a and 87B is connected to the bit line 94 via a contact plug 93. The thin film silicon layer 84 in which the switching transistors 87a and 87B are formed is separated from the adjacent thin film silicon layer by the element isolation insulating film 77. An n + sidewall diffusion layer 86 is formed around the thin film silicon layer 84, and a contact plug 85 made of n + doped polysilicon is formed between the n + sidewall diffusion layer 86 and the element isolation insulating film 77. ing. Further, an n + impurity diffusion layer 72 is formed on the first main surface side of the thin film silicon layer 84. An electrode buffer layer 74 made of an Sr0.7 La0.3 TiO3 film or the like is formed between the electrode layer 75 of the first electrode 73 constituting the thin film capacitor 96 of the DRAM and the n + impurity diffusion layer 72. . The first electrode 73 is separated from adjacent unit cells by a capacitor isolation insulating film 76.

  As shown in FIG. 13, the electrode buffer layer 74 of the first electrode 73 of the thin film capacitor 96 includes the switching transistor 87A or 87B via the contact plug 85, the n + sidewall diffusion layer 86 and the n + impurity diffusion layer 72. Since it is connected to the n + source region 88, the contact resistance is extremely small.

Further, according to the structure shown in FIG. 13, since the thin film silicon layer 84 composed of the (100) surface of the Si substrate 71 can be used as a base, the entire surface of the lower side (first main surface side) of the thin film silicon layer 84 ( 100) oriented Sr _0.7 La _{0. 3} TiO 3 film 74, (100) -oriented SrRuO ₃ film 75 and 79, and (100) -oriented (Ba, Sr) making a like TiO ₃ film 78 stably Can do. For this reason, it is possible to suppress variations in the dielectric constant and leakage current of the regular electric capacitor.

  Further, since the thin film capacitor 96 is formed on the same plane level below the switching transistors 87A and 87B, there is no surface step due to the presence of the thin film capacitor when the wiring layer is formed, and contact and wiring formation are performed. A process becomes easy and simplification of a process and simplification of a planarization process can be achieved. Further, since the first electrode 73 of the thin film capacitor 96 and the switching transistors 87A and 87B can be simultaneously separated by the capacitor isolation insulating film 76 and the element isolation insulating film 77, the mask alignment error is small, and the product yield is improved.

  In addition, since the thin film capacitor 96 is three-dimensionalized in a region on the lower side (first main surface side) of the switching transistors 87A and 87B, the thin film capacitor 96 is provided on the lower side (first main surface side) of the switching transistors 87A and 87B. The entire area can be used as a capacitor area. Therefore, the area occupied by the thin film capacitor in each memory cell can be secured without increasing the area of the memory cell. As a result, the amount of charge stored in the DRAM can be increased and the memory cell operation margin can be increased. Although not shown, the peripheral circuit portion can be made into a thin-film SOI structure by applying an insulating film in place of the thin-film capacitor 41, so that high-speed operation and low-power consumption operation of the transistor are possible. Become.

  Next, with reference to FIGS. 14 to 17, the DRAM manufacturing method of this embodiment will be described by focusing attention only on the switching transistor 87A side.

First, as shown in FIG. 14A, after forming an n + impurity diffusion layer 72 having a depth of about 0.1 μm on the first main surface of a p-type Si (100) substrate 71, a first electrode 73 is formed. A 10 nm thick Sr _0.7 La _0.3 TiO ₃ film as the electrode buffer layer 74 and a 20 nm thick SrRuO ₃ film as the electrode layer 75 are continuously epitaxially grown at a substrate temperature of 600 ° C. by sputtering.

Next, as shown in FIG. 14B, a first groove for separating adjacent capacitors and a second groove for element isolation are formed by photolithography and reactive ion etching (RIE), respectively. Then, an oxide film (SiO ₂ film) is formed as the capacitor isolation insulating film 76 and the element isolation insulating film 77 by using the CVD method. Thereafter, the first main surface side is flattened by CMP. At this time, in order to protect the surface of the electrode layer 75, a method of forming a TiN film or the like in advance as a polishing stopper layer and removing it by etching after CMP can be used.

Next, as shown in FIG. 14 (c), a BSTO thin film having a Ba mole fraction of 30% and a thickness of 20 nm is formed as the dielectric thin film 78, and a 20 nm thick SrRuO ₃ film is formed as the second electrode 79 by RF and Epitaxial growth is performed at a substrate temperature of 600 ° C. by DC sputtering. The BSTO film and the SrRuO ₃ film above the capacitor isolation insulating film 76 and the element isolation insulating film 77 are polycrystalline films. Hereinafter, the polycrystallized BSTO film and SrRuO ₃ film are referred to as “poly BSTO film 78p” and “poly SrRuO ₃ 79p”, respectively. Further, a 200 nm-thick TiN film is formed on the entire surface as the plate electrode 80 at room temperature.

  Next, as shown in FIG. 15A, after a BPSG film is formed to a thickness of, for example, about 500 nm as the bonding insulating film 81, the surface is flattened by, for example, CMP to obtain a mirror surface.

  On the other hand, a support substrate 82 is prepared, and as shown in FIG. 15B, another BPSG film 83 is formed on the support substrate 82, and the surface thereof is flattened to obtain a mirror surface. Then, the mirror surfaces of the BPSG film are brought into contact with each other, and the p-type Si (100) substrate 71 and the support substrate 82 are bonded. For the bonding, a known method shown in the above-described embodiment is used.

  Next, as shown in FIG. 16A, polishing is performed from the second main surface side of the p-type Si (100) substrate 71, and the element isolation insulating film 77 is used as a stop layer, for example, with a thickness of about 150 nm. A thin silicon layer 84 is formed. In order to obtain the thin film silicon layer 84, a method of forming an SOI by bonding such as a smart cut substrate or RIE may be used. Of course, the second main surface of the thin film silicon layer 84 is mirror-polished so that it can withstand a subsequent transistor formation step. The transistor isolation region is also isolated at the same time by the element isolation insulating film 77 formed from the first main surface side.

Next, a connection hole is opened adjacent to the element isolation insulating film 77 by using a dry etching technique such as a normal photolithography method and an RIE method. Etching conditions at this time may be selectively stopped using the electrode buffer layer 74 (Sr _0.7 La _0.3 TiO ₃ film) or the electrode layer 75 (SrRuO ₃ film) as a stopper.

  Next, as shown in FIG. 16B, a doped polysilicon film containing, for example, an n + -type impurity is deposited to a thickness of about 200 nm on the entire surface of the connection hole, and the entire surface is etched back by CMP or the like. As a result, a contact plug 85 made of an n + doped polysilicon film is formed in the connection hole. Thereafter, annealing is carried out in a nitrogen atmosphere at about 800 ° C. for 20 seconds by the RTA method, whereby n + -type impurities are diffused into the p-type Si (100) substrate 71 from the side surface of the connection hole to form an n + sidewall diffusion layer 86. .

  Next, the switching transistor 87A is formed on the second main surface side of the thin film silicon layer 84 using a general MOS process. That is, as shown in FIG. 17, a switching transistor 87A composed of an n + source region 88, an n + drain region 89, a gate oxide film 90, and a gate electrode 91 is formed. Further, a first interlayer insulating film 92 is deposited, the interlayer insulating film 92 above the n + drain region 89 is removed, and a contact plug 93 is embedded to form a bit line 94. Further, if a second interlayer insulating film 95 is deposited on the bit line 94, the DRAM shown in FIG. 17 is completed.

In the above description, only the switching transistor 87A has been described. However, the switching transistor 87B is of course completed simultaneously in the same process. However, as shown in FIG. 17, in the above manufacturing process, the lower part of the capacitor isolation insulating film 76 and the element isolation insulating film 77 is the poly BSTO 78p and the poly SrRuO ₃ film 79p. The DRAM structure shown is slightly different.

  By manufacturing the DRAM by the method shown in FIGS. 14 to 17, the first and second electrodes and the dielectric film of the thin film capacitor are aligned with the orientation of the p-type Si (100) substrate, and the (100) plane is epitaxial. It was confirmed that it was growing. For this reason, a paraelectric film having a very high dielectric constant was obtained, and the dielectric constant was a very large value of 930. Good DRAM operation was confirmed by such a thin plate capacitor using a paraelectric film.

  Next, an embodiment in which the semiconductor device of the present invention is applied to a semiconductor device having an MMIC capacitor will be described with reference to FIG.

In the semiconductor device shown in FIG. 18, an SrTiO ₃ film 102 and a first wiring layer 103 made of an Sr _0.5 La _0.5 TiO ₃ film are arranged in this order on a GaAs substrate 101. A capacitor 104 is formed on the first wiring layer 103. The lower electrode 105 of the capacitor 104 is made of SrRuO ₃ , and the dielectric film 106 is made of SrTiO ₃ (STO).

The upper electrode 107 of the capacitor 104 has a multilayer structure composed of SrRuO ₃ , WNx (tungsten nitride) layer 107a (120 nm) / W layer 107b (300 nm) in order from the bottom. That is, the contact surface of the upper electrode 107 in contact with the dielectric film 106 is SrRuO ₃ . In this capacitor 104, the lower buffer layer also serves as the first wiring layer 103, and the bottom surfaces of the STO film 102, the buffer layer 103, the lower electrode 105, the dielectric film 106, and the upper electrode 107 are all epitaxial films. It has become. Reference numeral 108 denotes an insulating layer, and 109 denotes a wiring layer.

Other STO The dielectric film _{106, Ba x Sr 1-x} TiO 3 (BSTO), Ta 2 O 5, etc. _{PbZr x Ti 1-x O3,} Pb x La 1-x Zr y Ti ly O 3 The metal oxide high dielectric can be used. In the case of a capacitor for MMIC, since it is assumed that it is used at a frequency of 800 MHz or higher, it is a paraelectric property even if its relative dielectric constant is slightly lower than that of a ferroelectric dielectric having poor frequency characteristics. The perovskite dielectrics are suitable.

  In order to produce such an epitaxial capacitor on a GaAs substrate, it is necessary to form a film at a lower temperature than the capacitor on the Si substrate described in each of the above embodiments. In this case, for example, by using the MOCVD method, a single crystal epitaxial capacitor can be formed by film formation at 450 to 500 ° C. Although a capacitor manufactured at such a low temperature has an epitaxial structure, the dielectric constant is slightly smaller than that of a film formed at a higher temperature, but a larger dielectric than that of an ordinary polycrystalline capacitor. Since it exhibits a high rate and a small leakage current, it exhibits excellent characteristics as an MMIC used for microwave applications.

It is sectional drawing which shows the capacitor part of 1st Embodiment of the semiconductor memory device to which this invention is applied. FIG. 8 is a cross-sectional view showing a modification of the capacitor shown in FIG. 1. It is sectional drawing which shows the capacitor part of the semiconductor memory device by Example 1 of this invention. It is a figure which shows the relationship between the applied voltage and dielectric constant of the semiconductor memory device by Example 2 of this invention. It is a figure which shows the relationship between the applied voltage and leakage current density of the semiconductor memory device by Example 2 of this invention. It is sectional drawing which shows the capacitor part of the semiconductor memory device by Example 3 of this invention. It is sectional drawing which shows the principal part of the manufacturing process of the capacitor | condenser part of the semiconductor memory device by Example 7 of this invention. FIG. 8 is a cross-sectional view showing a manufacturing step of the capacitor portion following that of FIG. 7; It is a top view which shows 2nd Embodiment of the semiconductor memory device to which this invention is applied. FIG. 10 is a cross-sectional view taken along the line XX ′ of the semiconductor memory device shown in FIG. 9. FIG. 10 is a cross-sectional view taken along line YY ′ of the semiconductor memory device shown in FIG. 9. FIG. 10 is a cross-sectional view showing a main part of an example of a manufacturing process of the semiconductor memory device shown in FIG. 9. It is sectional drawing which shows 3rd Embodiment of the semiconductor memory device to which this invention is applied. FIG. 14 is a cross-sectional view showing a main part of a manufacturing process of the semiconductor memory device shown in FIG. 13. FIG. 15 is a cross-sectional view showing the manufacturing process of the semiconductor memory device, following FIG. 14; FIG. 16 is a cross-sectional view showing the manufacturing process of the semiconductor memory device, following FIG. 15; FIG. 17 is a cross-sectional view showing the manufacturing process of the semiconductor memory device, following FIG. 16; It is sectional drawing which shows 4th Embodiment of the semiconductor device of this invention.

Explanation of symbols

2, 11, 21, 32 ... plug, 3 ... thin film capacitor, 4 ... lower electrode, 5, 16, 28, 36 ... dielectric thin film, 6, 17, 29, 37 ... upper electrode, 7, 14, 26, 33 ... Electrode buffer layer, 8, 15, 27, 35 ... Electrode layers 13, 25 ... Non-oxide buffer layer

Claims (3)

In a semiconductor device comprising a thin film capacitor having a lower electrode, a dielectric thin film made of a perovskite oxide disposed on the lower electrode, and an upper electrode disposed on the dielectric thin film,
The lower electrode is composed of a laminated film of at least two kinds of conductive perovskite oxides, and is connected to Si via a buffer layer made of a non-oxide having conductivity. Semiconductor device. The semiconductor device according to claim 1,
The lower electrode includes an electrode layer made of a conductive perovskite-type acid disposed so as to be in contact with the dielectric thin film;
A semiconductor device comprising: an electrode buffer layer made of a conductive perovskite oxide that is different from the conductive perovskite oxide constituting the electrode layer and is stable under a low oxygen partial pressure. The semiconductor device according to claim 1,
The lower electrode is disposed in contact with the dielectric thin film, and SrRuO ₃ , Sr _1-x Ba _x RuO ₃ and Sr _1-y RE _y CoO ₃ (RE is at least selected from La, Pr, Sm and Nd) An electrode layer composed of at least one conductive perovskite oxide selected from the group consisting of at least one element wherein x and y are 0 <x <1, and 0 <y <1) AETiO _3-d having AE (AE represents at least one element selected from Sr and Ba) and part of the constituent elements is M element (M represents at least one element selected from Nb and rare earth elements) And an electrode buffer layer made of at least one conductive perovskite oxide selected from AETiO ₃ substituted with the above.

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