JP2005039173A - Thin film transistor and method for manufacturing the same, and display unit and method for manufacturing the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film transistor capable of driving a current driven light emitting element for a long time. <P>SOLUTION: In this thin film transistor 1 wherein a gate insulating film 5 is provided to cover a gate electrode 3 and an amorphous silicon-made channel layer 7, a source 11a, and a drain 11b are successively laminated on the gate insulating film 5, hydrogen concentration in the channel layer 7 becomes increasingly higher from the interface with the gate insulating film 5 toward the interfaces with the source 11a and with the drain 11b. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a thin film transistor particularly suitable for driving a display device using a current-driven element such as an organic EL element, a manufacturing method thereof, a display device, and a manufacturing method thereof.

  A thin film transistor (TFT) using a thin film semiconductor layer is used as a driving element of a flat panel display device. This thin film transistor is formed as follows, for example. First, a silicon thin film formed on a substrate is patterned to form source / drain regions. Next, a silicon thin film is formed again and crystallization is performed by heat treatment. The silicon thin film is patterned to form a channel portion silicon thin film. Thereafter, a gate insulating layer is formed, and a gate electrode is formed on the channel portion silicon thin film via the gate insulating layer (see Patent Document 1 below).

Japanese Patent Laid-Open No. 5-129202 (particularly FIG. 1 and paragraphs 0015 to 0029)

  By the way, among the flat panel display devices, an organic EL display device using an organic EL element as a light emitting element controls light emission of the organic EL element by current driving by a thin film transistor. For this reason, the driving thin film transistor is required to have higher reliability than the liquid crystal display device in which the thin film transistor is used only as a switching element.

  However, in the thin film transistor formed in the above-described process, a thin film transistor in which the channel portion silicon film is formed of amorphous silicon cannot obtain sufficient BT (Baias-Temparater) characteristics, and is unlike an organic EL display device. When used in a current-driven display device, there is a problem that the threshold voltage changes greatly.

  Accordingly, an object of the present invention is to provide a highly reliable thin film transistor that can withstand driving of a current-driven display device and a manufacturing method thereof, and a display device using the thin film transistor and a manufacturing method thereof.

  In order to achieve such an object, the thin film transistor of the present invention includes a source / drain layer, a channel layer made of amorphous silicon, a gate insulating film, and a gate electrode on a substrate in this order or in the reverse order. It is a thin film transistor formed by stacking. In particular, the hydrogen concentration in the channel layer increases from the gate insulating film side interface toward the source / drain layer side interface.

  The thin film transistor having such a configuration has a concentration gradient such that the hydrogen concentration in the channel layer increases from the gate insulating film side interface toward the source / drain layer side interface. As a result, the hydrogen concentration is suppressed at the interface on the gate insulating film side, while a necessary amount of hydrogen concentration is secured at the interface on the source / drain layer side. In addition, by suppressing the hydrogen concentration at the gate insulating film side interface, the change over time in the threshold voltage (ΔVt) can be kept small, and the necessary amount of hydrogen concentration is secured at the source / drain layer side interface. By doing so, the mobility of electrons (carriers) between the source and the drain is ensured.

  In the first thin film transistor manufacturing method according to the present invention, a channel layer made of amorphous silicon is formed on the substrate through a gate insulating film in a state of covering the gate electrode on the substrate, and then the surface of the channel layer is formed. It is characterized by performing hydrogenation treatment on

  According to such a first thin film transistor manufacturing method, it is possible to introduce hydrogen into the channel layer made of amorphous silicon by performing a hydrogenation process on the surface of the channel layer. The hydrogen concentration distribution in the channel layer can be adjusted so that the hydrogen concentration becomes higher. As a result, a bottom-gate thin film transistor having a channel layer in which the hydrogen concentration on the source / drain side is high and the hydrogen concentration on the gate insulating film side is kept low in a state where the source / drain layer is formed on the channel layer is obtained. It is done.

  At this time, a heat treatment for desorbing hydrogen in the channel layer is performed between the formation of the channel layer and the hydrogenation process, or hydrogen in the channel layer is desorbed in forming the channel layer. It shall be performed under heating conditions. Thereby, in the channel layer, the hydrogen concentration on the gate insulating film side can be further suppressed.

  In the second thin film transistor manufacturing method according to the present invention, a first channel layer made of amorphous silicon is formed on a substrate with a gate insulating film interposed between the gate electrode on the substrate, and then one channel is formed. A second channel layer made of amorphous silicon having a hydrogen concentration higher than that of the layer is formed.

  With such a second manufacturing method, a channel layer having a laminated structure in which a second channel layer having a higher hydrogen concentration is formed on the first channel layer on the gate insulating film. Therefore, in the state where the source / drain layer is formed on the channel layer, the bottom gate type thin film transistor having a channel layer in which the hydrogen concentration on the source / drain side is high and the hydrogen concentration on the gate insulating film side is suppressed low Is obtained.

  At this time, a heat treatment for desorbing hydrogen in the first channel layer is performed between the formation of the first channel layer and the formation of the two channel layers, or the formation of the first channel layer is performed in the first channel layer. By performing the heating under the condition that hydrogen in the layer is desorbed, the hydrogen concentration in the first channel layer, that is, the hydrogen concentration in the channel layer portion in contact with the gate insulating film can be further suppressed.

  Furthermore, in the third thin film transistor manufacturing method of the present invention, a first channel layer made of amorphous silicon containing hydrogen is formed on a substrate via a source / drain layer, and then the hydrogen concentration is higher than that of the first channel layer. A second channel layer made of amorphous silicon having a low thickness is formed, and then a gate electrode is formed through a gate insulating film.

  In such a third manufacturing method, the first channel layer containing hydrogen and the second channel layer having a lower hydrogen concentration are laminated in this order from the source / drain layer side. A channel layer is formed. Thus, the channel layer there can be obtained a top gate type thin film transistor having a channel layer having a high hydrogen concentration on the source / drain side and a low hydrogen concentration on the gate insulating film side.

  The display device of the present invention is characterized in that current-driven light-emitting elements connected to the thin film transistor having the above-described structure are formed on a substrate.

  In such a display device, the light emitting element is driven by a thin film transistor in which the amount of change (ΔVt) of the threshold voltage with time is kept small in a state where the mobility of electrons between the source and the drain is ensured. For this reason, the light emitting element is driven stably over a long period of time.

  The method for manufacturing a display device according to the present invention includes any one of the first to third methods described above in manufacturing a display device in which current-driven light emitting elements connected to thin film transistors are formed on a substrate. It has a manufacturing process of a thin film transistor

  According to the thin film transistor of the present invention, in a thin film transistor using a channel layer made of amorphous silicon, the amount of change over time (ΔVt) of the threshold voltage is reduced while securing the mobility of electrons between the source and the drain. Therefore, it is possible to further improve long-term reliability while maintaining initial characteristics.

  Further, according to the display device of the present invention, it is possible to improve the long-term reliability of the display device by using such a thin film transistor for driving a current-driven light emitting element.

  According to the method for manufacturing a thin film transistor of the present invention, it is possible to obtain the thin film transistor having the above-described configuration in which the hydrogen concentration on the source / drain side is high and the hydrogen concentration on the gate insulating film side is kept low.

  Further, according to the method for manufacturing a display device of the present invention, it is possible to obtain a display device provided with the thin film transistor having the above structure.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In each embodiment, the configuration of the thin film transistor, the configuration of the display device using the thin film transistor, the method for manufacturing the thin film transistor, and the method for manufacturing the display device subsequent thereto will be described in this order.

<First Embodiment>
(A) Thin Film Transistor FIG. 1 is a cross-sectional view illustrating the thin film transistor of the first embodiment. A thin film transistor 1 shown in this figure is a bottom gate type thin film transistor, and a gate insulating film 5 made of silicon nitride is formed in a state of covering a gate electrode 3 patterned on a substrate 2 made of glass or the like. A channel layer 7 made of amorphous silicon is patterned on the gate insulating film 5 so as to cover the gate electrode 3. A protective stopper layer 9 made of silicon nitride is patterned on the channel layer 7 so as to be stacked on the gate electrode 3. On the channel layer 7, a source 11 a and a drain 11 b made of an n-type amorphous silicon layer are patterned at positions sandwiching the protective stopper layer 9. The ends of these source 11 a and drain 11 b are stacked on the protective stopper layer 9 and are separated by the protective stopper layer 9. On the gate insulating film 5, a source electrode 13a and a drain electrode 13b, which are partially stacked on the source 11a and the drain 11b, are patterned.

In particular, in the thin film transistor 1 of the present embodiment, the hydrogen concentration in the channel layer 7 made of amorphous silicon is distributed in the depth direction so as to increase from the gate insulating film 5 side toward the source 11a and drain 11b side. It shall have. Specifically, the hydrogen concentration in the channel layer 7 is such that the hydrogen concentration in the vicinity of the interface on the gate insulating film 5 side is 1 × 10 ²¹ (atom / cm ³ ) or less, and the source 11a and drain of the channel layer 7 The hydrogen concentration in the vicinity of the 11b side interface is preferably 3 × 10 ²¹ (atom / cm ³ ) or more.

  The thin film transistor 1 having such a configuration has a concentration gradient so that the hydrogen concentration in the channel layer 7 increases from the gate insulating film 5 side toward the source 11a and drain 11b side. As a result, while the hydrogen concentration is suppressed near the interface of the gate insulating film 5, a necessary amount of hydrogen concentration is ensured near the interface on the source 11a and drain 11b side. Further, by suppressing the hydrogen concentration at the interface on the gate insulating film 5 side, the amount of change (ΔVt) of the threshold voltage over time is suppressed to a small value, and a necessary amount is near the interface on the source 11a and drain 11b side. By securing the hydrogen concentration, the mobility of electrons in the channel layer 7 portion between the source 11a and the drain 11b is secured.

  Table 1 below shows (A) the hydrogen concentration at the gate insulating film 5 side interface in the channel layer 7, (B) the hydrogen concentration at the source 11a and drain 11b side interface in the channel layer 7, and (C) between the source 11a and the drain 11b. (D) shows the value of change in threshold voltage (denoted as ΔVt) after the BT stress test. The stress conditions of the BT stress test are a gate voltage of 15 V, a drain voltage of 0 V, a temperature of 80 ° C., and a stress time of 10,000 seconds. Further, the hydrogen concentration is a measurement result by a secondary ion mass spectrometer, and since the concentration at the interface of the channel layer 7 cannot be measured accurately, the hydrogen concentration in the 5 nm film from the interface on the gate insulating film side is represented by (A) The hydrogen concentration at the gate insulating film side interface and the hydrogen concentration in the 10 nm film from the source / drain side interface are defined as (B) the hydrogen concentration at the source / drain side interface.

  In addition, in FIG. 3 shows the hydrogen concentration distribution in the depth direction in the channel layer measured by a secondary ion mass spectrometer. As shown in this figure, in all the samples, it was confirmed that the hydrogen concentration in the channel layer continuously changed from the source / drain side interface to the gate insulating film side interface. In FIG. 2, “surface concentration” is (B) the hydrogen concentration at the interface of the source 11 a and drain 11 b side in the channel layer 7, and “interface concentration” is (A) the gate insulating film 5 in the channel layer 7. The hydrogen concentration at the side interface.

  As shown in Table 1 above, (A) the lower the hydrogen concentration at the gate insulating film side interface, (D) the threshold voltage change ΔVt after the BT stress test is reduced, and (B) the source / drain side It was confirmed that the higher the hydrogen concentration at the interface, the higher the electron mobility between (C) the source 11a and the drain 11b.

In particular, sample no. 3, the hydrogen concentration near the gate insulating film 5 side interface is 1 × 10 ²¹ (atom / cm ³ ) or less, and the hydrogen concentration near the source 11 a and drain 11 b side interfaces of the channel layer 7 is 3 × 10 ^21. If (atom / cm ³ ) or more, (D) the threshold voltage change ΔVt after the BT stress test can be suppressed to 2 [V], and (C) the electron mobility between the source 11a and the drain 11b is 0. .5 [cm ² / Vsec].

  As a result, in the thin film transistor according to the first embodiment described with reference to FIG. 1, while maintaining the initial characteristics by securing the mobility of electrons between the source 11 a and the drain 11 b, ΔVt is kept small and long-term reliability is ensured. Improvements can be made.

(B) Display Device Next, a configuration example of a display device using such a thin film transistor 1 will be described with reference to FIG. In FIG. 3, the detailed configuration of the thin film transistor 1 is not shown.

  The display device 20 is formed by arraying light emitting elements (here, organic EL elements) 23 connected to the respective thin film transistors 1 on an interlayer insulating film 21 covering the formation surface side of the thin film transistors 1 of the substrate 2. Each organic EL element 23 includes a lower electrode 25 connected to the thin film transistor 1 through a connection hole 21 a formed in the interlayer insulating film 21. These lower electrodes 25 are patterned for each pixel, and the periphery thereof is covered with an insulating film pattern 27 so that only the central portion is widely exposed. In addition, an organic layer 29 including at least a light emitting layer is stacked on the exposed portion of each lower electrode 25 in a patterned state. The light emitting layer is made of an organic material that emits light by recombination of holes and electrons injected into the light emitting layer. An upper electrode 31 is disposed and formed above each organic layer 29 and the insulating film pattern 27 thus patterned in a state where insulation is maintained between the lower electrode 25.

  In this display device 20, the lower electrode 25 is used as an anode (or cathode), and the upper electrode 31 is used as a cathode (or anode). Then, by injecting holes and electrons from the lower electrode 25 and the upper electrode 31 into the organic layer 29 sandwiched between the lower electrode 25 and the upper electrode 31, in the light emitting layer portion of the organic layer 29. Luminescence occurs. When the display device 20 is a top emission type that extracts emitted light from the upper electrode 31 side, the upper electrode 31 is configured by using a material having high light transmittance. On the other hand, when the display device 20 is a transmissive type that extracts emitted light from the substrate 2 side, the substrate 2 and the lower electrode 25 are configured using a material having high light transmittance.

  According to the display device 20 having such a configuration, the thin film transistor 1 having the configuration described with reference to FIG. 1 is connected to the organic EL element 23, whereby the electron mobility between the source 11a and the drain 11b is increased. In the secured state, the organic EL element 23 can be driven by the thin film transistor 1 in which the amount of change (ΔVt) of the threshold voltage with time is kept small. For this reason, it becomes possible to drive the organic EL element 23 stably over a long period of time, and the long-term reliability of the display device 20 using the organic EL element 23 can be improved.

(C) Manufacturing Method Next, a manufacturing method of the thin film transistor 1 having the above-described configuration and a subsequent manufacturing method of the display device will be described.

  First, as shown in FIG. 4A, the substrate 2 is made of a metal having a two-layer structure of aluminum (film thickness of 300 nm) to which about 1% of neodymium is added and molybdenum (film thickness of 50 nm) as an upper layer. The gate electrode 3 is formed by patterning. Thereafter, a gate insulating film 5 made of silicon nitride is formed to a thickness of about 400 nm by plasma CVD.

  Next, as shown in FIG. 4B, a channel layer 7 made of amorphous silicon is formed on the gate insulating film 5 to a thickness of 45 nm.

  Thereafter, subsequent to the formation of the channel layer 7, a heat treatment for desorbing hydrogen in the channel layer 7 is performed. This heat treatment is preferably performed with the surface of the channel layer 7 exposed. At this time, desorption of hydrogen contained in the amorphous silicon starts from a temperature of about 400 ° C., and thus a heat treatment temperature of 400 ° C. or higher is required. As a heat treatment step of 400 ° C. or higher, a method in which the substrate 2 is directly placed on a heater and heated, a method in which infrared rays are radiated to the channel layer 7, a method in which the channel layer 7 is heated with heated nitrogen gas, a heater It is possible to use a method in which heating of the substrate 2 by heating and heating of the channel layer 7 by light using a lamp are used together. The heat treatment temperature is preferably as high as possible unless the substrate 2 is deformed. In particular, by performing heat treatment at 600 ° C. or higher, a sufficient heat treatment effect can be obtained in a short time. For this reason, heat treatment is performed here at 600 ° C. for 5 minutes as an example.

  Then, following this heat treatment, a hydrogenation treatment is performed on the surface of the channel layer 7. As this hydrogenation treatment, hydrogen plasma treatment is performed in which the channel layer 7 is exposed to hydrogen gas plasma. By performing this hydrogen plasma treatment, hydrogen is introduced into the channel layer 7 made of amorphous silicon.

  Next, as shown in FIG. 4C, a protective stopper layer 9 made of silicon nitride is formed to a thickness of 200 nm on the channel layer 7 by plasma CVD.

  Note that a series of process steps from the formation of the gate insulating film 5 described with reference to FIG. 4A to the formation of the protective stopper layer 9 described with reference to FIG. It is desirable to perform processing continuously in a vacuum or without being exposed to a device connected by a transfer device whose inside is kept airtight (so-called multi-chamber device).

  Next, as shown in FIG. 4D, the protective stopper layer 9 is patterned so as to leave the protective stopper layer 9 only immediately above the gate electrode 3 through a photolithography process and an etching process.

  Thereafter, as shown in FIG. 4 (5), an n-type amorphous silicon film 11 containing phosphorus is formed on the channel layer 7 in a thickness of about 50 nm so as to cover the patterned protective stopper layer 9. Thereafter, the n-type amorphous silicon film 11 and the underlying channel layer 7 are patterned in an island shape through photolithography and etching process steps.

  Next, as shown in FIG. 4 (6), a source / drain electrode film 13 is formed by sputtering while covering the n-type amorphous silicon film 11. Thereafter, the source / drain electrode film 13 is patterned to form the source electrode 13a and the drain electrode 13b. Thereafter, the n-type amorphous silicon 11 portion is removed by etching on the protective stopper layer 9 exposed from the source electrode 13a and the drain electrode 13b to form the source 11a and the drain 11b.

  Thus, as described with reference to FIG. 1, the channel protection type thin film transistor 1 in which the channel layer 7 is protected by the protection stopper layer 9 is formed.

  And when manufacturing the display apparatus provided with such a thin-film transistor 1, the following process is performed continuously. That is, as shown in FIG. 3, the substrate 2 provided with the thin film transistor 1 is covered with an interlayer insulating film 21, and a connection hole 21 a connected to the thin film transistor 1 is formed in the interlayer insulating film 21. Thereafter, the lower electrode 25 connected to the thin film transistor 1 through the connection hole 21 a is patterned on the interlayer insulating film 21. Next, after surrounding the lower electrode 25 with an insulating film pattern 27, an organic layer pattern 29 including at least a light emitting layer is formed on the lower electrode 25 exposed from the insulating film pattern 27. Next, the upper electrode 31 is formed so as to cover the organic layer pattern 29 and the insulating film pattern 27. Thereby, the organic EL element 23 connected to the thin film transistor 1 by the lower electrode 25 is formed.

  According to such a manufacturing method, as described with reference to FIG. 4B, after forming the channel layer 7, the surface of the channel layer 7 is subjected to hydrogenation treatment, whereby the gate insulating film 5. The hydrogen concentration distribution in the channel layer 7 is adjusted so that the hydrogen concentration is higher on the surface side than on the interface side. Thus, in the process described with reference to FIG. 4 (6), hydrogen is generated from the gate insulating film 5 side toward the source 11 a and drain 11 b side in the state where the source 11 a and drain 11 b are formed on the channel layer 7. A channel layer 7 having a distribution in which the concentration increases can be formed.

  In particular, in the process described with reference to FIG. 4 (2), a heat treatment for desorbing hydrogen in the channel layer 7 is performed between the formation of the channel layer 7 and the hydrogenation process. 7 can be kept lower than the hydrogen concentration on the gate electrode side.

  Table 2 below shows (E) the heat treatment temperature, (A) the hydrogen concentration at the gate insulating film 5 side interface in the channel layer 7, and (B) the source 11a in the channel layer 7 when the hydrogenation treatment is omitted after the heat treatment. , Hydrogen concentration at the drain 11b side interface, (C) electron mobility between the source 11a and the drain 11b, and (D) change in threshold voltage (denoted as ΔVt) after the BT stress test. The definition of the stress condition and hydrogen concentration in the BT stress test is the same as in Table 1 above.

  In addition, in FIG. 10 shows the hydrogen concentration distribution in the depth direction in the channel layer measured by a secondary ion mass spectrometer. As shown in this figure, in all the samples, it was confirmed that the hydrogen concentration in the channel layer continuously changed from the source / drain side interface to the gate insulating film side interface. In FIG. 5, “surface concentration” is (B) the hydrogen concentration at the source 11 a and drain 11 b side interface in the channel layer 7, and “interface concentration” is (A) the gate insulating film 5 in the channel layer 7. The hydrogen concentration at the side interface.

  Also from Table 2, (A) the lower the hydrogen concentration at the gate insulating film side interface, the lower the (D) threshold voltage change ΔVt after the BT stress test, and (B) the source / drain side interface. It was confirmed that the higher the hydrogen concentration, the higher the electron mobility between (C) the source 11a and the drain 11b. However, from Table 2 and FIG. 5 above, the concentration of the hydrogen concentration contained in the channel layer 7 is sufficient in the direction of increasing from the gate insulating film 5 side toward the source 11a and drain 11b side only by the heat treatment. It can be seen that a state having a gradient cannot be achieved, and further, it is impossible to achieve both high electron mobility to ensure reliability and low ΔVt to obtain initial characteristics. .

  Table 3 below shows (E) heat treatment temperature, (F) hydrogenation time, (A) hydrogen concentration at the gate insulating film 5 side interface, and (B) when hydrogenation is performed after heat treatment. The values of the hydrogen concentration at the interface between the source 11a and the drain 11b, (C) the mobility of electrons between the source 11a and the drain 11b, and (D) the change in threshold voltage (denoted by ΔVt) after the BT stress test are shown. The definition of the stress condition and hydrogen concentration in the BT stress test is the same as in Table 1 above.

  The sample No. in Table 3 The hydrogen concentration distribution in the depth direction in the 13 channel layers corresponds to the hydrogen concentration distribution of FIG.

From Table 3 and FIG. 2, the hydrogen concentration distribution sufficiently increases the hydrogen concentration distribution contained in the channel layer 7 from the gate insulating film 5 side toward the source 11 a and drain 11 b side. It turns out that it will be in the state which has a sufficient concentration gradient. Further, by adjusting the conditions of the hydrogenation treatment, specifically, by adjusting the treatment time, the electron mobility is kept high at 0.5 [cm ² / Vsec], and ΔVt is 2 [V]. Thus, it is possible to obtain the above-described thin film transistor 1 that is kept low.

  FIG. 6 shows the relationship between the gate voltage and the drain current when the hydrogenation treatment is performed and not performed after the heat treatment temperature of 600 ° C. (5 minutes). From this figure, it can be seen that by performing a hydrogenation treatment after sufficient heat treatment, the electron mobility between the source and the drain in the channel layer is secured, and the thin film transistor 1 can be operated.

  Further, in the above manufacturing process, the steps from the formation of the gate insulating film 5 to the formation of the channel layer 7 are performed without being exposed to the atmosphere, thereby improving the adhesion between the gate insulating film 5 and the channel layer 7. Therefore, process problems such as film peeling can be prevented and throughput can be increased, so that a thin film transistor with high reliability can be formed at low cost.

  As described above with reference to FIG. 4B, in the first embodiment, the procedure for performing the heat treatment and the hydrogenation treatment successively after the formation of the channel layer 7 is used. Then, after the gate insulating film 5 and the channel layer 7 are formed, hydrogenation treatment may be performed. Even if it is such a process, the same effect can be acquired. Further, with such a process, it is not necessary to perform a special heat treatment process, so that the number of processes can be reduced and the thin film transistor 1 can be formed with high throughput.

  Further, in the first embodiment, as described with reference to FIG. 4B, the procedure in which the heat treatment and the hydrogenation treatment are continuously performed after the formation of the channel layer 7 is described. Immediately after the formation, a silicon oxide film having a thickness of about 10 nm may be formed, followed by heat treatment and hydrogenation treatment.

Second Embodiment
(A) Thin Film Transistor FIG. 7 is a cross-sectional view for explaining the thin film transistor of the second embodiment. The difference between the thin film transistor 1 'shown in this figure and the thin film transistor (1) described in the first embodiment is that the channel layer 7 made of amorphous silicon has a two-layer structure. The same shall apply.

That is, the channel layer 7 is composed of a first channel layer 7a formed immediately above the gate insulating film 5 and a second channel layer 7b on the source / drain side stacked on the first channel layer 7a. The hydrogen concentration of the first channel layer 7a is lower than the hydrogen concentration of the second channel layer 7b on the source 11a and drain 11b side. The first channel layer (H−) 7a has a hydrogen concentration of 1 × 10 ²¹ (atom / cm ³ ) or less, and the second channel layer 7b (H +) on the source 11a and drain 11b side has a hydrogen concentration. It is preferably 3 × 10 ²¹ (atom / cm ³ ) or more.

The channel layer 7 is not limited to a two-layer structure, and has a multilayer structure of three or more layers as long as the hydrogen concentration increases from the gate insulating film 5 side toward the source 11a and drain 11b side. There may be. Further, even in such a multilayer structure of three or more layers, the hydrogen concentration of the channel layer arranged in contact with the gate insulating film 5 is 1 × 10 ²¹ (atom / cm ³ ) or less, and the source 11a, The hydrogen concentration of the channel arranged in contact with the drain 11b is preferably 3 × 10 ²¹ (atom / cm ³ ) or more.

  Even with the thin film transistor 1 ′ having such a configuration, the same effect as the thin film transistor (1) of the first embodiment can be obtained.

(B) Display Device Next, the configuration of the display device using such a thin film transistor 1 ′ can be exemplified by the display device described with reference to FIG. be able to.

(C) Manufacturing Method Next, a manufacturing method of the thin film transistor 1 ′ having the above-described configuration and a subsequent manufacturing method of the display device will be described.

  First, the process shown in FIG. 8A is performed in the same manner as described with reference to FIG. 4A in the first embodiment, and the gate electrode 3 is formed on the substrate 2 made of glass. A gate insulating film 5 is formed.

Thereafter, as shown in FIG. 8B, a first channel layer 7 a made of amorphous silicon is formed on the gate insulating film 5. Thereafter, subsequent to the formation of the first channel layer 7a, a heat treatment for desorbing hydrogen in the first channel layer 7a is performed. This heat treatment is performed in the same manner as described in the first embodiment with reference to FIG. As a result, the hydrogen concentration of the first channel layer 7a is set to 1 × 10 ²¹ (atom / cm ³ ) or less. Here, hydrogen desorption from the first channel layer 7a may be performed simultaneously with the film formation by performing the film formation of the first channel layer 7 at the same temperature as the heat treatment.

Next, as shown in FIG. 8C, a second channel layer 7b made of amorphous silicon having a higher hydrogen concentration than the first channel layer 7a is formed on the first channel layer 7a. Here, after the second channel layer 7b is formed, hydrogen treatment is performed by introducing hydrogen from the surface side of the second channel layer 7b, so that the hydrogen concentration of the second channel layer 7a is 3 × 10 ²¹ (atom / cm ³ ) or more. Here, the second channel layer 7b may be formed in an atmosphere containing hydrogen gas so that the second channel layer 7b contains a necessary amount of hydrogen simultaneously with the film formation.

  As described above, the channel layer 7 made of amorphous silicon is formed by laminating the first channel layer 7a (H−) and the second channel layer (H +) 7b having a higher hydrogen concentration in this order. The When the channel layer 7 has a stacked structure of three or more layers, the hydrogen concentration is adjusted in the formation of the above-described second channel layer so that the hydrogen concentration in the channel layer formed in the upper layer becomes higher. An upper channel layer is formed.

  The subsequent steps are performed in the same manner as described with reference to FIGS. 4 (3) to 4 (6) in the first embodiment, so that the channel etch including the channel layer 7 having the stacked structure shown in FIG. A thin film transistor 1 ′ is formed.

  The subsequent steps when manufacturing a display device including such a thin film transistor 1 'are performed in the same manner as described in the first embodiment.

  Even in the manufacturing method described above, similarly to the first embodiment, the bottom gate having the channel layer 7 in which the hydrogen concentration on the source 11a and drain 11b side is high and the hydrogen concentration on the gate insulating film 5 side is suppressed low. Since the thin film transistor 1 ′ is obtained, the same effects as those of the manufacturing method of the first embodiment can be obtained.

<Third Embodiment>
(A) Thin Film Transistor FIG. 9 is a cross-sectional view illustrating a thin film transistor according to a third embodiment. The difference between the thin film transistor 1 "shown in this figure and the thin film transistor (1) described in the first embodiment is that the protective stopper layer 9 made of silicon nitride is not provided on the channel layer 7, The configuration is the same.

  Even in the thin film transistor 1 ″ having such a configuration, the hydrogen concentration in the channel layer 7 is set in the same manner as the channel layer of the thin film transistor (1) described in the first embodiment. The same effect as the thin film transistor (1) can be obtained.

(B) Display Device Next, as a configuration of a display device using such a thin film transistor 1 ″, the display device described with reference to FIG. 2 can be exemplified, and the same effects as those of the first embodiment can be obtained. be able to.

(C) Manufacturing Method Next, a manufacturing method of the thin film transistor 1 ″ having the above-described configuration and a subsequent manufacturing method of the display device will be described.

  First, the steps shown in FIGS. 10 (1) and 10 (2) are performed in the same manner as described with reference to FIGS. 4 (1) to 4 (2) in the first embodiment, and on the substrate 2 made of glass. Then, the gate electrode 3 is formed, the gate insulating film 5 made of silicon nitride is formed, the channel layer 7 made of amorphous silicon is further formed, and then heat treatment and hydrogenation treatment are subsequently performed. However, the channel layer 7 is formed to a thickness of about 200 nm, which is thicker than in the first embodiment.

  Thereafter, as shown in FIG. 10 (3), an n-type amorphous silicon film 11 containing phosphorus to be a source / drain region of the transistor is formed to a thickness of about 50 nm.

  A series of processes from the formation of the gate insulating film 5 described with reference to FIG. 10A to the formation of the n-type amorphous silicon film 11 described with reference to FIG. It is desirable to carry out the treatment continuously in a vacuum without being put in, or in an apparatus (so-called multi-chamber apparatus) connected by a conveying apparatus in which the inside is kept airtight.

  Next, as shown in FIG. 10 (4), the n-type amorphous silicon film 11 and the underlying channel layer 7 are patterned in an island shape through a photolithography process and an etching process.

  Thereafter, as shown in FIG. 10 (5), a source / drain electrode film 13 is formed on the gate insulating film 5 by sputtering while covering the n-type amorphous silicon film 11.

  Next, as shown in FIG. 10 (6), the source / drain electrode film 13 is patterned to form the source electrode 13 a and the drain electrode 13 b, and the n-type amorphous silicon 11 is etched and separated on the channel layer 7. Thus, the source 11a and the drain 11b are formed.

  Thus, the channel etch type thin film transistor 1 ″ is formed.

  The subsequent process in manufacturing a display device including such a thin film transistor 1 ″ is performed in the same manner as described in the first embodiment.

  Even in the manufacturing method described above, the same process as that described with reference to FIG. 4B in the first embodiment is performed in the process shown in FIG. The same effect can be obtained.

  Further, by performing the steps from the formation of the gate insulating film 5 to the formation of the n-type amorphous silicon 11 without exposing them to the atmosphere, the adhesion between the gate insulating film 5-channel layer 7-n-type amorphous silicon 11 is improved. Therefore, the occurrence of process problems such as film peeling can be prevented, and the throughput can be increased, so that a highly reliable thin film transistor can be formed at low cost.

  In the third embodiment, as described with reference to FIG. 10B, the heat treatment and the hydrogenation treatment are performed following the formation of the channel layer 7. However, after the channel layer 7 is formed, heat treatment is performed, and then the n-type amorphous silicon film 11 is formed. Further, as shown in FIG. 10 (6), the source electrode 13a and the drain electrode 13b are formed to form the channel layer 7 The upper amorphous silicon film 11 may be etched to form the source 11a and the drain 11b, and then a hydrogenation process may be applied. Even in such a process, since hydrogen is introduced from the channel layer 7 exposed between the source 11a and the drain 11b, the hydrogen concentration on the interface side of the gate insulating film 5 is low, and the distance between the source 11a and the drain 11b is low. A thin film transistor 1 ″ having a high hydrogen concentration in the channel layer 7 can be obtained.

  Further, in the third embodiment, the configuration of the channel layer 7 can be combined with the second embodiment by adopting the same laminated structure as described in the second embodiment.

<Fourth embodiment>
(A) Thin Film Transistor FIG. 11 is a cross-sectional view illustrating a thin film transistor according to a fourth embodiment. The thin film transistor 1a shown in this figure is a top gate type thin film transistor, and a channel layer 7 is provided in a state where both ends are overlapped with the end portions of the source 11a and the drain 11b patterned on the substrate 2. A gate electrode 3 is laminated on the channel layer 7 via a gate insulating film 5 provided so as to cover them. In such a thin film transistor 1a, as in the thin film transistors of the first to third embodiments, the hydrogen concentration in the channel layer 7 made of amorphous silicon increases from the gate insulating film 5 side toward the source 11a and drain 11b side. As described above, it has a distribution in the depth direction.

Here, the channel layer 7 has a two-layer structure as in the second embodiment, and the first channel layer 7c formed immediately above the source 11a and the drain 11b, and the insulating film layer stacked on the first channel layer 7c. The second channel layer 7d is configured such that the hydrogen concentration of the second channel layer 7d on the gate insulating film 5 side is lower than the hydrogen concentration of the first channel layer 7c on the source 11a and drain 11b side. The first channel layer (H +) 7c on the source 11a and drain 11b side has a hydrogen concentration of 3 × 10 ²¹ (atom / cm ³ ) or more, and the second channel layer (H−) 7d on the gate insulating film 5 side. The hydrogen concentration is preferably 1 × 10 ²¹ (atom / cm ³ ) or less.

The channel layer 7 is not limited to a two-layer structure, and has a multilayer structure of three or more layers as long as the hydrogen concentration increases from the gate insulating film 5 side toward the source 11a and drain 11b side. There may be. Further, even in such a multilayer structure of three or more layers, the hydrogen concentration of the channel layer arranged in contact with the gate insulating film 5 is 1 × 10 ²¹ (atom / cm ³ ) or less, and the source 11a, The hydrogen concentration of the channel arranged in contact with the drain 11b is preferably 3 × 10 ²¹ (atom / cm ³ ) or more.

  Even in the thin film transistor 1a having such a configuration, the hydrogen concentration in the channel layer 7 is set in the same manner as the channel layer of the thin film transistor (1) described in the first embodiment, whereby the thin film transistor of the first embodiment. The same effect as (1) can be obtained.

(B) Display Device Next, as a configuration of the display device using such a thin film transistor 1a, the display device described with reference to FIG. 2 can be exemplified, and the same effect as in the first embodiment can be obtained. Can do.

(C) Manufacturing Method Next, in the manufacturing method of the thin film transistor 1a having the above-described configuration and the manufacturing method of the display device subsequent thereto, each of the channel layers 7c and 7d is desired in a normal top gate type stacked thin film transistor manufacturing process. Amorphous silicon forming the first channel layer (H +) 7c and amorphous silicon forming the second channel layer (H−) 7d are formed so that the hydrogen concentration is obtained.

  The subsequent process in manufacturing a display device including such a thin film transistor 1a is performed in the same manner as described in the first embodiment.

  As described above, the thin film transistor 1a of the fourth embodiment and the display device using the same are obtained.

  It can be applied to a thin film transistor for driving a light emitting element by current drive and a display device provided with the light emitting element.

It is sectional drawing which shows the structure of the thin-film transistor of 1st Embodiment. It is a graph (1) which shows the hydrogen concentration distribution of the depth direction in a channel layer. 1 is a cross-sectional view of a display device using a thin film transistor of the present invention. FIG. 3 is a cross-sectional process diagram illustrating a method for manufacturing the thin film transistor of FIG. 1. It is a graph (2) which shows the hydrogen concentration distribution of the depth direction in a channel layer. It is a figure which shows the relationship between the presence or absence of a hydrogenation process, a gate voltage, and a drain current. It is sectional drawing which shows the structure of the thin-film transistor of 2nd Embodiment. FIG. 8 is a cross-sectional process diagram illustrating a method for manufacturing the thin film transistor of FIG. 7. It is sectional drawing which shows the structure of the thin-film transistor of 3rd Embodiment. FIG. 10 is a cross-sectional process diagram illustrating a method for manufacturing the thin film transistor of FIG. 9. It is sectional drawing which shows the structure of the thin-film transistor of 4th Embodiment.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1,1 ', 1 ", 1a ... Thin-film transistor, 2 ... Substrate, 3 ... Gate electrode, 5 ... Gate insulating film, 7 ... Channel layer, 7a, 7c ... 1st channel layer, 7b, 7d ... 2nd channel layer, DESCRIPTION OF SYMBOLS 11a ... Source, 11b ... Drain, 20 ... Display apparatus, 23 ... Organic EL element (light emitting element)

Claims (18)

In a thin film transistor in which a source / drain layer, a channel layer made of amorphous silicon, a gate insulating film, and a gate electrode are stacked in this order or in the reverse order on a substrate,
A thin film transistor, wherein a hydrogen concentration in the channel layer increases from the gate insulating film side interface toward the source / drain layer side interface. The thin film transistor according to claim 1, wherein
The hydrogen concentration at the gate insulating film side interface of the channel layer is 1 × 10 ²¹ (atom / cm ³ ) or less,
2. A thin film transistor, wherein a hydrogen concentration at the source / drain layer side interface of the channel layer is 3 × 10 ²¹ (atom / cm ³ ) or more. A thin film transistor characterized by forming a channel layer made of amorphous silicon over a gate insulating film on the substrate in a state of covering a gate electrode on the substrate, and then performing a hydrogenation process on the surface of the channel layer. Production method. In the manufacturing method of the thin-film transistor of Claim 3,
A method for manufacturing a thin film transistor, wherein a heat treatment for desorbing hydrogen in the channel layer is performed between the formation of the channel layer and the hydrogenation treatment. In the manufacturing method of the thin-film transistor of Claim 3,
The method for manufacturing a thin film transistor, characterized in that the channel layer is formed under heating conditions in which hydrogen in the channel layer is eliminated. Forming a first channel layer made of amorphous silicon on the substrate through a gate insulating film in a state of covering the gate electrode on the substrate;
A method of manufacturing a thin film transistor, comprising: forming a second channel layer made of amorphous silicon having a hydrogen concentration higher than that of the first channel layer on the first channel layer. In the manufacturing method of the thin-film transistor of Claim 6,
A method of manufacturing a thin film transistor, comprising: performing heat treatment for desorbing hydrogen in the first channel layer after forming the first channel layer and before forming the two-channel layer. In the manufacturing method of the thin-film transistor of Claim 6,
The first channel layer is formed under heating conditions in which hydrogen in the first channel layer is desorbed,
A method for manufacturing a thin film transistor. Forming a first channel layer made of amorphous silicon containing hydrogen on a substrate via a source / drain layer;
Forming a second channel layer made of amorphous silicon having a hydrogen concentration lower than that of the first channel layer on the first channel layer;
A gate electrode is formed on the second channel layer through a gate insulating film. A method of manufacturing a thin film transistor, comprising: A thin film transistor in which a source / drain layer, a channel layer made of amorphous silicon, a gate insulating film, and a gate electrode are stacked in this order or in the reverse order, and a current-driven light emitting element connected to the thin film transistor In a display device having an array formed thereon,
The display device, wherein the hydrogen concentration in the channel layer increases from the gate insulating film side interface toward the source / drain layer side interface. The display device according to claim 10.
The hydrogen concentration at the gate insulating film side interface of the channel layer is 1 × 10 ²¹ (atom / cm ³ ) or less,
The display device, wherein the hydrogen concentration at the source / drain layer side interface of the channel layer is 3 × 10 ²¹ (atom / cm ³ ) or more. A thin film transistor in which a source / drain layer is provided via a channel layer made of amorphous silicon on a gate insulating film covering a gate electrode, and a current drive type light emitting element connected to the thin film transistor are arrayed on a substrate. A display device manufacturing method comprising:
Forming a channel layer made of amorphous silicon on the substrate through a gate insulating film in a state of covering the gate electrode on the substrate, and then performing a hydrogenation process on the surface of the channel layer. A display device manufacturing method. In the manufacturing method of the display device according to claim 12,
A method for manufacturing a display device, comprising: performing a heat treatment for desorbing hydrogen in the channel layer between the formation of the channel layer and the hydrogenation treatment. In the manufacturing method of the display device according to claim 12,
The method for manufacturing a display device is characterized in that the channel layer is formed under heating conditions in which hydrogen in the channel layer is desorbed. A thin film transistor in which a source / drain layer is provided via a channel layer made of amorphous silicon on a gate insulating film covering a gate electrode, and a current drive type light emitting element connected to the thin film transistor are arrayed on a substrate. A display device manufacturing method comprising:
A first channel layer made of amorphous silicon is formed on the substrate through a gate insulating film in a state of covering the gate electrode on the substrate, and then the hydrogen concentration is higher than that of the first channel layer on the first channel layer. A method for manufacturing a display device, comprising: forming a second channel layer made of high amorphous silicon. In the manufacturing method of the display device according to claim 15,
A method for manufacturing a display device, comprising the step of performing a heat treatment for desorbing hydrogen in the first channel layer after forming the first channel layer and before forming the two-channel layer. . In the manufacturing method of the display device according to claim 15,
The method for manufacturing a display device is characterized in that the first channel layer is formed under heating conditions in which hydrogen in the first channel layer is desorbed. A thin film transistor in which a gate electrode is provided on a channel layer made of amorphous silicon covering a source / drain layer via a gate insulating film, and a current drive type light emitting element connected to the thin film transistor are arrayed on a substrate. A display device manufacturing method comprising:
Forming a first channel layer made of amorphous silicon containing hydrogen via a source / drain layer on the substrate;
Forming a second channel layer made of amorphous silicon having a hydrogen concentration lower than that of the first channel layer on the first channel layer;
Forming a gate electrode on the second channel layer through a gate insulating film. A method of manufacturing a display device, comprising:

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