JP2005038962A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a substrate itself from being included into a feedback loop when a noise voltage generated in a digital circuit is reduced by a noise reducing circuit. <P>SOLUTION: A semiconductor integrated circuit, on which a digital circuit and an analog circuit are mounted under a mixed state, is provided with a noise reducing circuit 15 constituted of a differential amplifier 16 having an inversion input terminal, a noninverting input terminal, and an output terminal while the inversion input terminal is connected to a border guard band region 14 in the semiconductor integrated circuit and the noninverting input terminal is connected to the node of a reference potential; and a capacitance 17 for feedback, which is connected between the differential amplifier 16 and the inversion input terminal. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

なお、４〜６式において、
ΔＶｉｎ１＝ΔＶｇｓ１＋ΔＶｃｏｍ …（７）
ΔＶｉｎ２＝ΔＶｇｓ２＋ΔＶｃｏｍ …（８）
ΔＶｉｎ３＝ΔＶｇｓ３＋ΔＶｃｏｍ …（９）
である。
【０１０２】
すなわち、各入力電圧は平衡状態における直流分Ｖｉｎｘ０（ｘ＝１，２，３）と変動分（小信号交流分）ΔＶｉｎｘ（ｘ＝１，２，３）で表すことができる。
【０１０３】
このとき、トランジスタＮ１１、Ｎ１２、Ｎ１３のドレイン電流Ｉｄ１、Ｉｄ２、Ｉｄ３も、平衡状態における直流電流値Ｉｄ１０、Ｉｄ２０、Ｉｄ２０と、小信号交流分ΔＩｄ１、ΔＩｄ２、ΔＩｄ３で表すことができる。
【０１０４】
つまり、下記の１０〜１２式が成立する。
【０１０５】
Ｉｄ１＝Ｉｄ１０＋ΔＩｄ１ …（１０）
Ｉｄ２＝Ｉｄ２０＋ΔＩｄ２ …（１１）
Ｉｄ３＝Ｉｄ３０＋ΔＩｄ３ …（１２）
テール電流、つまり電流源用のトランジスタＮ１４に流れる電流Ｉｓｓは、トランジスタＮ１１、Ｎ１２、Ｎ１３のドレイン電流の和（Ｉｄ１＋Ｉｄ２＋Ｉｄ３）に等しく、このテール電流を、平衡状態における電流Ｉｓｓ０と変動分ΔＩｓｓに分けると下記の１３式が得られる。
【０１０６】

なお、
Ｉｓｓ０＝Ｉｄ１０＋Ｉｄ２０＋Ｉｄ３０ …（１４）
ΔＩｓｓ＝ΔＩｄ１＋ΔＩｄ２＋ΔＩｄ３ …（１５）
である。
【０１０７】
ここで、トランジスタＮ１１、Ｎ１２、Ｎ１３は全て飽和領域で動作するものとした場合の、各トランジスタのドレイン電流とゲート電圧の関係を求める。ＭＯＳトランジスタの基本式から、各ドレイン電流は下記の１６〜１８式で与えられる。
【０１０８】
Ｉｄ１＝（μＣｏｘ／２）（Ｗ１／Ｌ１）（Ｖｇｓ１−Ｖｔｈ）^２（１＋λＶｄｓ１） …（１６）
Ｉｄ２＝（μＣｏｘ／２）（Ｗ２／Ｌ２）（Ｖｇｓ２−Ｖｔｈ）^２（１＋λＶｄｓ２） …（１７）
Ｉｄ３＝（μＣｏｘ／２）（Ｗ３／Ｌ３）（Ｖｇｓ３−Ｖｔｈ）^２（１＋λＶｄｓ３） …（１８）
なお、１６〜１８式において、μはキャリアの移動度、Ｃｏｘはゲート絶縁膜の誘電率、Ｗｘ（ｘ＝１，２，３）は各トランジスタのチャネル幅、Ｌｘ（ｘ＝１，２，３）は各トランジスタのチャネル長であり、Ｖｔｈは閾値電圧である。
【０１０９】
ここで、
ΔＩｄｘ＝Ｉｄｘ−Ｉｄｘ０＝（∂Ｉｄｘ／∂Ｖｇｓｘ）ΔＶｇｓｘ＋（∂Ｉｄｘ／∂Ｖｄｓｘ）ΔＶｄｓｘ ［ｘ＝１，２，３］…（１９）
を用いて、小信号ドレイン電流ΔＩｄ１、ΔＩｄ２、ΔＩｄ３を求めると、下記の２０〜２２式が得られる。
【０１１０】
ΔＩｄ１＝Ｉｄ１−Ｉｄ１０＝ｇｍ１ΔＶｇｓ１＋（１／ｒｏ１）ΔＶｄｓ１ …（２０）
ΔＩｄ２＝Ｉｄ２−Ｉｄ２０＝ｇｍ２ΔＶｇｓ２＋（１／ｒｏ２）ΔＶｄｓ２ …（２１）
ΔＩｄ３＝Ｉｄ３−Ｉｄ３０＝ｇｍ３ΔＶｇｓ３＋（１／ｒｏ３）ΔＶｄｓ３ …（２２）
ただし、ｇｍｘ［＝∂Ｉｄｘ／∂Ｖｇｓｘ］は各トランジスタの相互コンダクタンスであり、ｒｏｘ［（＝∂Ｉｄｘ／∂Ｖｄｓｘ）^−１］は各トランジスタの出力抵抗であり、ｇｍｘ（ｘ＝１，２，３）は下記の２３〜２５式で表される。
【０１１１】
ｇｍ１≒μＣｏｘ（Ｗ１／Ｌ１）（Ｖｇｓ１０−Ｖｔｈ）（１＋λＶｄｓ１０）≒｛２μＣｏｘ（Ｗ１／Ｌ１）Ｉｄ１０｝^１／２…（２３）
ｇｍ２≒μＣｏｘ（Ｗ２／Ｌ２）（Ｖｇｓ２０−Ｖｔｈ）（１＋λＶｄｓ２０）≒｛２μＣｏｘ（Ｗ２／Ｌ２）Ｉｄ２０｝^１／２…（２４）
ｇｍ３≒μＣｏｘ（Ｗ３／Ｌ３）（Ｖｇｓ３０−Ｖｔｈ）（１＋λＶｄｓ３０）≒｛２μＣｏｘ（Ｗ３／Ｌ３）Ｉｄ３０｝^１／２…（２５）
ここで、
１／ｒｏ１≒λ（μＣｏｘ／２）（Ｗ１／Ｌ１）（Ｖｇｓ１０−Ｖｔｈ）^２≒λＩｄ１０ …（２６）
１／ｒｏ２≒λ（μＣｏｘ／２）（Ｗ２／Ｌ２）（Ｖｇｓ２０−Ｖｔｈ）^２≒λＩｄ２０ …（２７）
１／ｒｏ３≒λ（μＣｏｘ／２）（Ｗ３／Ｌ３）（Ｖｇｓ３０−Ｖｔｈ）^２≒λＩｄ３０ …（２８）
で表される。
【０１１２】
次に、小信号ドレイン電流により、トランジスタＮ１１、Ｎ１２、Ｎ１３の出力端子（Ｖｏｕｔ１，Ｖｏｕｔ２，Ｖｏｕｔ３）に生じる小信号電圧分を求める。これら各トランジスタＮ１１、Ｎ１２、Ｎ１３の負荷となるＰチャネルトランジスタＰ１１、Ｐ１２、Ｐ１３には一定のゲートバイアス電圧Ｖｂｐが印加されており、小信号においてはそれぞれ等価的に抵抗ｒｐ１，ｒｐ２，ｒｐ３で表すことができる。出力端子における小信号電圧ΔＶｏｕｔ１，ΔＶｏｕｔ２，ΔＶｏｕｔ３は、これらの等価抵抗ｒｐ１，ｒｐ２，ｒｐ３の電圧降下分で表されるので、下記の２９〜３１式が成立する。
【０１１３】
ΔＶｏｕｔ１＝−ｒｐ１ΔＩｄ１＝−ｒｐ１｛ｇｍ１ΔＶｇｓ１＋（１／ｒｏ１）ΔＶｄｓ１｝ …（２９）
ΔＶｏｕｔ２＝−ｒｐ２ΔＩｄ２＝−ｒｐ２｛ｇｍ２ΔＶｇｓ２＋（１／ｒｏ２）ΔＶｄｓ２｝ …（３０）
ΔＶｏｕｔ３＝−ｒｐ３ΔＩｄ３＝−ｒｐ３｛ｇｍ３ΔＶｇｓ３＋（１／ｒｏ３）ΔＶｄｓ３｝ …（３１）
また、電流源であるＮチャネルトランジスタＮ１４には一定のゲートバイアス電圧Ｖｂｎが印加されており、小信号に着目すると、等価的に抵抗ｒｓで表すことができる。テール電流Ｉｓｓは、負荷抵抗ｒｐ１，ｒｐ２，ｒｐ３を流れる電流の合計に等しく、小信号電流ΔＩｓｓについて、下記の３２式が成立する。
【０１１４】

以上により、小信号電圧、電流成分の等価回路を表すことができる。
【０１１５】
つまり、上記７〜９式、１４式、１５式、２０〜２２式、２９〜３１式、３２式に基づき、図１４に示す３入力の差動段は、図１５に示すような小信号等価回路で表すことができる。
【０１１６】
図１５の等価回路から入出力伝達特性を求める。
【０１１７】
ここで、電圧の変動分ΔＶｉｎ、ΔＶｏｕｔ、ΔＶｇｓ、ΔＶｃｏｍをｖｉｎ、ｖｏｕｔ、ｖｇｓ、ｖｃｏｍでそれぞれ表すことにする。
【０１１８】
上記２９〜３１式と１０〜１２式をそれぞれ書き直すと、下記の３３〜３５式が得られる。ただし、ｘ＝１，２，３である。
【０１１９】
Ｖｏｕｔｘ＝−ｒｐｘ（ｇｍｘ・ｖｇｓｘ＋ｖｄｓｘ／ｒｏｘ） …（３３）
ｖｇｓｘ＝ｖｉｎｘ−ｖｃｏｍ …（３４）
ｖｄｓｘ＝ｖｏｕｔｘ−ｖｃｏｍ …（３５）
上記３３〜３５式から下記の３６式が得られる。
【０１２０】

また、３２式を書き直すと、下記の３７式が得られる。
【０１２１】
ｖｃｏｍ／ｒｓ＝−（ｖｏｕｔ１／ｒｐ１＋ｖｏｕｔ２／ｒｐ２＋ｖｏｕｔ３／ｒｐ３） …（３７）
３６式及び３７式からｖｏｕｔｘに着目して解くと、以下の３８式が得られる。
【０１２２】

従って、下記の３９〜４１式に示す連立方程式が成り立つ。
【０１２３】

ここで、下記の４２〜５０式のように係数を定義して上記３９〜４１式を書き直すと、下記の５１〜５３式に示す連立方程式が得られる。
【０１２４】
ａ１１＝１＋ｒｐ１／ｒｏ１−ｒｓ（ｇｍ１＋１／ｒｏ１） …（４２）
ａ１２＝−ｒｓ（ｒｐ１／ｒｐ２）（ｇｍ１＋１／ｒｏ１） …（４３）
ａ１３＝ｒｓ（ｒｐ１／ｒｐ３）（ｇｍ１＋１／ｒｏ１） …（４４）
ａ２１＝−ｒｓ（ｒｐ２／ｒｐ１）（ｇｍ２＋１／ｒｏ２） …（４５）
ａ２２＝１＋ｒｐ２／ｒｏ２−ｒｓ（ｇｍ１＋２／ｒｏ２） …（４６）
ａ２３＝−ｒｓ（ｒｐ２／ｒｐ３）（ｇｍ２＋１／ｒｏ２） …（４７）
ａ３１＝−ｒｓ（ｒｐ３／ｒｐ１）（ｇｍ３＋１／ｒｏ３） …（４８）
ａ３２＝−ｒｓ（ｒｐ３／ｒｐ２）（ｇｍ３＋１／ｒｏ３） …（４９）
ａ３３＝１＋ｒｐ３／ｒｏ３−ｒｓ（ｇｍ３＋２／ｒｏ３） …（５０）
ａ１１・ｖｏｕｔ１＋ａ１２・ｖｏｕｔ２＋ａ１３・ｖｏｕｔ３＋ｇｍ１・ｒｐ１・ｖｉｎ１＝０ …（５１）
ａ２１・ｖｏｕｔ１＋ａ２２・ｖｏｕｔ２＋ａ２３・ｖｏｕｔ３＋ｇｍ２・ｒｐ２・ｖｉｎ２＝０ …（５２）
ａ３１・ｖｏｕｔ１＋ａ３２・ｖｏｕｔ２＋ａ３３・ｖｏｕｔ３＋ｇｍ３・ｒｐ３・ｖｉｎ３＝０ …（５３）
上記５１〜５３式の連立方程式をｖｏｕｔ１、ｖｏｕｔ２、ｖｏｕｔ３について解くと、下記の５４〜５６式が得られる。
【０１２５】

なお、上記５４〜５６式におけるＤは下記の５７式で与えられる。
【０１２６】

ここで、５４〜５６式及び５７式のｋ１１〜ｋ１３、ｋ２１〜ｋ２３、ｋ３１〜ｋ３３、Ｄに４２〜５０式を代入して整理すると、下記の５８〜６７式が得られる。
【０１２７】

なお、

である。
【０１２８】
つまり、図１５の等価回路で示される３入力の差動段における入出力伝達特性は、５４〜５６式と５８〜６６式及び６７式の係数ｋ１１〜ｋ１３、ｋ２１〜ｋ２３、ｋ３１〜ｋ３３及びＤにより与えられる。
【０１２９】
図１５の等価回路では、係数ｋ１１〜ｋ１３、ｋ２１〜ｋ２３、ｋ３１〜ｋ３３及びＤはそれぞれ正の値をとる。
【０１３０】
これらを書き直すと、下記の６８〜７０式に示される入出力伝達特性が得られる。
【０１３１】
ｖｏｕｔ１＝−｛ｋ１１・ｇｍ１・ｒｐ１・ｖｉｎ１−（ｋ１２・ｇｍ２・ｒｐ２・ｖｉｎ２＋ｋ１３・ｇｍ３・ｒｐ３・ｖｉｎ３）｝／Ｄ …（６８）
ｖｏｕｔ２＝−｛ｋ２２・ｇｍ２・ｒｐ２・ｖｉｎ２−（ｋ２３・ｇｍ３・ｒｐ３・ｖｉｎ３＋ｋ２１・ｇｍ１・ｒｐ１・ｖｉｎ１）｝／Ｄ …（６９）
ｖｏｕｔ３＝−｛ｋ３３・ｇｍ３・ｒｐ３・ｖｉｎ３−（ｋ３１・ｇｍ１・ｒｐ１・ｖｉｎ１＋ｋ３２・ｇｍ２・ｒｐ２・ｖｉｎ２）｝／Ｄ …（７０）
上記６８〜７０式で示される入出力伝達特性により、各出力端子からは対応する入力端子への入力電圧とそれ以外の他の２つの入力端子への入力電圧の重み付け加算電圧との差が出力される。
【０１３２】
ここで、いま、図１４に示す差動段の利得が十分に大きく、ｇｍｘ・ｒｏｘ＞＞１，ｇｍｘ・ｒｓ＞＞１＋ｒｐｘ／ｒｏｘ ［ｘ＝１，２，３］、及びＰチャネルトランジスタＰ１１〜Ｐ１３、ＮチャネルトランジスタＮ１１〜Ｎ１３それぞれのチャネル幅とチャネル長との比率あるいは実効チャネル長（Ｌｅｆｆ）が同一であってｒｐ１／ｒｏ１＝ｒｐ２／ｒｏ２＝ｒｐ３／ｒｏ３が成り立つとき、つまり、ＰチャネルトランジスタとＮチャネルトランジスタのペア特性が、Ｐ１１−Ｎ１１及びＰ１２−Ｎ１２、Ｐ１３−Ｎ１３の各ペアにおいて等しくされているとき、係数Ｄ及びｋ１１〜ｋ１３、ｋ２１〜ｋ２３、ｋ３１〜ｋ３３は下記の７１〜８０式で与えられる。
【０１３３】

【０１３４】
ｖｏｕｔ１＝｛（ｇｍ２・ｖｉｎ２＋ｇｍ３・ｖｉｎ３）／（ｇｍ２＋ｇｍ３）−ｖｉｎ１｝｛ｇｍ１・ｒｐ１（ｇｍ２＋ｇｍ３）｝／｛（１＋ｅ）（ｇｍ１＋ｇｍ２＋ｇｍ３）｝ …（８１）
ｖｏｕｔ２＝｛（ｇｍ３・ｖｉｎ３＋ｇｍ１・ｖｉｎ１）／（ｇｍ３＋ｇｍ１）−ｖｉｎ２｝｛ｇｍ２・ｒｐ２（ｇｍ３＋ｇｍ１）｝／｛（１＋ｅ）（ｇｍ１＋ｇｍ２＋ｇｍ３）｝ …（８２）
ｖｏｕｔ３＝｛（ｇｍ１・ｖｉｎ１＋ｇｍ２・ｖｉｎ２）／（ｇｍ１＋ｇｍ２）−ｖｉｎ３｝｛ｇｍ３・ｒｐ３（ｇｍ１＋ｇｍ２）｝／｛（１＋ｅ）（ｇｍ１＋ｇｍ２＋ｇｍ３）｝ …（８３）
または、
ｖｏｕｔ１＝｛（ｇｍ２（ｖｉｎ２−ｖｉｎ１）＋ｇｍ３（ｖｉｎ３−ｖｉｎ１）｝ｇｍ１・ｒｐ１／｛（１＋ｅ）（ｇｍ１＋ｇｍ２＋ｇｍ３）｝ …（８４）
ｖｏｕｔ２＝｛（ｇｍ３（ｖｉｎ３−ｖｉｎ２）＋ｇｍ１（ｖｉｎ１−ｖｉｎ２）｝ｇｍ２・ｒｐ２／｛（１＋ｅ）（ｇｍ１＋ｇｍ２＋ｇｍ３）｝ …（８５）
ｖｏｕｔ３＝｛（ｇｍ１（ｖｉｎ１−ｖｉｎ３）＋ｇｍ２（ｖｉｎ２−ｖｉｎ３）｝ｇｍ３・ｒｐ３／｛（１＋ｅ）（ｇｍ１＋ｇｍ２＋ｇｍ３）｝ …（８６）
上記８１式より、ｖｏｕｔ１は、ｖｉｎ２とｖｉｎ３の内分点電圧βｖｉｎ２＋（１−β）ｖｉｎ３ ［ただし、β＝ｇｍ２／（ｇｍ２＋ｇｍ３）］とｖｉｎとのを差を増幅したものとなり、増幅率はｇｍ１・ｒｐ１（ｇｍ２＋ｇｍ３）／（ｇｍ１＋ｇｍ２＋ｇｍ３）に比例する。上記８２、８３式より、これと同様のことがｖｏｕｔ２，ｖｏｕｔ３についてもいえる。
【０１３５】
また、上記８４式により、ｖｏｕｔ１は、ｖｉｎ１を基準（ゼロ）としたときのｖｉｎ２とｖｉｎ３の重み付き加算値を増幅したものとなる。この場合の増幅利率はｇｍ１・ｒｐ１に比例する。上記８５、８６式より、これと同様のことがｖｏｕｔ２，ｖｏｕｔ３についてもいえる。
【０１３６】
ここで、図１４中の３個のＮチャネルトランジスタＮ１１〜Ｎ１３の特性が等しくかつ３個のＰチャネルトランジスタＰ１１〜Ｐ１３の特性が等しくされているとき、すなわち、ｇｍ１＝ｇｍ２＝ｇｍ３＝ｇｍ及びｒｐ１＝ｒｐ２＝ｒｐ３＝ｒｐが成り立つとき、Ａ＝（２／３）ｇｍ・ｒｐ／（１＋ｅ）とおくと、上記８１〜８６式は下記の８７〜９２式に書き直すことができる。
【０１３７】
ｖｏｕｔ１＝Ａ｛（ｖｉｎ２＋ｖｉｎ３）／２−ｖｉｎ１｝ …（８７）
ｖｏｕｔ２＝Ａ｛（ｖｉｎ３＋ｖｉｎ１）／２−ｖｉｎ２｝ …（８８）
ｖｏｕｔ３＝Ａ｛（ｖｉｎ１＋ｖｉｎ２）／２−ｖｉｎ３｝ …（８９）
ｖｏｕｔ１＝（Ａ／２）｛（ｖｉｎ２−ｖｉｎ１）＋（ｖｉｎ３−ｖｉｎ１）｝ …（９０）
ｖｏｕｔ２＝（Ａ／２）｛（ｖｉｎ３−ｖｉｎ２）＋（ｖｉｎ１−ｖｉｎ２）｝ …（９１）
ｖｏｕｔ３＝（Ａ／２）｛（ｖｉｎ１−ｖｉｎ３）＋（ｖｉｎ２−ｖｉｎ３）｝ …（９２）
上記８７、９０式により、ｖｏｕｔ１は、ｖｉｎ２とｖｉｎ３の平均値、または同相電圧分とｖｉｎ１との電圧差をＡ倍に増幅したもの、あるいはｖｉｎ１を基準（ゼロ）としたときのｖｉｎ２とｖｉｎ３の相対電圧の平均値、または同相電圧分を増幅したものとなる。また、上記８８、８９式及び９１、９２式により、これと同様のことがｖｏｕｔ２，ｖｏｕｔ３についてもいえる。
【０１３８】
つまり、図１４に示すような構成の３入力の差動段は、３つの入力端子のうちのいずれか１つの入力電圧を固定、あるいはオープンとし、残り２つの入力端子を用いれば、第１乃至第６の実施の形態の場合と同様の２入力の差動段となる。そして、出力段からの帰還の掛け方により多様な応用が可能である。
【０１３９】
第７の実施の形態では、３入力の差動段４１Ａの第３の入力端子に基準電圧が供給されることで第３の入力端子の入力電圧が固定され、第３の出力端子の信号（図１４中のＶｏｕｔ３）が出力段４１Ｂａ及び４１Ｂｂを介して、差動段４１Ａの第１及び第２の入力端子にそれぞれＶｏｕｔａ、Ｖｏｕｔｂとして負帰還される。このため、図１４に示す差動段４１Ａは、先の８７式でｖｏｕｔ３／Ａがゼロとなるように、つまりｖｉｎ３＝（ｖｉｎ１＋ｖｉｎ２）／２となるように制御される。
【０１４０】
この場合には、電源配線３１と接地配線３３に混入される同相ノイズ電圧成分（ΔＶｄｄ＋ΔＶｓｓ）が差動増幅器４１で吸収される。
【０１４１】
この実施の形態でも、電源配線３１と接地配線３３に混入したノイズは、差動増幅器４１で吸収されるので、アナログ回路にはノイズ電流が伝わり難くなる。これにより、デジタル回路が動作することによって発生するスイッチングノイズによるアナログ回路の誤動作が抑制される。
【０１４２】
しかも、差動増幅器４１の帰還ループには容量１７ａ、１７ｂ及び結合容量Ｃ１ａ、Ｃ１ｂが挿入されているだけであり、基板自体が帰還ループに含まれない。このため、ノイズ低減回路の回路設計を容易に行うことができる。
【０１４３】
なお、この第７の実施形態においても、接地配線３３、電源配線３１の代りに信号配線を接続することで、この両信号配線に混入する同相ノイズ電圧を差動増幅器４１で吸収させるように構成してもよい。
【０１４４】
図１６は、図１３の実施形態において、２個の出力段４１Ｂａ、４１Ｂｂを具体化した差動増幅器４１全体の回路構成例を示している。差動段４１Ａにおいて、帰還抵抗Ｒ０、Ｒ１はそれぞれ、Ｐチャネル及びＮチャネルトランジスタのソース・ドレイン間を並列に接続したＣＭＯＳトランスファゲートのオン抵抗が使用される。
【０１４５】
出力段４１Ｂａは１個のチャネルトランジスタＰ１４と３個のＮチャネルトランジスタＮ１５〜Ｎ１７とからなり、出力段４１Ｂｂは１個のチャネルトランジスタＰ１５と３個のＮチャネルトランジスタＮ１８〜Ｎ２０とからなる。
【０１４６】
図１３に示した第７の実施形態では、差動ノイズ電圧成分（ΔＶｄｄ−ΔＶｓｓ）は抑制されない特徴があり、両配線３１、３３相互間は容量結合されていない。このため、同相電圧成分は吸収されても差動電圧成分は抑制されることがない。従って、配線３１、３３を差動信号用の配線対とした場合には、差動信号が抑制されることなく、同相ノイズ成分のみ抑制できるという効果を得ることができる。
【０１４７】
（第８の実施の形態）
図１７は、この発明の第８の実施の形態に係る半導体集積回路の概略的な構成を示す回路図である。なお、この第８の実施形態に係る半導体集積回路の基本的な構成は第７の実施形態のものと同様なので、第７の実施形態と異なる点についてのみ以下に説明する。
【０１４８】
第７の実施形態において、差動増幅器４１は差動段４１Ａと２個の出力段４１Ｂａ、４１Ｂｂとから構成されていた。これに対し、第８の実施の形態では、差動増幅器４１は差動段４１Ａと１個の出力段４１Ｂとから構成され、出力段４１Ｂの出力端子は帰還用の容量１７及び結合容量Ｃ１ａを介して差動段４１Ａの第１の入力端子に接続されている。
【０１４９】
このような構成のノイズ低減回路を備えた半導体集積回路では、配線３１と配線３３に混入した同相ノイズが差動増幅器４１で吸収される。これにより、デジタル回路が動作することによって発生するスイッチングノイズによるアナログ回路の誤動作が抑制される。
【０１５０】
しかも、差動増幅器４１の帰還ループには容量１７及び結合容量Ｃ１ａが挿入されているだけであり、配線３３への負帰還制御は行われない。この結果、配線３３に混入したノイズに応じて配線３１の制御が行われ、両配線３１、３３の同相ノイズが低減される。
【０１５１】
（第９の実施の形態）
図１８は、この発明の第９の実施の形態に係る半導体集積回路の概略的な構成を示す回路図である。この第９の実施形態は、電源電圧Ｖｄｄが伝達される電源配線３１と接地電圧Ｖｓｓが伝達される接地配線３３とに混入する差動ノイズ電圧（ΔＶｄｄ−ΔＶｓｓ）を低減するためにノイズ低減回路を適用したものである。
【０１５２】
すなわち、図１８において、電源配線３１には、外部端子３２を介してＩＣ外部から電源電圧Ｖｄｄが伝達される。接地配線３３には、外部端子３４を介してＩＣ外部から接地電圧Ｖｓｓが伝達される。
【０１５３】
ノイズ低減回路１５は２入力の差動増幅器１６及び帰還用の容量１７等から構成されている。差動増幅器１６は差動段１６Ａとソースフォロワ（ＳＦＷ）型の２個の出力段１６Ｂａ、１６Ｂｂとからなる。
【０１５４】
差動段１６Ａの非反転入力端子（＋）は電源配線３１上の任意のノードに接続されている。差動段１６Ａの非反転入力端子（＋）と反転出力端子（−）との間には自己バイアス用の帰還抵抗Ｒ０が接続されている。差動段１６Ａの反転入力端子（−）は接地配線３３上の任意のノードに接続されている。差動段１６Ａの反転入力端子（−）と非反転出力端子（＋）との間には自己バイアス用の帰還抵抗Ｒ１が接続されている。
【０１５５】
一方の出力段１６Ｂａの入力端子は差動段１６Ａの反転出力端子（−）に接続され、この出力段１６Ｂａの出力端子は帰還用の容量１７ａを介して、電源配線３１上の上記任意のノードに接続されている。他方の出力段１６Ｂｂの入力端子は差動段１６Ａの非反転出力端子（＋）に接続され、この出力段１６Ｂｂの出力端子は帰還用の容量１７ｂを介して、接地配線３３上の上記任意のノードに接続されている。
【０１５６】
このような構成において、デジタル回路が動作することによって電源配線３１及び接地配線３３に混入した差動ノイズ電圧（ΔＶｄｄ−ΔＶｓｓ）が差動増幅器１６で吸収される。
【０１５７】
しかも、差動増幅器１６の帰還ループには容量１７ａ、１７ｂ及び結合容量Ｃ１ａ、Ｃ１ｂが挿入されているだけであり、基板自体が帰還ループに含まれない。このため、ノイズ低減回路の回路設計を容易に行うことができる。
【０１５８】
（第１０の実施の形態）
図１９は、この発明の第１０の実施の形態に係る半導体集積回路の概略的な構成を示す回路図である。この実施の形態は、上記第７及び第８の実施の形態の場合と同様に、ノイズ低減回路内の差動増幅器として３入力のものを用いるようにしたものである。
【０１５９】
この第１０の実施の形態に係る半導体集積回路は、図１４に示す第７の実施の形態のものとは一部の構成が異なるだけなので、第７の実施形態と異なる点についてのみ以下に説明する。
【０１６０】
第７の実施形態では、差動増幅器４１の差動段４１Ａの第３の入力端子が接続されている基準電圧配線３５を、外部端子３６を介して電圧（Ｖｄｄ＋Ｖｓｓ）／２のノードに接続し、差動増幅器４１の２個の反転型の出力段４１Ｂａ、４１Ｂｂの入力端子を共に差動段４１Ａの第３の出力端子に接続する場合を説明した。
【０１６１】
これに対して、第１０の実施の形態では、基準電圧配線３５を、外部端子３６を介してＩＣ外部の基準電圧Ｖｇｎｄ（Ｖｒｅｆ）のノードに接続すると共に、差動増幅器４１の２個の出力段をソースフォロワ型とし、その出力段４１Ｂａ´、４１Ｂｂ´の入力端子を差動段４１Ａの第１及び第２の出力端子に接続している。
【０１６２】
図２０は、図１９中の差動増幅器４１の具体的な回路構成を示している。差動段４１Ａは、図１５及び図１６の場合と同様に、ＰチャネルトランジスタＰ１１〜Ｐ１３、Ｐ１６〜Ｐ１９及びＮチャネルトランジスタＮ１１〜Ｎ１４とから構成されている。
【０１６３】
一方の出力段４１Ｂａ´は、ゲートにバイアス電圧Ｖｐｂ１が供給される負荷としてのＰチャネルトランジスタＰ１６と、ゲートが差動段の第１の出力端子（ＰチャネルトランジスタＰ１１とＮチャネルトランジスタＮ１１の接続ノード）に接続されたＰチャネルトランジスタＰ１７とからなる。他方の出力段４１Ｂｂ´は、ゲートにバイアス電圧Ｖｐｂ１が供給される負荷としてのＰチャネルトランジスタＰ１８と、ゲートが差動段の第２の出力端子（ＰチャネルトランジスタＰ１２とＮチャネルトランジスタＮ１２の接続ノード）に接続されたＰチャネルトランジスタＰ１９とからなる。
【０１６４】
この実施の形態では、電源配線３１及び接地配線３３に混入した差動及び同相ノイズ電圧が差動増幅器４１で吸収される。
【０１６５】
しかも、差動増幅器４１の帰還ループには容量１７ａ、１７ｂ及び結合容量Ｃ１ａ、Ｃ１ｂが挿入されているだけであり、基板自体が帰還ループに含まれない。このため、ノイズ低減回路の回路設計を容易に行うことができる。
【０１６６】
なお、第１ないし第１０の各実施形態においては、接地配線あるいは電源配線の代りに信号配線を接続して、この信号配線に混入するノイズ電圧を差動増幅器で吸収させるように構成してもよい。
【０１６７】
また、この発明は、上記各実施の形態に限定されるものではなく、実施段階ではその要旨を逸脱しない範囲で種々に変形することが可能である。
【０１６８】
さらに、上記実施の形態には種々の段階の発明が含まれており、開示される複数の構成要件における適宜な組み合わせにより種々の発明が抽出され得る。例えば、実施の形態に示される全構成要件から幾つかの構成要件が削除されても、発明が解決しようとする課題の欄で述べた課題が解決でき、発明の効果の欄で述べられている効果が得られる場合には、この構成要件が削除された構成が発明として抽出され得る。
【０１６９】
【発明の効果】
以上説明したようにこの発明によれば、デジタル回路とアナログ回路とが混載された半導体集積回路において、高周波領域のノイズを効果的に低減できると共に、容易に回路設計できるノイズ低減回路を有する半導体集積回路を提供することができる。
【図面の簡単な説明】
【図１】この発明の第１の実施の形態に係る半導体集積回路の概略的な構成を示す回路図。
【図２】第１の実施形態によるノイズ低減回路と従来のデカップリング法とについてノイズ低減効果を試算した結果を示す特性図。
【図３】従来のノイズ低減手法であるデカップリング法によるノイズ低減回路の回路図。
【図４】第１の実施形態によるノイズ低減回路と従来のデカップリング手法と何の対策も施さない場合との３例についてノイズ低減効果をシミュレーションした結果の一例を示す特性図。
【図５】第１の実施形態のノイズ低減回路を実際のＩＣに適用した場合のＩＣチップの概略的な構成を示す回路図。
【図６】図１中のノイズ低減回路で使用される差動増幅器を具体化して示す回路図。
【図７】図６に示す差動増幅器の具体的な回路構成図。
【図８】この発明の第２の実施の形態に係る半導体集積回路の概略的な構成を示す回路図。
【図９】この発明の第３の実施の形態に係る半導体集積回路の概略的な構成を示す回路図。
【図１０】この発明の第４の実施の形態に係る半導体集積回路の概略的な構成を示す回路図。
【図１１】この発明の第５の実施の形態に係る半導体集積回路の概略的な構成を示す回路図。
【図１２】この発明の第６の実施の形態に係る半導体集積回路の概略的な構成を示す回路図。
【図１３】この発明の第７の実施の形態に係る半導体集積回路の概略的な構成を示す回路図。
【図１４】図１３中の差動増幅器の差動段の具体的な回路構成図。
【図１５】図１４に示す差動段の等価回路図。
【図１６】２個の出力段を具体化した図１３中の差動増幅器全体の回路構成図。
【図１７】この発明の第８の実施の形態に係る半導体集積回路の概略的な構成を示す回路図。
【図１８】この発明の第９の実施の形態に係る半導体集積回路の概略的な構成を示す回路図。
【図１９】この発明の第１０の実施の形態に係る半導体集積回路の概略的な構成を示す回路図。
【図２０】図１９中の差動増幅器の具体的な回路構成図。
【符号の説明】
１１…基板、１２ａ、１２ｂ…ウェル領域、１３，１３ａ，１３ｂ…ウェル周囲ガードバンド領域、１４…境界ガードバンド領域、１５，１５ａ，１５ｂ，１５ｃ，１５ｄ…ノイズ低減回路、１６，１６ａ，１６ｂ，４１…差動増幅器、１６Ａ，４１Ａ…差動段、１６Ｂ，４１Ｂａ，４１Ｂｂ，４１Ｂａ´，４１Ｂｂ´…出力段、１７，１７´，１７ａ，１７ｂ…帰還用の容量、１８…接地基準配線、１９…外部端子、２１，２４…ウェルバイアス領域、２２，２５，３１…電源配線、２３，２６，３３…接地配線、３２，３４，３６…外部端子、３５…基準電圧配線。[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit incorporating a noise reduction circuit, and more particularly to a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted on one chip.
[0002]
[Prior art]
As SoC (system on chip) increases in scale and speed, switching noise of CMOS digital circuits increases, and there is a problem of influence on analog circuits in the same chip via an IC substrate. Overcoming such substrate-coupled noise is essential for on-chip analog circuits.
[0003]
In particular, when MOS transistors are miniaturized and speeded up, and noise generated in digital circuits becomes a high-frequency region, the influence of parasitic capacitance and parasitic inductors becomes obvious, and the influence of board coupling noise via the IC board is serious for analog circuits. It will be something.
[0004]
Reducing substrate coupling noise is an important design issue for SoCs equipped with analog circuits, and requires a coupling noise reduction method that is not affected by parasitic impedance even in a high frequency region.
[0005]
Conventionally, in order to prevent substrate coupling noise between digital circuits and analog circuits, separation of power / ground wiring and wells of both circuits, installation of guard bands, decoupling by capacitance, and the like have been used.
[0006]
In the well isolation, when the noise becomes a high frequency region, the parasitic capacitance coupling (jωC) increases and the isolation effect is lost. In addition, the guard band and the capacitive decoupling have a problem that the ground impedance (jωL) increases due to the parasitic inductance of the wiring, so that the effect is lost and it is not useful for reducing the substrate coupling noise.
[0007]
Japanese Patent Application Laid-Open No. H10-228688 discloses a circuit that reduces substrate coupling noise using feedback control of an operational amplifier. More specifically, a substrate coupling noise is detected using an operational amplifier, and a canceling signal that cancels this is supplied to the substrate via a capacitor.
[0008]
However, in the device described in Patent Document 1, since the substrate itself is included in the feedback loop, it is necessary to perform circuit design in consideration of the parasitic parameters of the substrate, which makes it difficult to perform circuit design. There's a problem.
[0009]
[Patent Document 1]
Japanese Patent Laid-Open No. 11-233714
[0010]
[Problems to be solved by the invention]
As described above, conventionally, since the substrate itself is included in the feedback loop, there is a problem that the circuit design of the noise reduction circuit cannot be easily performed.
[0011]
The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to effectively reduce noise in a high frequency region and easily in a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted. Another object of the present invention is to provide a semiconductor integrated circuit having a noise reduction circuit capable of designing a circuit.
[0012]
[Means for Solving the Problems]
A semiconductor integrated circuit according to a first aspect of the present invention is a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted. The semiconductor integrated circuit has first and second input terminals and an output terminal. The first input terminal is the semiconductor integrated circuit. A differential amplifier connected to a predetermined node in the circuit and having a second input terminal connected to a reference potential node, and a capacitor connected between the output terminal and the first input terminal of the differential amplifier The noise reduction circuit which consists of these is comprised.
[0013]
A semiconductor integrated circuit according to a second invention is a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted. The semiconductor integrated circuit has first and second input terminals and an output terminal, and the first input terminal has a reference potential. A differential amplifier connected to the node; a plurality of first capacitors connected between the second input terminal of the differential amplifier and each of the plurality of nodes in the semiconductor integrated circuit; A noise reduction circuit comprising a plurality of second capacitors connected between the output terminal and each of the plurality of nodes in the semiconductor integrated circuit is provided.
[0014]
According to a third aspect of the present invention, there is provided a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted. The semiconductor integrated circuit includes first and second input terminals and an output terminal. The first input terminal is a semiconductor integrated circuit. A differential amplifier in which the second input terminal is connected to the second wiring in the semiconductor integrated circuit, and between the output terminal and the first input terminal of the differential amplifier. And a noise reduction circuit including a capacitor connected to the capacitor.
[0015]
According to a fourth aspect of the present invention, there is provided a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted. The semiconductor integrated circuit has first and second input terminals and an output terminal. The first input terminal is a semiconductor integrated circuit. A first differential amplifier having a second input terminal connected to a node of a reference potential, and an output terminal and a first input terminal of the first differential amplifier. A first capacitor connected in between, and third and fourth input terminals and an output terminal; the third input terminal is connected to a second wiring in the semiconductor integrated circuit; Noise comprising a second differential amplifier whose terminal is connected to the node of the reference potential, and a second capacitor connected between the output terminal and the third input terminal of the second differential amplifier. A reduction circuit is provided.
[0016]
According to a fifth aspect of the present invention, there is provided a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted, a differential amplifier having first and second input terminals and an output terminal; A first capacitor connected between one input terminal and a predetermined node on a first wiring in the semiconductor integrated circuit; a first input terminal of the differential amplifier; and a second capacitor in the semiconductor integrated circuit. A second capacitor connected between the predetermined node on the first wiring and a third capacitor connected between the output terminal of the differential amplifier and the predetermined node on the first wiring. And a fourth capacitor connected between the output terminal of the differential amplifier and the predetermined node on the second wiring, the second input terminal of the differential amplifier being a reference potential A noise reduction circuit connected to the node.
[0017]
A semiconductor integrated circuit according to a sixth aspect of the present invention is a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted, and has first and second input terminals and first and second output terminals having opposite phases. The first input terminal is connected to a predetermined node on the first wiring in the semiconductor integrated circuit, and the second input terminal is connected to a predetermined node on the second wiring in the semiconductor integrated circuit. A differential amplifier; a first capacitor connected between a first output terminal of the differential amplifier and the first input terminal; a second output terminal of the differential amplifier; A noise reduction circuit including a second capacitor connected to the input terminal is provided.
[0018]
According to a seventh aspect of the present invention, there is provided a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted. The first, second and third input terminals and the first, second and third terminals corresponding to the input terminals. A third output terminal, and a weighted addition voltage of the input voltage to the corresponding input terminal from the first, second and third output terminals and the input voltage to the other two input terminals; And a differential stage that outputs the difference between the two, and two output stages that invert and amplify the output of any one of the first, second, and third output terminals of the differential stage. A differential amplifier having one input terminal connected to a predetermined node on a first wiring in the semiconductor integrated circuit and a second input terminal connected to a predetermined node on a second wiring in the semiconductor integrated circuit Between one output terminal of the two output stages and the first input terminal. And a second capacitor connected between the other output terminal of the two output stages and the second input terminal, and a third input of the differential amplifier. A noise reduction circuit having a terminal connected to a reference voltage node is provided.
[0019]
According to an eighth aspect of the present invention, there is provided a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted, and the first, second and third input terminals and the first, second and third terminals corresponding to the respective input terminals. A third output terminal, and a weighted addition voltage of the input voltage to the corresponding input terminal from the first, second and third output terminals and the input voltage to the other two input terminals; Differential stage for outputting the difference between the first output stage and one output stage for amplifying the output of the third output terminal of the differential stage, and the first input terminal on the first wiring in the semiconductor integrated circuit A differential amplifier having a second input terminal connected to a predetermined node on a second wiring in the semiconductor integrated circuit, the output terminal of the output stage, and the first or second A capacitor connected between the input terminal and the third input terminal of the differential stage. It is provided with a noise reduction circuit connected to the node potential.
[0020]
According to a ninth aspect of the present invention, there is provided a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted. The first, second and third input terminals and the first, second and third input terminals corresponding to the input terminals. A third output terminal, and a weighted addition voltage of the input voltage to the corresponding input terminal from the first, second and third output terminals and the input voltage to the other two input terminals; And a first and second output stages for amplifying the outputs of the first and second output terminals of the differential stage, respectively, and the first input terminal is a semiconductor integrated circuit. The second input terminal is connected to a predetermined node on the second wiring in the semiconductor integrated circuit, and the third input terminal is a reference potential node. A differential amplifier connected to the first output stage, an output terminal of the first output stage, and a first input terminal; A first capacitor connected between, and includes a noise reduction circuit comprising a second capacitor connected between the output terminal and the second input terminal of the second output stage.
[0021]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.
[0022]
(First embodiment)
FIG. 1 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit (IC) according to a first embodiment of the present invention.
[0023]
In the surface region of the first conductivity type semiconductor substrate 11, a plurality of second conductivity type well regions 12 different from the substrate 11 are formed. In FIG. 1, two well regions 12a and 12b are illustrated.
[0024]
In one well region 12a, a plurality of first channel type MOS transistors (not shown) are formed. A first conductivity type well region is formed in or near the well region 12a, and a plurality of second channel type MOS transistors are formed in the first conductivity type well region. The plurality of first and second channel type MOS transistors are connected to each other, so that the well region 12a or the well region 12a and the first conductivity type well region provided in the vicinity thereof are disposed in the well region 12a. A CMOS type digital circuit is configured.
[0025]
A plurality of first channel type MOS transistors (not shown) are also formed in the other well region 12b formed apart from the well region 12a. A first conductivity type well region is also formed in or near the well region 12b, and a plurality of second channel type MOS transistors are formed in the first conductivity type well region. The first and second channel type MOS transistors are connected to each other, so that the first conductivity type well region provided in or near the well region 12b or the well region 12b is provided. An analog circuit is configured. That is, a digital circuit and an analog circuit are mixedly mounted on the substrate 11.
[0026]
On the substrate 11 around the one well region 12a, a well surrounding guard band region 13 of the same conductivity type as that of the substrate 11, that is, a first conductivity type is formed so as to surround the well region 12a. The guard band region 13 is usually supplied with a power supply voltage or a ground voltage supplied to the IC, and switching noise generated in the digital circuit formed in the well region 12a is caused to pass through the substrate 11 to the other side. Reaching other circuits including analog circuits formed in the well region 12b is prevented.
[0027]
Further, in order to prevent switching noise generated in the digital circuit from reaching the analog circuit, the substrate 11 between the one and the other well regions 12a and 12b has the same conductivity type as the substrate 11 (first conductivity type). The boundary guard band region 14 is formed.
[0028]
A noise reduction circuit 15 is connected to the boundary guard band region 14. The noise reduction circuit 15 includes a differential amplifier (op-amp) 16 having an inverting input terminal (−), a non-inverting input terminal (+), and an output terminal, and a feedback capacitor 17. The inverting input terminal (−) of the differential amplifier 16 is connected to the boundary guard band region 14, and a feedback capacitor 17 is connected between the output terminal and the inverting input terminal (−). The non-inverting input terminal (+) of the differential amplifier 16 is supplied with the ground reference voltage Vgnd (or Vref) outside the IC via the ground reference wiring 18 and the external terminal 19. Note that the symbols L and R in the figure equivalently indicate the parasitic inductance and the parasitic resistance associated with the path of the ground reference wiring 18 and the external terminal 19, respectively.
[0029]
In such a configuration, the differential amplifier 16 operates so that the DC potentials of the non-inverting input terminal (+) and the inverting input terminal (−) are equal. Since the non-inverting input terminal (+) of the differential amplifier 16 is connected to the ground reference voltage Vgnd outside the IC, the inverting input terminal (−) is virtually grounded. Therefore, the boundary guard band region 14 connected to the inverting input terminal (−) is also virtually grounded.
[0030]
Here, switching noise is generated by the operation of the digital circuit formed in the well region 12a, and thereby, when the noise current is transmitted to the other well region 12b via the substrate 11, it is virtually grounded. The noise current is absorbed by the differential amplifier 16 in the noise reduction circuit 15 through the boundary guard band region 14.
[0031]
At this time, the capacitor 17 connected between the input and output terminals of the differential amplifier 16 serves as a mirror capacitor multiplied by the gain of the differential amplifier 16 and serves to decouple the boundary guard band region 14.
[0032]
In addition, since no current flows through the ground reference wiring 18 when the noise current is absorbed, no noise is generated in the parasitic inductance L in the ground reference wiring 18 and the external terminal 19 and the boundary guard band region 14 is A stable virtual ground is achieved.
[0033]
That is, noise generated in the digital circuit is absorbed by the differential amplifier 16 via the boundary guard band region 14 before reaching the analog circuit, so that it is difficult for noise current to be transmitted to the analog circuit. As a result, malfunction of the analog circuit due to switching noise generated by the operation of the digital circuit is suppressed. Further, if a differential amplifier 16 capable of operating in a wide band is used, noise can be reduced over a high frequency region and is not affected by parasitic inductance.
[0034]
In addition, only the feedback capacitor 17 is inserted in the feedback loop of the differential amplifier 16, and the substrate itself is not included in the feedback loop as in the technique described in Patent Document 1. For this reason, the circuit design of the noise reduction circuit can be easily performed.
[0035]
FIG. 2 is a trial calculation of the noise reduction effect (noise reduction ratio) for the noise reduction circuit according to the first embodiment and the decoupling method using the capacitor C as shown in FIG. 3 which is a conventional noise reduction method. Results are shown. Here, the value of the capacitance C is 2 pF, the value of the parasitic inductance L is 100 nH, the value of the parasitic resistance R is 20Ω, and the coupling capacitance Cn from the noise source is 1 pF.
[0036]
In the case of the noise reduction circuit according to the first embodiment, two examples in which the direct current gain (DC gain) of the differential amplifier 16 is 26 dB and the band fc is 200 MHz and 800 MHz are shown. The noise source level is 0 dB in any case.
[0037]
In FIG. 2, the characteristic A is due to the noise reduction circuit of the first embodiment, and the characteristic B is due to a conventional decoupling technique using a capacitor. As is apparent from FIG. 2, the noise is reduced to some extent even in the case of the conventional decoupling method using the capacitance. However, since a current flows through the parasitic inductance L, noise is generated in the parasitic inductance L in the high frequency region, and the reduction effect is lost. On the other hand, in the noise reduction circuit of the first embodiment, noise is effectively reduced in both the band fc of 200 MHz and 800 MHz.
[0038]
Further, FIG. 4 shows three examples of a noise reduction circuit when the differential amplifier is configured with a CMOS circuit in the first embodiment, a decoupling method using a conventional capacitor, and a case where no measures are taken. Shows an example of the result of simulating the noise reduction effect (noise reduction ratio).
[0039]
In FIG. 4, the characteristic A is a case where no countermeasure is taken, the characteristic B is a case where a conventional decoupling method using a capacitor is used, and the characteristic C is the noise reduction circuit of the first embodiment. According to the case. In the noise reduction circuit according to the first embodiment, the value of the capacitor 17 is 1 pF, and the value of the capacitor C when the decoupling method is used is 500 pF. Also in this case, the noise source level is 0 dB.
[0040]
As is clear from FIG. 4, the noise reduction effect is superior in the case of the noise reduction circuit according to the first embodiment (characteristic C) as compared with the case of using a decoupling method using a capacitor (characteristic B). I understand that.
[0041]
FIG. 5 is a circuit diagram showing a schematic configuration of an IC chip when the noise reduction circuit of the first embodiment is applied to an actual IC. In FIG. 5, portions corresponding to those in FIG.
[0042]
A well bias region 21 for supplying a well potential to the well region 12a is formed in the well region 12a where the digital circuit is formed. A power supply voltage Vdd is applied to the well bias region 21 through a power supply wiring 22. A well surrounding guard band region 13a is formed so as to surround the well region 12a. A ground voltage Vss is applied to the well surrounding guard band region 13 a via the ground wiring 23.
[0043]
In order to make it difficult for switching noise generated in the digital circuit formed in the well region 12a to leak to the outside, a noise reduction circuit 15a is connected to the well surrounding guard band region 13a.
[0044]
A well bias region 24 for supplying a well potential to the well region 12b is formed in the well region 12b in which the analog circuit is formed. A power supply voltage Vdd is applied to the well bias region 24 via a power supply wiring 25 different from the power supply wiring 22. A well surrounding guard band region 13b is formed so as to surround the well region 12b. A ground voltage Vss is applied to the well surrounding guard band region 13 b via a ground wiring 26 different from the ground wiring 23.
[0045]
In order to make it difficult for noise to reach the analog circuit formed in the well region 12b, a noise reduction circuit 15b is connected to the well surrounding guard band region 13b. Further, a noise reduction circuit 15c is connected to the well bias region 24 in order to make it difficult for noise to reach the analog circuit.
[0046]
A boundary guard band region 14 is formed on the substrate between the well regions 12a and 12b so as to separate both well regions. A noise reduction circuit 15 d is connected to the boundary guard band region 14. The noise reduction circuit 15d corresponds to the noise reduction circuit 15 in FIG.
[0047]
Thus, if the noise reduction circuit of this embodiment is connected to a location where it is necessary to absorb noise generated in the chip, noise reaching the analog circuit can be effectively reduced.
[0048]
FIG. 6 is a circuit diagram specifically showing the differential amplifier 16 used in the noise reduction circuit 15 in FIG. The differential amplifier 16 includes a differential stage 16A and a source follower (SFW) type output stage 16B. The differential stage 16A has a non-inverting input terminal (+), an inverting input terminal (−), an inverting output terminal (−), and a non-inverting output terminal (+). A self-bias feedback resistor R0 is connected between the inverting output terminal (−) and the non-inverting input terminal (+), and between the non-inverting output terminal (+) and the inverting input terminal (−). A bias feedback resistor R1 is connected. The input terminal of the output stage 16B is connected to the non-inverting output terminal (+) of the differential stage 16A.
[0049]
A coupling capacitor C0 is inserted between the non-inverting input terminal (+) of the differential stage 16A and the ground reference wiring 18 as necessary. A coupling capacitor C1 is also inserted between the inverting input terminal (−) of the differential stage 16A and the boundary guard band region 14 as necessary. One end of the feedback capacitor 17 is connected to the output terminal of the output stage 16B, and the other end is connected to the inverting input terminal (−) of the differential stage 16A via the coupling capacitor C1.
[0050]
FIG. 7 shows a specific circuit configuration example of the differential amplifier 16 shown in FIG. Both the differential stage 16A and the output stage 16B are CMOS circuits using P-channel and N-channel MOS transistors.
[0051]
The differential stage 16A is composed of P-channel transistors P1, P2 and N-channel transistors N1, N2, N3. The output stage 16B is composed of P-channel transistors P3 and P4.
[0052]
The P-channel transistors P1 and P2 of the differential stage 16A are used as loads, the gates of both transistors P1 and P2 are connected in common, and a constant bias voltage Vbp is supplied to the common gate. N-channel transistors N1 and N2 constitute a differential pair. The gate of one transistor N1 serves as a non-inverting input terminal, and one end of a coupling capacitor C0 is connected to the gate of this transistor N1. The gate of the other transistor N2 constituting the differential pair serves as an inverting input terminal, and one end of the coupling capacitor C1 is connected to the gate of the transistor N2. The transistor N3 whose gate is supplied with a constant bias voltage Vbn is used as a current source. As the coupling capacitors C0 and C1, MOS capacitors using the gate capacitances of P-channel and N-channel MOS transistors are used. Further, as the resistors R0 and R1 in FIG. 6, the on-resistance of a CMOS transfer gate in which the source and drain of the P-channel and N-channel transistors are connected in parallel is used.
[0053]
The output stage 16B is of a source follower (SFW) type, and a transistor P3 whose gate is supplied with a constant bias voltage Vpn serves as a load, and the output from the non-inverting output terminal of the differential stage 16A is applied to the gate of the transistor P4. Supplied. As the feedback capacitor 17, a MOS capacitor using the gate capacitance of an N-channel transistor is used.
[0054]
(Second Embodiment)
FIG. 8 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to the second embodiment of the present invention.
[0055]
In the first embodiment, the case where the output of the noise reduction circuit is supplied to one circuit node, that is, a specific node in the boundary guard band region has been described. In other words, the case where the feedback capacitor 17 and the coupling capacitor C1 are each a single capacitor has been described.
[0056]
On the other hand, in the second embodiment, the feedback capacitor 17 and the coupling capacitor C1 are distributed to a plurality of nodes, and the plurality of nodes in the well bias region, the boundary guard band region, the power supply wiring, the ground wiring, and the like in the substrate 11 are distributed. On the other hand, by distributing and supplying the output of the noise reduction circuit, the noise voltage mixed in the plurality of nodes is absorbed by the noise reduction circuit 15, thereby stabilizing the potential.
[0057]
As shown in the figure, the differential amplifier 16 in the noise reduction circuit 15 includes a differential stage 16A and a source follower (SFW) type output stage 16B. A non-inverting input terminal (+) of the differential stage 16A is connected to a reference voltage Vgnd (Vref) outside the IC via a ground reference wiring 18 and an external terminal 19. One end of each of the plurality of coupling capacitors C1 ′ is connected to the inverting input terminal (−) of the differential stage 16A. The other ends of the plurality of coupling capacitors C1 ′ are respectively connected to a plurality of nodes in the substrate wiring 27 formed in the substrate 11 including a well bias region, a boundary guard band region, a power supply wiring, a ground wiring, and the like. ing.
[0058]
Further, one end of a plurality of feedback capacitors 17 ′ is connected to the output terminal of the output stage 16 </ b> B of the differential amplifier 16. The other ends of the plurality of capacitors 17 ′ are respectively connected to a plurality of nodes in the substrate wiring 27.
[0059]
In the semiconductor integrated circuit having such a configuration, when the switching noise is generated by the operation of the digital circuit and the noise voltage due to the noise is mixed into the in-substrate wiring 27, the noise voltage is the same as in the first embodiment. Is absorbed by the differential amplifier 16 of the noise reduction circuit 15, and the potentials of a plurality of nodes in the in-substrate wiring 27 can be stabilized.
[0060]
Moreover, only the capacitor 17 ′ and the coupling capacitor C1 ′ are inserted in the feedback loop of the differential amplifier 16, and the substrate itself is not included in the feedback loop. For this reason, the circuit design of the noise reduction circuit can be easily performed.
[0061]
(Third embodiment)
FIG. 9 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to the third embodiment of the present invention. In the third embodiment, the noise reduction circuit of the present invention is applied to reduce the noise voltage (ΔVdd) mixed in the power supply wiring to which the power supply voltage Vdd is transmitted.
[0062]
In other words, in FIG. 10, the power supply voltage Vdd is transmitted to the power supply wiring 31 from the outside of the IC through the external terminal 32. A ground voltage Vss is transmitted to the ground wiring 33 from the outside of the IC through the external terminal 34. Here, the power supply wiring 31 is, for example, an n-well bias wiring, and the ground wiring 33 is, for example, a p substrate bias wiring.
[0063]
The noise reduction circuit 15 includes a differential amplifier 16 and a feedback capacitor 17. The differential amplifier 16 includes a differential stage 16A and a source follower (SFW) type output stage 16B.
[0064]
The non-inverting input terminal (+) of the differential stage 16A is connected to an arbitrary node on the ground wiring 33. A self-bias feedback resistor R0 is connected between the non-inverting input terminal (+) and the inverting output terminal (−) of the differential stage 16A. The inverting input terminal (−) of the differential stage 16 </ b> A is connected to an arbitrary node on the power supply wiring 31. A self-bias feedback resistor R1 is connected between the inverting input terminal (−) and the non-inverting output terminal (+) of the differential stage 16A. The input terminal of the output stage 16B is connected to the non-inverting output terminal (+) of the differential stage 16A, and a feedback capacitor is provided between the output terminal of the output stage 16B and the inverting input terminal (−) of the differential stage 16A. 17 is connected. Also in this case, as shown in the figure, coupling between the non-inverting input terminal (+) and the inverting input terminal (−) of the differential stage 16A and the power supply wiring 31 and the ground wiring 33 is performed as necessary. Capacitors C0 and C1 may be inserted.
[0065]
In such a configuration, when the noise voltage ΔVdd due to switching noise generated by the operation of the digital circuit is mixed in the power supply wiring 31, this noise voltage is absorbed by the differential amplifier 16 as in the first embodiment. The As a result, the potential of the power supply wiring 31 can be stabilized. Therefore, there is no possibility that the noise voltage is transmitted to other wiring, for example, the ground wiring 33.
[0066]
On the other hand, when the noise voltage ΔVss is mixed into the ground wiring 33, the potential at the inverting input terminal (−) becomes equal to the potential at the non-inverting input terminal (+) due to the characteristics of the differential amplifier 16 as described above. The potential of the inverting input terminal (−) changes following the potential of the non-inverting input terminal (+). That is, the external noise mixed in the ground wiring 33 is transmitted to the power supply wiring 31 as in-phase noise. As a result, since no potential is generated between the two wirings, the influence on a circuit connected to the two wirings, for example, an analog circuit is mitigated. That is, even if a noise voltage is mixed in the ground wiring 33, malfunction due to this noise can be reduced.
[0067]
(Fourth embodiment)
FIG. 10 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to the fourth embodiment of the present invention. In the fourth embodiment, the noise reduction circuit of the present invention is applied to reduce the noise voltage individually mixed in the power supply wiring to which the power supply voltage Vdd is transmitted and the ground wiring to which the ground voltage Vss is transmitted. It is.
[0068]
In FIG. 10, a power supply voltage Vdd is transmitted to the power supply wiring 31 from the outside of the IC through the external terminal 32. A ground voltage Vss is transmitted to the ground wiring 33 from the outside of the IC through the external terminal 34. Further, the reference voltage Vgnd (Vref) is transmitted to the reference voltage wiring 35 from the outside of the IC through the external terminal 36. Here, the power supply wiring 31 is, for example, an n-well bias wiring, and the ground wiring 33 is, for example, a p substrate bias wiring.
[0069]
The noise reduction circuit 15 includes first and second differential amplifiers 16a and 16b, first and second capacitors 17a and 17b for feedback, and the like. Each of the differential amplifiers 16a and 16b includes a differential stage 16A and a source follower (SFW) type output stage 16B.
[0070]
The non-inverting input terminal (+) of the differential stage 16A in the first differential amplifier 16a is connected to the reference voltage wiring 35. A self-bias feedback resistor R0 is connected between the non-inverting input terminal (+) and the inverting output terminal (−) of the differential stage 16A. The inverting input terminal (−) of the differential stage 16A is connected to an arbitrary node on the power supply wiring 31. A self-bias feedback resistor R1 is connected between the inverting input terminal (−) and the non-inverting output terminal (+) of the differential stage 16A in the first differential amplifier 16a. The input terminal of the output stage 16B in the first differential amplifier 16a is connected to the non-inverting output terminal (+) of the differential stage 16A, and the output terminal of the output stage 16B and the inverting input terminal (−) of the differential stage 16A. A feedback capacitor 17a is connected between the two.
[0071]
The non-inverting input terminal (+) of the differential stage 16A in the second differential amplifier 16b is connected to the reference voltage line 35. A self-bias feedback resistor R0 is connected between the non-inverting input terminal (+) and the inverting output terminal (−) of the differential stage 16A. The inverting input terminal (−) of the differential stage 16A is connected to an arbitrary node on the ground power supply wiring 33. A self-bias feedback resistor R1 is connected between the inverting input terminal (−) and the non-inverting output terminal (+) of the differential stage 16A in the second differential amplifier 16b. The input terminal of the output stage 16B in the second differential amplifier 16b is connected to the non-inverting output terminal (+) of the differential stage 16A, and the output terminal of the output stage 16B and the inverting input terminal (−) of the differential stage 16A. A feedback capacitor 17b is connected between the two.
[0072]
Also in this case, as shown in the drawing, the non-inverting input terminal (+) and the inverting input terminal (−) of each differential stage 16A, the reference voltage wiring 35, the power supply wiring 31, or the ground wiring as required. The coupling capacitors C0 and C1 may be inserted between
[0073]
In such a configuration, when the noise voltage ΔVdd due to switching noise generated by the operation of the digital circuit is mixed in the power supply wiring 31, this noise voltage is absorbed by the first differential amplifier 16a, and thereby the power supply wiring 31. Can be stabilized.
[0074]
On the other hand, when the noise voltage ΔVss is mixed into the ground wiring 33, the noise voltage is absorbed by the second differential amplifier 16 b, thereby stabilizing the potential of the ground wiring 33.
[0075]
In addition, when a noise voltage is mixed in the power supply wiring 31 and the ground wiring 33, no current flows through the reference voltage wiring 35 in any case, so that the noise voltage is generated in the parasitic inductance associated with the reference voltage wiring 35. It is never induced.
[0076]
(Fifth embodiment)
FIG. 11 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to the fifth embodiment of the present invention. In the fifth embodiment, the noise reduction circuit of the present invention is applied to reduce the common-mode noise voltage mixed in the power supply wiring to which the power supply voltage Vdd is transmitted and the ground wiring to which the ground voltage Vss is transmitted. .
[0077]
In FIG. 11, a power supply voltage Vdd is transmitted to the power supply wiring 31 from the outside of the IC through the external terminal 32. A ground voltage Vss is transmitted to the ground wiring 33 from the outside of the IC through the external terminal 34. Further, the reference voltage wiring 35 is connected to an external terminal 36 for reference voltage. The external terminal 36 has a stable reference voltage (Vdd) obtained by dividing the voltage between the power supply voltage Vdd and the ground voltage Vss using two resistors Ri having resistance values equivalent to each other outside the IC. -Vss) / 2 is supplied.
[0078]
The noise reduction circuit 15 includes a differential amplifier 16 and a pair of feedback capacitors 17a and 17b. The differential amplifier 16 includes a differential stage 16A and one output stage 16B.
[0079]
The non-inverting input terminal (+) of the differential stage 16 </ b> A is connected to the reference voltage wiring 35. The inverting input terminal (−) of the differential stage 16A is connected to an arbitrary node on the power supply wiring 31 through the coupling capacitor C1a, and is connected to an arbitrary node on the ground wiring 33 through the coupling capacitor C1b. . A feedback resistor R1 for self-bias is connected between the inverting input terminal (−) and the output terminal of the differential stage 16A.
[0080]
The input terminal of the output stage 16B is connected to the output terminal of the differential stage 16A, and the output terminal of the output stage 16B is connected to the arbitrary node on the power supply wiring 31 through the feedback capacitor 17a and used for feedback. It is connected to the arbitrary node on the ground wiring 33 through a capacitor 17b.
[0081]
In such a configuration, the reference voltage (Vdd−Vss) / 2 is supplied to the non-inverting input terminal (+) of the differential stage 16A of the differential amplifier 16, and the inverting input terminal (− ) Is virtually grounded by this reference voltage. Therefore, the common-mode noise voltage (ΔVdd + ΔVss) mixed in the power supply wiring 31 and the ground wiring 33 is absorbed by the differential amplifier 16.
[0082]
On the other hand, when a differential noise voltage is mixed in the power supply wiring 31 and the ground wiring 33, the current flows through the pair of capacitors 17a and 17b connected in series between the two wirings, and is smoothed and reduced. Is done.
[0083]
In the fifth embodiment, the output terminal of the output stage 16B is connected to an arbitrary node on the power supply wiring 31 via the feedback capacitor 17a and on the ground wiring 33 via the feedback capacitor 17b. In the above description, the common-mode noise voltage mixed in the power supply wiring 31 and the ground wiring 33 is absorbed by the differential amplifier 16 by connecting the power supply wiring 31 and the ground wiring 33. By connecting, the differential amplifier 16 may be configured to absorb the common-mode noise voltage mixed in both the signal wirings.
[0084]
(Sixth embodiment)
FIG. 12 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to the sixth embodiment of the present invention. Since the basic configuration of the semiconductor integrated circuit according to the sixth embodiment is the same as that of the fifth embodiment, only differences from the fifth embodiment will be described below.
[0085]
In the fifth embodiment, the differential amplifier 16 includes a differential stage 16A and one output stage 16B. In contrast, in the sixth embodiment, the differential amplifier 16 includes a differential stage 16A and two source follower (SFW) type output stages 16Ba and 16Bb. The input terminals of the two output stages 16Ba and 16Bb are connected to the same output terminal of the differential stage 16A. The output terminal of one output stage 16Ba is connected to an arbitrary node of the power supply wiring 31 via the feedback capacitor 17a, and the output terminal of the other output stage 16Bb is connected to the ground wiring 33 via the feedback capacitor 17b. Connected to any node.
[0086]
In the CMOS circuit, for example, one capacitor 17a uses a P-channel MOS transistor and the other capacitor 17b uses an N-channel MOS transistor. Composed. In such a case, as in the fifth embodiment shown in FIG. 11, when the output voltage from one output stage 16B is supplied to the pair of capacitors 17a and 17b, a sufficient potential difference is not applied between both ends of the capacitors, Sufficient capacity may not be obtained.
[0087]
Thus, in the sixth embodiment, the output stage 16B of the differential amplifier 16 is used as an output stage 16Ba for driving a capacitor 17a made of a P-channel MOS transistor and an output for driving a capacitor 17b made of an N-channel MOS transistor. Dividing into two stages 16Bb, the drive voltages of the capacitors are made different so that the feedback capacitors 17a and 17b have sufficiently large capacities.
[0088]
In the sixth embodiment, when the noise voltage (ΔVdd) is mixed into the power supply wiring 31 and the noise voltage (ΔVss) is mixed into the ground wiring 33, the differential amplifier 16 has the common-mode voltage (ΔVdd + ΔVss) of the two noise voltages. Negative feedback control works so that becomes zero, and the common-mode voltage component is absorbed. In this case, since the feedback capacitors 17a and 17b are driven by separate output stages 16Ba and 16Bb, it is possible to set drive voltages suitable for, for example, MOS type capacitors formed of P-channel and N-channel transistors. As a result, a large capacitance can be obtained with a small-sized transistor, so that the degree of freedom in design increases and the noise voltage suppression effect is enhanced.
[0089]
It is effective that the one output stage 16Ba is a source follower using an N-channel transistor, and the other output stage 16Bb is a source follower using a P-channel transistor.
[0090]
Also in the sixth embodiment, a signal line is connected instead of the ground line 33 and the power line 31 so that the common-mode noise voltage mixed in both signal lines is absorbed by the differential amplifier 16. May be.
[0091]
(Seventh embodiment)
FIG. 13 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to the seventh embodiment of the present invention. In the first to sixth embodiments, the case where a two-input type differential amplifier in the noise reduction circuit 15 has been described. In contrast, in the seventh embodiment, a three-input differential amplifier is used as the differential amplifier in the noise reduction circuit 15.
[0092]
In FIG. 13, a power supply voltage Vdd is transmitted to the power supply wiring 31 from the outside of the IC through the external terminal 32. A ground voltage Vss is transmitted to the ground wiring 33 from the outside of the IC through the external terminal 34. Further, the reference voltage wiring 35 is connected to the external terminal 36. The external terminal 36 is obtained by dividing the voltage between the power supply voltage Vdd and the ground voltage Vss as the reference voltage using, for example, two resistors Ri having mutually equivalent resistance values outside the IC. A stable reference voltage (Vdd−Vss) / 2 is supplied.
[0093]
The noise reduction circuit 15 includes a three-input differential amplifier 41 and a pair of feedback capacitors 17a and 17b. The differential amplifier 41 includes a differential stage 41A and two inverted output stages 41Ba and 41Bb. Further, the differential stage 41A has first to third input terminals and corresponding first to third output terminals.
[0094]
The first input terminal (non-inverting input terminal (+)) of the differential stage 41A is connected to an arbitrary node on the power supply wiring 31 through the coupling capacitor C1a. The second input terminal (inverted input terminal (−)) of the differential stage 41A is connected to an arbitrary node on the ground wiring 33 via the coupling capacitor C1b. Further, the third input terminal of the differential stage 41A is connected to the reference voltage line 35 via the coupling capacitor C0.
[0095]
A self-bias feedback resistor R1 is connected between the first and second output terminals of the differential stage 41A and the first and second input terminals. Further, a self-bias feedback resistor R0 is connected between the third output terminal and the third input terminal of the differential stage 41A.
[0096]
The input terminals of the two output stages 41Ba and 41Bb are both connected to the third output terminal of the differential stage 41A, and the output terminal of one output stage 41Ba is connected to the above-mentioned power supply line 31 via the feedback capacitor 17a. The output terminal of the other output stage 41Bb is connected to the arbitrary node on the ground wiring 33 via the feedback capacitor 17b.
[0097]
FIG. 14 shows an example of a specific circuit configuration of the differential stage 41A of the differential amplifier 41 in FIG. This circuit is composed of P-channel transistors P11 to P13 and N-channel transistors N11 to N14.
[0098]
P-channel transistors P11 to P13 are used as loads, and the gates of these transistors are connected in common. A constant bias voltage Vbp is supplied to the common gate. N-channel transistors N11 and N12, N12 and N13, and N13 and N11 form a differential pair. The gates of the transistors N11 to N13 are provided with first to third input terminals, and input signals Vin1, Vin2, and Vin3 are input to the first to third input terminals, respectively. The transistor N14 whose gate is supplied with a constant bias voltage Vbn is used as a current source. In addition, a first output terminal is provided at a connection node between the transistors P11 and N11, a second output terminal is provided at a connection node between the transistors P12 and N12, and a third output terminal is provided at a connection node between the transistors P13 and N13. Signals Vout1, Vout2, and Vout3 are output from the first to third output terminals, respectively.
[0099]
Here, the input signals Vin1, Vin2, and Vin3 of the three differential pairs in FIG. 14 are respectively the gate-source voltages Vgs1, Vgs2, and Vgs3 of the N-channel transistors N11, N12, and N13, and the three transistors N11. , N12, N13 and the voltage Vcom at the source common connection node, and is expressed as follows.
[0100]
Vin1 = Vgs1 + Vcom (1)
Vin2 = Vgs2 + Vcom (2)
Vin3 = Vgs3 + Vcom (3)
Consider an equilibrium state in which a sufficiently high resistance (infinite) is connected between the gates and drains of the transistors N11, N12, and N13. When the above equations 1 to 3 are rewritten using the voltage in this equilibrium state, the following equations 4 to 6 are obtained.
[0101]

In equations 4-6,
ΔVin1 = ΔVgs1 + ΔVcom (7)
ΔVin2 = ΔVgs2 + ΔVcom (8)
ΔVin3 = ΔVgs3 + ΔVcom (9)
It is.
[0102]
That is, each input voltage can be expressed by a DC component Vinx0 (x = 1, 2, 3) and a fluctuation component (small signal AC component) ΔVinx (x = 1, 2, 3) in an equilibrium state.
[0103]
At this time, the drain currents Id1, Id2, and Id3 of the transistors N11, N12, and N13 can also be expressed as DC current values Id10, Id20, and Id20 in an equilibrium state and small signal AC components ΔId1, ΔId2, and ΔId3.
[0104]
That is, the following formulas 10 to 12 are established.
[0105]
Id1 = Id10 + ΔId1 (10)
Id2 = Id20 + ΔId2 (11)
Id3 = Id30 + ΔId3 (12)
The tail current, that is, the current Iss flowing through the current source transistor N14 is equal to the sum of the drain currents of the transistors N11, N12, and N13 (Id1 + Id2 + Id3). The following 13 equations are obtained.
[0106]

In addition,
Iss0 = Id10 + Id20 + Id30 (14)
ΔIss = ΔId1 + ΔId2 + ΔId3 (15)
It is.
[0107]
Here, the relationship between the drain current and the gate voltage of each transistor when the transistors N11, N12, and N13 all operate in the saturation region is obtained. From the basic equation of the MOS transistor, each drain current is given by the following equations 16-18.
[0108]
Id1 = (μCox / 2) (W1 / L1) (Vgs1-Vth) ² (1 + λVds1) (16)
Id2 = (μCox / 2) (W2 / L2) (Vgs2-Vth) ² (1 + λVds2) (17)
Id3 = (μCox / 2) (W3 / L3) (Vgs3-Vth) ² (1 + λVds3) (18)
In Equations 16 to 18, μ is the carrier mobility, Cox is the dielectric constant of the gate insulating film, Wx (x = 1, 2, 3) is the channel width of each transistor, and Lx (x = 1, 2, 3). ) Is the channel length of each transistor, and Vth is the threshold voltage.
[0109]
here,
ΔIdx = Idx−Idx0 = (∂Idx / ∂Vgsx) ΔVgsx + (∂Idx / ∂Vdsx) ΔVdsx [x = 1, 2, 3] (19)
Is used to obtain the small signal drain currents ΔId1, ΔId2, and ΔId3, the following equations 20 to 22 are obtained.
[0110]
ΔId1 = Id1−Id10 = gm1ΔVgs1 + (1 / ro1) ΔVds1 (20)
ΔId2 = Id2−Id20 = gm2ΔVgs2 + (1 / ro2) ΔVds2 (21)
ΔId3 = Id3−Id30 = gm3ΔVgs3 + (1 / ro3) ΔVds3 (22)
However, gmx [= ∂Idx / ∂Vgsx] is a mutual conductance of each transistor, and rox [(= ∂Idx / ∂Vdsx) ^-1 ] Is the output resistance of each transistor, and gmx (x = 1, 2, 3) is expressed by the following equations 23-25.
[0111]
gm1≈μCox (W1 / L1) (Vgs10−Vth) (1 + λVds10) ≈ {2μCox (W1 / L1) Id10} ^1/2 ... (23)
gm2≈μCox (W2 / L2) (Vgs20−Vth) (1 + λVds20) ≈ {2μCox (W2 / L2) Id20} ^1/2 ... (24)
gm3≈μCox (W3 / L3) (Vgs30−Vth) (1 + λVds30) ≈ {2μCox (W3 / L3) Id30} ^1/2 ... (25)
here,
1 / ro1≈λ (μCox / 2) (W1 / L1) (Vgs10−Vth) ² ≈λId10 (26)
1 / ro2≈λ (μCox / 2) (W2 / L2) (Vgs20−Vth) ² ≈λId20 (27)
1 / ro3≈λ (μCox / 2) (W3 / L3) (Vgs30−Vth) ² ≈λId30 (28)
It is represented by
[0112]
Next, a small signal voltage component generated at the output terminals (Vout1, Vout2, Vout3) of the transistors N11, N12, and N13 is obtained from the small signal drain current. A constant gate bias voltage Vbp is applied to the P-channel transistors P11, P12, and P13 serving as loads of the transistors N11, N12, and N13, and equivalently represented by resistors rp1, rp2, and rp3 for small signals, respectively. be able to. Since the small signal voltages ΔVout1, ΔVout2, and ΔVout3 at the output terminal are expressed by voltage drops of these equivalent resistances rp1, rp2, and rp3, the following equations 29 to 31 are established.
[0113]
ΔVout1 = −rp1ΔId1 = −rp1 {gm1ΔVgs1 + (1 / ro1) ΔVds1} (29)
ΔVout2 = −rp2ΔId2 = −rp2 {gm2ΔVgs2 + (1 / ro2) ΔVds2} (30)
ΔVout3 = −rp3ΔId3 = −rp3 {gm3ΔVgs3 + (1 / ro3) ΔVds3} (31)
A constant gate bias voltage Vbn is applied to the N-channel transistor N14 which is a current source, and can be equivalently represented by a resistance rs when attention is paid to a small signal. The tail current Iss is equal to the sum of the currents flowing through the load resistors rp1, rp2, and rp3, and the following 32 equations are established for the small signal current ΔIss.
[0114]

As described above, an equivalent circuit of a small signal voltage and a current component can be expressed.
[0115]
In other words, the three-input differential stage shown in FIG. 14 is based on the above 7-9 formula, 14 formula, 15 formula, 20-22 formula, 29-31 formula, 32 formula, and the small signal equivalent as shown in FIG. It can be represented by a circuit.
[0116]
The input / output transfer characteristics are obtained from the equivalent circuit of FIG.
[0117]
Here, voltage fluctuations ΔVin, ΔVout, ΔVgs, and ΔVcom are represented by vin, vout, vgs, and vcom, respectively.
[0118]
Rewriting the above 29-31 and 10-12 respectively yields the following 33-35. However, x = 1, 2, 3.
[0119]
Voutx = −rpx (gmx · vgsx + vdsx / rox) (33)
vgsx = vinx−vcom (34)
vdsx = voutx−vcom (35)
The following 36 formulas are obtained from the above 33-35 formulas.
[0120]

Further, when the equation 32 is rewritten, the following equation 37 is obtained.
[0121]
vcom / rs = − (vout1 / rp1 + vout2 / rp2 + vout3 / rp3) (37)
The following 38 equations can be obtained by solving the equations 36 and 37 by paying attention to voutx.
[0122]

Therefore, the simultaneous equations shown in the following equations 39 to 41 are established.
[0123]

Here, when the coefficients are defined as in the following equations 42 to 50 and the above equations 39 to 41 are rewritten, the simultaneous equations shown in the following equations 51 to 53 are obtained.
[0124]
a11 = 1 + rp1 / ro1-rs (gm1 + 1 / ro1) (42)
a12 = −rs (rp1 / rp2) (gm1 + 1 / ro1) (43)
a13 = rs (rp1 / rp3) (gm1 + 1 / ro1) (44)
a21 = −rs (rp2 / rp1) (gm2 + 1 / ro2) (45)
a22 = 1 + rp2 / ro2-rs (gm1 + 2 / ro2) (46)
a23 = −rs (rp2 / rp3) (gm2 + 1 / ro2) (47)
a31 = −rs (rp3 / rp1) (gm3 + 1 / ro3) (48)
a32 = −rs (rp3 / rp2) (gm3 + 1 / ro3) (49)
a33 = 1 + rp3 / ro3-rs (gm3 + 2 / ro3) (50)
a11 · vout1 + a12 · vout2 + a13 · vout3 + gm1 · rp1 · vin1 = 0 (51)
a21 · vout1 + a22 · vout2 + a23 · vout3 + gm2 · rp2 · vin2 = 0 (52)
a31 * vout1 + a32 * vout2 + a33 * vout3 + gm3 * rp3 * vin3 = 0 (53)
The following equations 54 to 56 are obtained by solving the simultaneous equations of equations 51 to 53 for vout1, vout2, and vout3.
[0125]

In the above equations 54 to 56, D is given by the following equation 57.
[0126]

Here, the following equations 58 to 67 are obtained by substituting equations 42 to 50 for k11 to k13, k21 to k23, k31 to k33, and D in equations 54 to 56 and 57.
[0127]

In addition,

It is.
[0128]
That is, the input / output transfer characteristics in the 3-input differential stage shown in the equivalent circuit of FIG. 15 are the coefficients k11 to k13, k21 to k23, k31 to k33, and D Given by.
[0129]
In the equivalent circuit of FIG. 15, the coefficients k11 to k13, k21 to k23, k31 to k33, and D each take a positive value.
[0130]
When these are rewritten, the input / output transfer characteristics shown in the following equations 68 to 70 are obtained.
[0131]
vout1 = − {k11 · gm1 · rp1 · vin1− (k12 · gm2 · rp2 · vin2 ++ k13 · gm3 · rp3 · vin3)} / D (68)
vout2 = − {k22 · gm2 · rp2 · vin2− (k23 · gm3 · rp3 · vin3 + k21 · gm1 · rp1 · vin1)} / D (69)
vout3 = − {k33 · gm3 · rp3 · vin3− (k31 · gm1 · rp1 · vin1 + k32 · gm2 · rp2 · vin2)} / D (70)
Due to the input / output transfer characteristics shown by the above equations 68 to 70, the difference between the input voltage to the corresponding input terminal and the weighted addition voltage of the input voltages to the other two input terminals is output from each output terminal. Is done.
[0132]
Here, the gain of the differential stage shown in FIG. 14 is sufficiently large, gmx · rox >> 1, gmx · rs >> 1 + rpx / rox [x = 1, 2, 3], and P-channel transistors P11 to P11- When the ratio of the channel width to the channel length or the effective channel length (Leff) of each of P13 and N-channel transistors N11 to N13 is the same and rp1 / ro1 = rp2 / ro2 = rp3 / ro3 holds, that is, the P-channel transistor And the pair characteristics of the N-channel transistors are equal in each of the pairs P11-N11, P12-N12, and P13-N13, the coefficients D and k11 to k13, k21 to k23, and k31 to k33 are the following 71 to 80: It is given by the formula.
[0133]

[0134]
vout1 = {(gm2 · vin2 + gm3 · vin3) / (gm2 + gm3) −vin1} {gm1 · rp1 (gm2 + gm3)} / {(1 + e) (gm1 + gm2 + gm3)} (81)
vout2 = {(gm3 · vin3 + gm1 · vin1) / (gm3 + gm1) −vin2} {gm2 · rp2 (gm3 + gm1)} / {(1 + e) (gm1 + gm2 + gm3)} (82)
vout3 = {(gm1 · vin1 + gm2 · vin2) / (gm1 + gm2) −vin3} {gm3 · rp3 (gm1 + gm2)} / {(1 + e) (gm1 + gm2 + gm3)} (83)
Or
vout1 = {(gm2 (vin2-vin1) + gm3 (vin3-vin1)} gm1.rp1 / {(1 + e) (gm1 + gm2 + gm3)} (84)
vout2 = {(gm3 (vin3−vin2) + gm1 (vin1−vin2)} gm2 · rp2 / {(1 + e) (gm1 + gm2 + gm3)} (85)
vout3 = {(gm1 (vin1-vin3) + gm2 (vin2-vin3)} gm3 · rp3 / {(1 + e) (gm1 + gm2 + gm3)} (86)
From the above equation 81, vout1 is obtained by amplifying the difference between the internal divided voltage βvin2 + (1-β) vin3 [where β = gm2 / (gm2 + gm3)] and vin of vin2 and vin3, and the amplification factor is gm1 -Proportional to rp1 (gm2 + gm3) / (gm1 + gm2 + gm3). From the above equations 82 and 83, the same can be said for vout2 and vout3.
[0135]
Further, according to the above equation 84, vout1 is obtained by amplifying the weighted addition value of vin2 and vin3 when vin1 is used as a reference (zero). The amplification rate in this case is proportional to gm1 · rp1. From the above formulas 85 and 86, the same can be said for vout2 and vout3.
[0136]
Here, when the characteristics of the three N-channel transistors N11 to N13 in FIG. 14 are equal and the characteristics of the three P-channel transistors P11 to P13 are equal, that is, gm1 = gm2 = gm3 = gm and rp1 When = rp2 = rp3 = rp holds, if A = (2/3) gm · rp / (1 + e), then the above 81-86 equations can be rewritten into the following 87-92 equations.
[0137]
vout1 = A {(vin2 + vin3) / 2−vin1} (87)
vout2 = A {(vin3 + vin1) / 2−vin2} (88)
vout3 = A {(vin1 + vin2) / 2−vin3} (89)
vout1 = (A / 2) {(vin2-vin1) + (vin3-vin1)} (90)
vout2 = (A / 2) {(vin3-vin2) + (vin1-vin2)} (91)
vout3 = (A / 2) {(vin1-vin3) + (vin2-vin3)} (92)
According to the above equations 87 and 90, vout1 is the average value of vin2 and vin3, or the voltage difference between the in-phase voltage and vin1, amplified by A times, or vin2 and vin3 when vin1 is used as a reference (zero) It is the average value of the relative voltage or the amplified common-mode voltage. The same can be said for vout2 and vout3 according to the above-mentioned formulas 88 and 89 and formulas 91 and 92.
[0138]
That is, in the three-input differential stage configured as shown in FIG. 14, if any one of the three input terminals is fixed or open and the remaining two input terminals are used, the first to first stages This is a two-input differential stage similar to that of the sixth embodiment. Various applications are possible depending on how feedback is applied from the output stage.
[0139]
In the seventh embodiment, the reference voltage is supplied to the third input terminal of the three-input differential stage 41A, so that the input voltage at the third input terminal is fixed, and the signal at the third output terminal ( Vout3) in FIG. 14 is negatively fed back as Vouta and Voutb to the first and second input terminals of the differential stage 41A via the output stages 41Ba and 41Bb, respectively. For this reason, the differential stage 41A shown in FIG. 14 is controlled so that vout3 / A becomes zero in Equation 87 above, that is, vin3 = (vin1 + vin2) / 2.
[0140]
In this case, the common-mode noise voltage component (ΔVdd + ΔVss) mixed in the power supply wiring 31 and the ground wiring 33 is absorbed by the differential amplifier 41.
[0141]
Also in this embodiment, noise mixed in the power supply wiring 31 and the ground wiring 33 is absorbed by the differential amplifier 41, so that it is difficult for noise current to be transmitted to the analog circuit. As a result, malfunction of the analog circuit due to switching noise generated by the operation of the digital circuit is suppressed.
[0142]
In addition, the capacitors 17a and 17b and the coupling capacitors C1a and C1b are only inserted in the feedback loop of the differential amplifier 41, and the substrate itself is not included in the feedback loop. For this reason, the circuit design of the noise reduction circuit can be easily performed.
[0143]
In the seventh embodiment, signal wiring is connected instead of the ground wiring 33 and the power supply wiring 31 so that the common-mode noise voltage mixed in both signal wirings is absorbed by the differential amplifier 41. May be.
[0144]
FIG. 16 shows a circuit configuration example of the entire differential amplifier 41 in which the two output stages 41Ba and 41Bb are embodied in the embodiment of FIG. In the differential stage 41A, the feedback resistors R0 and R1 are respectively the on-resistances of CMOS transfer gates in which the sources and drains of the P-channel and N-channel transistors are connected in parallel.
[0145]
The output stage 41Ba is composed of one channel transistor P14 and three N channel transistors N15 to N17, and the output stage 41Bb is composed of one channel transistor P15 and three N channel transistors N18 to N20.
[0146]
The seventh embodiment shown in FIG. 13 is characterized in that the differential noise voltage component (ΔVdd−ΔVss) is not suppressed, and the wirings 31 and 33 are not capacitively coupled. For this reason, even if the common-mode voltage component is absorbed, the differential voltage component is not suppressed. Therefore, when the wirings 31 and 33 are differential signal wiring pairs, it is possible to obtain an effect that only the common-mode noise component can be suppressed without suppressing the differential signal.
[0147]
(Eighth embodiment)
FIG. 17 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to the eighth embodiment of the present invention. Note that the basic configuration of the semiconductor integrated circuit according to the eighth embodiment is the same as that of the seventh embodiment, and therefore only differences from the seventh embodiment will be described below.
[0148]
In the seventh embodiment, the differential amplifier 41 is composed of a differential stage 41A and two output stages 41Ba and 41Bb. On the other hand, in the eighth embodiment, the differential amplifier 41 includes a differential stage 41A and one output stage 41B, and the output terminal of the output stage 41B includes a feedback capacitor 17 and a coupling capacitor C1a. To the first input terminal of the differential stage 41A.
[0149]
In the semiconductor integrated circuit including the noise reduction circuit having such a configuration, the common-mode noise mixed in the wiring 31 and the wiring 33 is absorbed by the differential amplifier 41. As a result, malfunction of the analog circuit due to switching noise generated by the operation of the digital circuit is suppressed.
[0150]
Moreover, only the capacitor 17 and the coupling capacitor C1a are inserted in the feedback loop of the differential amplifier 41, and negative feedback control to the wiring 33 is not performed. As a result, the wiring 31 is controlled according to the noise mixed in the wiring 33, and the common-mode noise of both the wirings 31 and 33 is reduced.
[0151]
(Ninth embodiment)
FIG. 18 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to the ninth embodiment of the present invention. The ninth embodiment is a noise reduction circuit for reducing the differential noise voltage (ΔVdd−ΔVss) mixed in the power supply wiring 31 to which the power supply voltage Vdd is transmitted and the ground wiring 33 to which the ground voltage Vss is transmitted. Is applied.
[0152]
That is, in FIG. 18, the power supply voltage Vdd is transmitted to the power supply wiring 31 from the outside of the IC through the external terminal 32. A ground voltage Vss is transmitted to the ground wiring 33 from the outside of the IC through the external terminal 34.
[0153]
The noise reduction circuit 15 includes a two-input differential amplifier 16 and a feedback capacitor 17. The differential amplifier 16 includes a differential stage 16A and two source follower (SFW) type output stages 16Ba and 16Bb.
[0154]
The non-inverting input terminal (+) of the differential stage 16A is connected to an arbitrary node on the power supply wiring 31. A self-bias feedback resistor R0 is connected between the non-inverting input terminal (+) and the inverting output terminal (−) of the differential stage 16A. The inverting input terminal (−) of the differential stage 16 </ b> A is connected to an arbitrary node on the ground wiring 33. A self-bias feedback resistor R1 is connected between the inverting input terminal (−) and the non-inverting output terminal (+) of the differential stage 16A.
[0155]
The input terminal of one output stage 16Ba is connected to the inverting output terminal (−) of the differential stage 16A, and the output terminal of this output stage 16Ba is connected to the arbitrary node on the power supply wiring 31 via the feedback capacitor 17a. It is connected to the. The input terminal of the other output stage 16Bb is connected to the non-inverted output terminal (+) of the differential stage 16A. Connected to the node.
[0156]
In such a configuration, when the digital circuit operates, the differential noise voltage (ΔVdd−ΔVss) mixed in the power supply wiring 31 and the ground wiring 33 is absorbed by the differential amplifier 16.
[0157]
In addition, the capacitors 17a and 17b and the coupling capacitors C1a and C1b are only inserted in the feedback loop of the differential amplifier 16, and the substrate itself is not included in the feedback loop. For this reason, the circuit design of the noise reduction circuit can be easily performed.
[0158]
(Tenth embodiment)
FIG. 19 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to the tenth embodiment of the present invention. In this embodiment, as in the case of the seventh and eighth embodiments, a three-input differential amplifier is used in the noise reduction circuit.
[0159]
The semiconductor integrated circuit according to the tenth embodiment is only partially different from that of the seventh embodiment shown in FIG. 14, and therefore only the differences from the seventh embodiment will be described below. To do.
[0160]
In the seventh embodiment, the reference voltage wiring 35 to which the third input terminal of the differential stage 41A of the differential amplifier 41 is connected is connected to the node of voltage (Vdd + Vss) / 2 via the external terminal 36. In the above description, the input terminals of the two inverting output stages 41Ba and 41Bb of the differential amplifier 41 are both connected to the third output terminal of the differential stage 41A.
[0161]
On the other hand, in the tenth embodiment, the reference voltage wiring 35 is connected to the node of the reference voltage Vgnd (Vref) outside the IC via the external terminal 36 and the two outputs of the differential amplifier 41 are connected. The stage is a source follower type, and the input terminals of the output stages 41Ba ′ and 41Bb ′ are connected to the first and second output terminals of the differential stage 41A.
[0162]
FIG. 20 shows a specific circuit configuration of the differential amplifier 41 in FIG. The differential stage 41A includes P-channel transistors P11 to P13, P16 to P19, and N-channel transistors N11 to N14, as in the case of FIGS.
[0163]
One output stage 41Ba ′ includes a P-channel transistor P16 as a load whose gate is supplied with a bias voltage Vpb1, and a first output terminal (a connection node between the P-channel transistor P11 and the N-channel transistor N11) whose gate is a differential stage. ) Connected to the P channel transistor P17. The other output stage 41Bb ′ includes a P channel transistor P18 as a load whose gate is supplied with a bias voltage Vpb1, and a second output terminal whose gate is a differential stage (a connection node between the P channel transistor P12 and the N channel transistor N12). ) Connected to the P channel transistor P19.
[0164]
In this embodiment, differential and common-mode noise voltages mixed in the power supply wiring 31 and the ground wiring 33 are absorbed by the differential amplifier 41.
[0165]
In addition, the capacitors 17a and 17b and the coupling capacitors C1a and C1b are only inserted in the feedback loop of the differential amplifier 41, and the substrate itself is not included in the feedback loop. For this reason, the circuit design of the noise reduction circuit can be easily performed.
[0166]
In each of the first to tenth embodiments, a signal wiring may be connected instead of the ground wiring or the power supply wiring, and the noise voltage mixed in the signal wiring may be absorbed by the differential amplifier. Good.
[0167]
The present invention is not limited to the above-described embodiments, and various modifications can be made without departing from the scope of the invention when it is practiced.
[0168]
Further, the above embodiments include inventions at various stages, and various inventions can be extracted by appropriately combining a plurality of disclosed constituent elements. For example, even if some constituent elements are deleted from all the constituent elements shown in the embodiment, the problem described in the column of the problem to be solved by the invention can be solved, and is described in the column of the effect of the invention. When an effect is obtained, a configuration in which this configuration requirement is deleted can be extracted as an invention.
[0169]
【The invention's effect】
As described above, according to the present invention, in a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted, a semiconductor integrated circuit having a noise reduction circuit capable of effectively reducing noise in a high frequency region and easily designing a circuit. A circuit can be provided.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to a first embodiment of the invention.
FIG. 2 is a characteristic diagram showing a result of trial calculation of noise reduction effect for the noise reduction circuit according to the first embodiment and the conventional decoupling method.
FIG. 3 is a circuit diagram of a noise reduction circuit by a decoupling method which is a conventional noise reduction method.
FIG. 4 is a characteristic diagram showing an example of a result of simulating a noise reduction effect for three examples of the noise reduction circuit according to the first embodiment, the conventional decoupling technique, and a case where no measures are taken.
FIG. 5 is a circuit diagram showing a schematic configuration of an IC chip when the noise reduction circuit of the first embodiment is applied to an actual IC.
6 is a circuit diagram specifically showing a differential amplifier used in the noise reduction circuit in FIG. 1. FIG.
7 is a specific circuit configuration diagram of the differential amplifier shown in FIG. 6;
FIG. 8 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to a second embodiment of the present invention.
FIG. 9 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to a third embodiment of the present invention.
FIG. 10 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to a fourth embodiment of the invention.
FIG. 11 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to a fifth embodiment of the present invention.
FIG. 12 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to a sixth embodiment of the present invention.
FIG. 13 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to a seventh embodiment of the invention.
14 is a specific circuit configuration diagram of a differential stage of the differential amplifier in FIG. 13;
15 is an equivalent circuit diagram of the differential stage shown in FIG. 14;
16 is a circuit configuration diagram of the entire differential amplifier in FIG. 13 in which two output stages are embodied.
FIG. 17 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to an eighth embodiment of the present invention.
FIG. 18 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to a ninth embodiment of the invention.
FIG. 19 is a circuit diagram showing a schematic configuration of a semiconductor integrated circuit according to a tenth embodiment of the invention.
20 is a specific circuit configuration diagram of the differential amplifier in FIG. 19;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 11 ... Board | substrate, 12a, 12b ... Well area | region, 13, 13a, 13b ... Well surrounding guard band area | region, 14 ... Boundary guard band area | region, 15, 15a, 15b, 15c, 15d ... Noise reduction circuit 16, 16a, 16b, 41 ... Differential amplifier, 16A, 41A ... Differential stage, 16B, 41Ba, 41Bb, 41Ba ', 41Bb' ... Output stage, 17, 17 ', 17a, 17b ... Feedback capacitor, 18 ... Ground reference wiring, 19 ... external terminals, 21, 24 ... well bias regions, 22, 25, 31 ... power supply wiring, 23, 26, 33 ... ground wiring, 32, 34, 36 ... external terminals, 35 ... reference voltage wiring.

Claims (13)

In a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted,
A difference between first and second input terminals and an output terminal, wherein the first input terminal is connected to a predetermined node in the semiconductor integrated circuit and the second input terminal is connected to a node of a reference potential; A dynamic amplifier;
A semiconductor integrated circuit comprising a noise reduction circuit comprising a capacitor connected between an output terminal and a first input terminal of the differential amplifier. In a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted,
A differential amplifier having first and second input terminals and an output terminal, wherein the first input terminal is connected to a node of a reference potential;
A plurality of first capacitors connected between a second input terminal of the differential amplifier and a plurality of nodes in the semiconductor integrated circuit;
A semiconductor integrated circuit comprising a noise reduction circuit comprising a plurality of second capacitors connected between an output terminal of the differential amplifier and each of the plurality of nodes in the semiconductor integrated circuit. In a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted,
The first input terminal has an output terminal, the first input terminal is connected to a first wiring in the semiconductor integrated circuit, and the second input terminal is a second wiring in the semiconductor integrated circuit. A differential amplifier connected to
A semiconductor integrated circuit comprising a noise reduction circuit comprising a capacitor connected between an output terminal and a first input terminal of the differential amplifier. In a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted,
A first input terminal connected to a first wiring in the semiconductor integrated circuit, and a second input terminal connected to a reference potential node; 1 differential amplifier;
A first capacitor connected between an output terminal and a first input terminal of the first differential amplifier;
A third input terminal connected to a second wiring in the semiconductor integrated circuit; and a fourth input terminal connected to the reference potential node. A second differential amplifier;
A semiconductor integrated circuit comprising a noise reduction circuit comprising a second capacitor connected between an output terminal and a third input terminal of the second differential amplifier. In a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted,
A differential amplifier having first and second input terminals and an output terminal;
A first capacitor connected between the first input terminal of the differential amplifier and a predetermined node on the first wiring in the semiconductor integrated circuit;
A second capacitor connected between the first input terminal of the differential amplifier and a predetermined node on the second wiring in the semiconductor integrated circuit;
A third capacitor connected between the output terminal of the differential amplifier and the predetermined node on the first wiring;
A fourth capacitor connected between the output terminal of the differential amplifier and the predetermined node on the second wiring;
A semiconductor integrated circuit comprising a noise reduction circuit in which a second input terminal of the differential amplifier is connected to a node of a reference voltage. 6. The semiconductor integrated circuit according to claim 5, wherein the node of the reference voltage is a node of a voltage intermediate between two voltages transmitted through the first and second wirings. In a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted,
The first and second input terminals and the first and second output terminals having opposite phases to each other, and the first input terminal is connected to a predetermined node on the first wiring in the semiconductor integrated circuit A differential amplifier having a second input terminal connected to a predetermined node on the second wiring in the semiconductor integrated circuit;
A first capacitor connected between the first output terminal of the differential amplifier and the first input terminal;
A semiconductor integrated circuit comprising a noise reduction circuit comprising a second capacitor connected between a second output terminal of the differential amplifier and the second input terminal. In a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted,
The first, second, and third input terminals and the first, second, and third output terminals corresponding to the input terminals, and the first, second, and third output terminals correspond to the first, second, and third output terminals. A differential stage for outputting a difference between an input voltage to the input terminal and a weighted addition voltage of the input voltages to the other two input terminals, and first, second and third outputs of the differential stage Two output stages for inverting and amplifying the output of any one of the output terminals, the first input terminal being connected to a predetermined node on the first wiring in the semiconductor integrated circuit, A differential amplifier having an input terminal connected to a predetermined node on a second wiring in the semiconductor integrated circuit;
A first capacitor connected between one output terminal of the two output stages and the first input terminal;
A second capacitor connected between the other output terminal of the two output stages and the second input terminal;
A semiconductor integrated circuit comprising a noise reduction circuit in which a third input terminal of the differential stage is connected to a node of a reference voltage. 9. The semiconductor integrated circuit according to claim 8, wherein the node of the reference voltage is a node of a voltage intermediate between two voltages transmitted through the first and second wirings. In a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted,
The first, second, and third input terminals and the first, second, and third output terminals corresponding to the input terminals, and the first, second, and third output terminals correspond to the first, second, and third output terminals. A differential stage that outputs the difference between the input voltage to the input terminal and the weighted addition voltage of the input voltages to the other two input terminals, and the output of the third output terminal of the differential stage is amplified. And a first input terminal connected to a predetermined node on the first wiring in the semiconductor integrated circuit, and a second input terminal on the second wiring in the semiconductor integrated circuit. A differential amplifier connected to a given node;
A capacitor connected between the output terminal of the output stage and the first or second input terminal;
A semiconductor integrated circuit comprising a noise reduction circuit in which a third input terminal of the differential stage is connected to a node of a reference potential. In a semiconductor integrated circuit in which a digital circuit and an analog circuit are mixedly mounted,
The first, second, and third input terminals and the first, second, and third output terminals corresponding to the input terminals, and the first, second, and third output terminals correspond to the first, second, and third output terminals. A differential stage that outputs a difference between an input voltage to the input terminal and a weighted addition voltage of input voltages to the other two input terminals, and outputs of the first and second output terminals of the differential stage Each of the first and second output stages, the first input terminal is connected to a predetermined node on the first wiring in the semiconductor integrated circuit, and the second input terminal is the semiconductor integrated circuit A differential amplifier having a third input terminal connected to a reference potential node;
A first capacitor connected between an output terminal of the first output stage and a first input terminal;
A semiconductor integrated circuit comprising a noise reduction circuit comprising a second capacitor connected between an output terminal of the second output stage and the second input terminal. The differential stage is:
A first channel type first MOS transistor in which one of a source and a drain is connected to a node of a power supply voltage and a bias voltage is supplied to a gate;
A second channel type second MOS transistor in which one end between the source and drain is connected to the other of the source and drain of the first MOS transistor, and the first input terminal is provided at the gate;
A first channel type third MOS transistor in which one of a source and a drain is connected to a node of the power supply voltage and the bias voltage is supplied to a gate;
One end between the source and drain is connected to the other of the source and drain of the third MOS transistor, and the other end between the source and drain is connected in common to the other end between the source and drain of the second MOS transistor. A second channel type fourth MOS transistor whose gate is provided with the second input terminal;
A first channel type fifth MOS transistor in which one of a source and a drain is connected to a node of the power supply voltage and the bias voltage is supplied to a gate;
One end between the source and drain is connected to the other of the source and drain of the fifth MOS transistor, and the other end between the source and drain is connected in common to the other end between the source and drain of the second MOS transistor. A sixth MOS transistor of the second channel type in which the third input terminal is provided at the gate;
The source and drain are inserted between the common connection node at the other end between the source and drain of the second, fourth and sixth MOS transistors and the node of the ground voltage, and a constant bias voltage is supplied to the gate. A second channel type seventh MOS transistor,
The first output terminal is provided at a series connection node of the first and second MOS transistors,
The second output terminal is provided at a series connection node of the third and fourth MOS transistors,
12. The semiconductor integrated circuit according to claim 8, wherein the third output terminal is provided at a series connection node of the fifth and sixth MOS transistors. The first channel type first, third, and fifth MOS transistors have the same characteristics, and the second channel type second, fourth, and sixth MOS transistors have the same characteristics. The semiconductor integrated circuit according to claim 12.

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