JP2005033176A - Capacitor and method of manufacturing capacitor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin film capacitor that can obtain a more large electrostatic capacitance even when the capacitor has a small size, and to provide a method of manufacturing the capacitor. <P>SOLUTION: In the thin film capacitor, a first thin dielectric film 13(A), an another kind of thin electrode conductor film 14, and a second thin dielectric film 13(B) are arranged in this order between the same kind of thin electrode conductor films 17(A) and 17(B) adjoining each other in the direction of lamination. In addition, first and second thin coupling conductor film sections 19a and 19b are respectively protruded into first and second through holes 13h(A) and 13h(B) from the same kind of thin electrode conductor films 17(A) and 17(B) and an integral coupling conductor section 19 is formed in a second through hole 16 by coupling the first and second thin coupling conductor film sections 19a and 19b with each other. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a capacitor and a method for manufacturing the capacitor.

  In an integrated circuit device such as a CPU or other LSI that operates at high speed, power lines are allocated to a plurality of circuit blocks in the integrated circuit so as to branch from a common power source. When the elements are simultaneously switched at a high speed, a large current is drawn from the power supply at once, and there is a problem that fluctuations in the power supply voltage become a kind of noise and propagate to each circuit block through the power supply line. Therefore, providing a decoupling capacitor for reducing the power supply impedance for each circuit block is effective in suppressing noise propagation between blocks due to power supply voltage fluctuations. Further, a bypass capacitor (commonly referred to as “pass capacitor”) that removes external noise such as surge noise in an AC filtering manner may be provided in the same connection form.

  By the way, in the case of a large-scale integrated circuit such as a CPU, the number of circuit blocks to be built is large, the number of power supply terminals and ground terminals tends to increase, and the distance between terminals is steadily decreasing. Decoupling capacitors need to be connected to each power supply line going to each circuit block, and it is not only difficult to mount capacitors individually in an integrated circuit where many terminals are densely packed, but also miniaturization, etc. Go backwards in the flow.

Therefore, in Patent Document 1 and Non-Patent Document 1, a ferroelectric thin film and a metal thin film are laminated, and a large number of capacitor terminals individually connected to a dense integrated circuit side terminal are formed using photolithography technology. A recessed thin film decoupling capacitor is disclosed. In a high frequency region (especially 100 MHz or more) where the noise problem due to power supply voltage fluctuation at the time of high-speed switching is particularly likely to occur, the specific gravity of the inductive reactance term occupying the power supply impedance becomes large. Making the distance from the terminal as close as possible is effective in reducing the power source impedance. Further, when the inductance of the terminal portion increases, there is a problem that the resonance point is generated by coupling with the capacitance component of the decoupling capacitor, and the bandwidth capable of obtaining a sufficient impedance reduction effect is reduced. Therefore, using the photolithography technology as described above to produce a thin film capacitor with a small distance between terminals contributes not only to the miniaturization of the element but also to the reduction of the power source impedance and the broadening of the band, which are the original purposes. There are advantages to doing.
JP 2003-142624 A Kazuaki Kurihara “Development of Low Inductance Thin Film Decoupling Capacitors” Electronics Packaging Technology Vol. 19 (2003) No. 1, p. 50

  By the way, in recent years, devices using integrated circuits have been remarkably miniaturized, and decoupling capacitors have been required to be smaller. However, when the element size of the capacitor becomes small, it becomes difficult to realize a desired capacitance within a limited size. In particular, in order to enhance the impedance reduction effect in a relatively low band, a decoupling capacitor having a larger capacity is required. However, the thin film decoupling capacitors disclosed in Patent Document 1 and Non-Patent Document 1 described above are capacitors. There are only two layers of electrodes, and no consideration is given to a specific method for increasing the capacity or compensating for the reduction of the element size in terms of capacity.

  An object of the present invention is to provide a thin film capacitor capable of obtaining a larger capacitance even with a small size, and a manufacturing method thereof.

Means for Solving the Problems and Effects of the Invention

In order to solve the above problems, the capacitor of the present invention is:
A first type having a thin film laminate in which a plurality of dielectric thin films and a plurality of electrode conductor thin films forming a capacitor are alternately laminated, and separated from each other in a direct current manner on the first main surface of the thin film laminate A terminal and a second type terminal are formed,
The electrode conductor thin film is alternately arranged in the stacking direction in such a manner that the first kind electrode conductor thin film conducting to the first kind terminal and the second kind electrode conductor thin film conducting to the second kind terminal are separated by the dielectric thin film. A first dielectric thin film, another kind of electrode conductor thin film, and a second dielectric thin film between one of the same kind of electrode conductor thin film and the other of the same kind of electrode conductor thin film adjacent to each other in the stacking direction. Arranged in this order,
The first through hole formed in the first dielectric thin film and the second through hole formed in the other-type electrode conductor thin film have an overlap by in-plane projection, and the second through hole and the second through hole The third through-hole formed in the dielectric thin film has an overlap by in-plane projection,
A coupling conductor portion that joins one homogeneous electrode conductor thin film and the other homogeneous electrode conductor thin film fills the first through hole and the third through hole, respectively, and is coupled with at least one of the two identical electrode conductor thin films. The outer peripheral surface of the coupling conductor portion is formed as a thin film portion to be formed and is filled in the second through hole with the first dielectric thin film and the dielectric hole filling portion integrated with the second dielectric thin film. And the inner peripheral surface of the second through hole are separated from each other in a direct current manner. In the present invention, “thin film” means a film having a thickness of 1.5 μm or less.

  According to this structure, the electrode conductor thin films of different polarities of the capacitor are alternately laminated as a first kind electrode conductor thin film and a second kind electrode conductor thin film via a plurality of dielectric thin films, and further, the first kind electrode conductor thin film And the second-type electrode conductor thin film are coupled by coupling conductor portions respectively filling (first and third) through-holes formed in the dielectric thin film. The coupled conductor portion is a thin film portion that is co-filmed with at least one of two similar electrode conductor thin films. The coupling conductor portion is provided with a second through hole at a position where it intersects with different types of electrode conductor thin films having different polarities, and the coupling conductor thin film portion is disposed inside the second through hole, and the second penetration hole. In the hole, the outer peripheral surface of the coupling conductor portion and the inner peripheral surface of the second through hole are separated in a direct current manner by the dielectric hole filling portion. As a result, two types of electrode conductor thin films of the same type (that is, those having the same polarity when a capacitor is used) are connected to each other by a plurality of layers and a coupled conductor thin film portion, and on the other hand, , Different polarities) are completely separated in a direct current manner through the dielectric thin film and the dielectric hole filling portion. As a result, the total area of the electrode conductor thin film of each polarity is expanded by multilayering, and in combination with the thinning effect of the dielectric layer, the achievable capacitance is greatly increased even if the element size is small. Can be made.

  Moreover, the (first to third) through holes formed in the electrode conductor thin film and the dielectric thin film can be easily formed in each thin film by photolithography, and the dielectric hole filling portion is a dielectric thin film. When the film is formed and deposited, the raw material is also deposited in the second through-hole. In addition, the coupled conductor thin film portion is disposed in the first through third through-holes when the electrode conductor thin film is formed and deposited. Can also be formed very easily. That is, although the electrode conductor thin film and the dielectric thin film are laminated in multiple layers in the lamination direction and the electrode conductor thin films having different polarities are separated from each other in a direct current manner, It can be easily manufactured by simply repeating patterning by lithography and general film formation.

  The thickness of the dielectric thin film is preferably 10 nm or more and 1000 nm or less, for example. When the thickness of the dielectric thin film is less than 10 nm, the direct current separation state between the electrode conductor thin films separated by the dielectric thin film deteriorates, and the occurrence of leakage current becomes significant. On the other hand, when the thickness of the dielectric thin film exceeds 1000 nm, the merit of miniaturization or large capacity peculiar to the thin film capacitor is not significant. The thickness of the dielectric thin film is more preferably 30 nm or more and 500 nm or less. On the other hand, for example, when a metal thin film is used as the electrode conductor thin film, the thickness is desirably set to 10 nm or more and 500 nm or less. When the thickness of the metal thin film forming the electrode conductor thin film is less than 10 nm, the sheet resistance of the thin film increases, so that the DC resistance component added in series to the formed capacitor increases in terms of the equivalent circuit. This is a cause of impairing the impedance reduction effect when used for a decoupling capacitor, a bypass capacitor, or the like, and may lead to narrowing of the bandwidth due to formation of an RC series resonance circuit. In addition, the use of an electrode conductor thin film having a thickness of 500 nm or more also causes an increase in cost. The thickness of the electrode conductor thin film is more desirably 50 nm or more and 300 nm or less.

  For the same kind of electrode conductor thin film coupled at the coupling conductor portion, in order to reduce inductance and prevent DC resistance increase, each electrode conductor thin film has a plurality of coupling conductor portions that are electrically connected to the electrode conductor thin film on the same main surface side. It is desirable to form them individually. In this case, it is desirable that the distance between the edges of the plurality of coupled conductor portions which are different and closest to each other is 20 μm or more and 300 μm or less. When the distance between the edges is less than 20 μm, a short circuit is likely to occur between different types of coupled conductor parts to be separated in a direct current manner. In addition, it may be difficult to fill the dielectric layer between the coupling conductor portions, and defects such as voids may be easily generated. On the other hand, if the distance between the edges exceeds 300 μm, the direct current resistance of the capacitor is likely to increase. On the other hand, if the distance between the different types of coupling conductors is made close to 300 μm or less, the apparent inductance of the coupling conductors can be reduced due to the mutual inductive cancellation effect of the negative phase alternating current waveforms flowing through the different types of coupling conductors. As a result, the impedance of the capacitor can be further reduced. Note that the photolithography technique can be used in the present invention when the coupling conductor portion is fine in the order of μm as described above when used as a decoupling capacitor for an integrated circuit having a large number of power supply terminals or ground terminals. Even when it is dense, there is an advantage that it can be formed easily and with high precision.

  In this case, a plurality of first-type terminals and second-type terminals are arranged at predetermined intervals on the first main surface of the thin film laminate that forms the main body of the capacitor. The seed terminal can be coupled to the first-type electrode conductor thin film and the second-type electrode conductor thin film closest to the first main surface in the stacking direction either directly or via an auxiliary coupling conductor portion. As a result, the distance from the electrode conductor thin film of the capacitor terminal portion is greatly reduced, and the inductance of the terminal portion can be reduced, so that the impedance can be further reduced. And, when a terminal array in which the plurality of first-type terminals and second-type terminals are mixed is formed on the first main surface of the thin-film laminate, the dissimilar terminals closest to each other in the terminal array It is desirable that the interval between the edges is 20 μm or more and 300 μm or less. When used as a decoupling capacitor, one of the above-mentioned different terminals functions as a power supply terminal and the other functions as a ground terminal. The apparent inductance of the terminal portion can be reduced by the mutual inductive canceling effect between the flowing reverse-phase alternating current waveforms, and as a result, the impedance of the capacitor can be further reduced.

  Next, a plurality of coupling conductor portions (for example, the same number as the first type terminal or the second type terminal conducting to the electrode conductor thin film) may be dispersedly formed in the surface of the electrode conductor thin film. it can. In this way, the direct current resistance component and parasitic inductance of the entire capacitor including the coupling conductor portion can be greatly reduced, and as a result, a low impedance thin film capacitor can be obtained.

  The electrode conductor thin film and the coupling conductor portion can be made of a metal such as Cu, Ag, Au, or Pt, for example, and it is efficient to form the electrode conductor thin film and the bonding conductor portion by a vapor deposition method such as sputtering or vacuum deposition. On the other hand, in the case of an inorganic dielectric such as an oxide or a nitride, the dielectric thin film and the dielectric hole filling portion are formed by a gas phase such as high-frequency sputtering, reactive sputtering, or chemical vapor deposition (CVD). It is efficient to use a film forming method. In the case of an oxide-based dielectric thin film, it can be formed by a chemical solution deposition (CSD) method such as a so-called sol-gel deposition method. The chemical solution film formation method is a method of obtaining a dielectric thin film by drying or baking a coating layer of a solution that is a raw material of a compound constituting the dielectric thin film. There is an advantage that can be formed. For example, in the sol-gel film forming method, a sol-like composition of an organometallic solution is applied onto a plate-like substrate, dried and then fired to obtain a dielectric thin film (for example, an oxide thin film).

  In particular, when it is desired to obtain a capacitor having a high capacitance, or when it is desired to further reduce the size of a capacitor having the same capacitance, it is advantageous to use a dielectric having a higher dielectric constant. It is desirable that the body thin film and the dielectric hole filling portion be made of a high dielectric constant ceramic (defined as a ceramic having a relative dielectric constant of 50 or more: for example, a ferroelectric ceramic). As the dielectric thin film made of a high dielectric constant ceramic, a composite oxide having a perovskite crystal structure, for example, one composed of one or more of barium titanate, strontium titanate and lead titanate is particularly used. Since it has a high dielectric constant and is relatively easy to manufacture, it can be suitably used in the present invention. Note that a dielectric thin film made of a high dielectric constant ceramic causes a significant decrease in dielectric constant when the crystallinity is impaired. Therefore, it is desirable that the dielectric thin film be configured as a crystalline thin film. When employing a vapor phase film formation method such as sputtering, crystallization can be promoted by forming a film while heating the plate-like substrate. When employing a chemical solution film formation method such as a sol-gel method, Crystallization of the film can be advanced by baking treatment after drying.

  Next, in the capacitor according to the present invention, the second main surface of the thin film laminate is bonded to the first main surface of the plate-like substrate, and the first main surfaces of the plate-like substrate are separated from each other in a direct current manner. A seed substrate side terminal and a second type substrate side terminal are formed, and the first type substrate side terminal and the second type substrate side terminal are closest to the second main surface of the thin film laminate. And it can be set as the structure respectively couple | bonded with the 2nd type electrode conductor thin film. The first type terminal and the second type terminal formed on the first main surface of the thin film laminate can be solder-connected to the power supply terminal and the ground terminal on the semiconductor element side formed of a silicon integrated circuit chip, respectively, A power supply terminal and a ground terminal on the main substrate side mainly composed of a polymer material can be connected to the first-type substrate-side terminal and the second-type substrate-side terminal on the second main surface side of the plate-like substrate. Therefore, the capacitor having the structure can be functioned as an intermediate substrate that is located between the semiconductor element and the main substrate and mediates the connection between the two.

  In addition, by connecting a capacitor that functions as a decoupling capacitor (or bypass capacitor) directly to a semiconductor element in the form of an intermediate substrate, the decoupling capacitor can be brought closer to the semiconductor element, and the wiring length between the power supply terminal and the decoupling capacitor Can be shortened. As a result, the inductance of the capacitor terminal can be reduced, which contributes to lowering the impedance of the decoupling capacitor. Further, since the decoupling capacitor is incorporated in the intermediate board, it is not necessary to arrange the decoupling capacitor as a separate element on the back side of the main board, and the number of parts can be reduced or the apparatus can be downsized.

  In Patent Document 1, the thin film capacitor is formed on a silicon substrate, the semiconductor element is further mounted on the thin film capacitor, the silicon substrate is peeled off, and the thin film capacitor is singly formed as an intermediate substrate. It has become. This configuration requires man-hours for peeling the silicon substrate, and the thin film capacitor having the peeled substrate has a drawback that the rigidity is not so high. For this reason, when the main substrate to be connected is mainly composed of a polymer material such as a mother board or an organic package substrate that forms the second intermediate substrate, when a thermal history such as solder reflow is added, The difference in coefficient of linear expansion coefficient between the semiconductor element and the main board cannot be absorbed, and there is a risk that the solder may be peeled off or the thin film capacitor itself may be damaged due to insufficient rigidity. However, as described above, the substrate-side terminal and the substrate-side coupling conductor portion are formed in the plate-like substrate that is the film formation base of the thin film laminate constituting the thin-film capacitor, and the plate-like substrate is used as a component of the intermediate substrate. Once incorporated, the substrate peeling step is not required, and the rigidity of the intermediate substrate is greatly improved, and the occurrence of the above-described problems can be effectively prevented.

  From the viewpoint of improving rigidity, the plate-like substrate is preferably formed thicker than a thin film laminate having low rigidity. The material of the plate-like substrate may be a polymer material. However, more preferably, the difference in expansion coefficient between the semiconductor element (for example, silicon) and the intermediate substrate and between the intermediate substrate and the main substrate mainly composed of the polymer material is reduced, and as a result, the intermediate substrate is not reflowed during solder reflow. It is desirable from the viewpoint of preventing the solder from peeling off at the terminals so that the level of the thermal shear stress applied to each terminal formed on both sides can be reduced. The linear expansion coefficient of silicon from room temperature to around 300 ° C used for solder reflow is as low as 2-3 ppm / ° C. Conversely, polymer materials such as epoxy resins that constitute the main substrate (motherboard or organic package substrate) are It is as high as 17 to 20 ppm / ° C. For example, in the case of the above-described perovskite type oxide, the dielectric layer constituting the thin film laminate is relatively high at 12 to 13 ppm / ° C., and therefore the linear expansion coefficient is lower than this. Constructing a plate-like substrate with a ceramic material is effective for reducing the above-described differences in linear expansion coefficients and, in turn, reducing the shear stress acting on the terminals. As such a ceramic material, alumina (7 to 8 ppm / ° C.), glass ceramic obtained by adding 40 to 60 parts by weight of an inorganic ceramic filler such as alumina to borosilicate glass or lead borosilicate glass can be used. As other ceramic materials, aluminum nitride, silicon nitride, mullite, silicon dioxide, magnesium oxide, and the like can also be used. On the other hand, as a material other than ceramic, silicon can also be used from the viewpoint that the linear expansion coefficient is similar to that of a semiconductor element (however, a capacitor incorporated in a thin film laminate or a conductive material to this). It is necessary to consider insulation from the conductor part).

  Due to the difference in the coefficient of linear expansion, relative displacement in the in-plane direction between the terminals is likely to occur between the semiconductor element and the intermediate substrate and between the intermediate substrate and the main substrate, but this is restrained by solder bonding between the terminals. Therefore, a shear stress is applied to the solder connection portion between the terminals. In this case, it is desirable that the plate-like substrate forming the main part of the intermediate substrate is made of a ceramic material having a higher Young's modulus than the high dielectric constant ceramic forming the dielectric thin film. As a result, the rigidity of the plate-like substrate is increased, and even if there is a slight difference in linear expansion coefficient, the amount of elastic deformation on the plate-like substrate side remains small. Becomes smaller, and it is difficult to cause problems such as peeling and disconnection of the connection portion.

  The plate-like substrate can also be configured as a multilayer ceramic capacitor substrate in which fired ceramic dielectric layers and electrode conductor layers fired simultaneously with the fired ceramic dielectric layers are alternately laminated. Thereby, the electrostatic capacitance of the whole capacitor can be further increased by the thin film capacitor built in the thin film laminate and the fired multilayer ceramic capacitor built on the plate-like substrate side. Moreover, a parallel combination of a relatively large-capacity thin film capacitor and a monolithic ceramic capacitor having a smaller capacity than that can be realized with one element, and the impedance reduction effect may be secured in a wider frequency band. . The dielectric layer used for the multilayer ceramic capacitor can be composed of a paraelectric ceramic such as alumina or glass ceramic. From the viewpoint of increasing the capacity, the dielectric layer used for the multilayer ceramic capacitor In addition, it is desirable to use a high dielectric constant ceramic (the above-mentioned perovskite oxide layer).

Next, the capacitor of the present invention is formed on the first main surface of the thin film laminate, a thin film laminate side terminal array in which a plurality of first type terminals and a plurality of second type terminals are mixed,
A substrate-side terminal array in which a plurality of first-type substrate-side terminals and a plurality of second-type substrate-side terminals are mixed is formed on the second main surface of the plate-like substrate,
The terminal arrangement interval of the substrate side terminal array can be configured to be set wider than the terminal arrangement interval of the thin film laminate side terminal array.

  In recent years, as described above, the terminal spacing of integrated circuit elements to which capacitors are to be connected tends to become narrower. On the other hand, the terminal interval on the main board side may not be narrowed from the viewpoint of manufacturing cost. In this case, the terminal interval of the integrated circuit element and the terminal interval on the main board side may not match. However, as described above, in the capacitor forming the intermediate substrate, the base-side terminal array formed on the second main surface of the plate-like base is more than the thin-film stack-side terminal array formed on the first main surface of the thin-film stack. If the terminal arrangement interval is set wide, even if the above-mentioned terminal interval mismatch occurs on the front and back sides of the capacitor forming the intermediate substrate, both can be connected without any problem.

  In this case, in the thin film laminate-side terminal array on the thin film laminate, the first type terminal and the second type terminal are directly or via an auxiliary coupling conductor portion with respect to the first type electrode conductor thin film closest to the first main surface. It has already been described that it is advantageous to reduce the inductance of the terminal portion of the thin film capacitor by coupling (that is, directly coupling) in the stacking direction. On the other hand, on the first main surface of the plate-like substrate, a first-type substrate-side coupling conductor portion conducting to the first-type substrate-side terminal, and a second-type substrate-side coupling conductor portion conducting to the second-type substrate-side terminal; Are arranged at intervals larger than the terminal interval of the thin film laminate-side terminal array, respectively, with respect to the first electrode thin film conductor and the second electrode thin film conductor closest to the second main surface of the thin film laminate, respectively. It can be coupled in the stacking direction directly or via an auxiliary coupling conductor part. In this case, in order to match the narrow terminal interval on the thin film laminate side terminal array side with the terminal arrangement of the wide substrate side terminal array, the terminal interval must be converted somewhere inside the capacitor.

  For example, the first terminal-coupled conductor portion in which the first-type substrate-side coupled conductor portion and the second-type substrate-side coupled conductor portion are arranged at a larger interval than the thin-film laminate-side terminal array on the second main surface of the thin film laminate. And it can be set as the structure connected to the 2nd terminal coupling conductor part, respectively. In other words, in this structure, the terminal spacing is converted inside the thin film laminate, and the first main surface of the plate-like substrate that forms a boundary with the thin film laminate is connected to the substrate-side coupling conductor portion having a large interval. It means that it has already been put together. Thereby, on the plate-like substrate side, it is not necessary to make the substrate-side coupling conductor portion so fine, and the production by firing is easy. On the other hand, on the thin film laminate side, not only the fine terminal arrangement of the thin film laminate side terminal array but also the terminal interval conversion part can be relatively easily manufactured by applying the photolithography technique.

  In this case, in the thin film laminate, at least one electrode conductor thin film is connected to the electrode conductor thin film from the thin film laminate side terminal array side to the electrode conductor thin film at the first arrangement interval. On the other hand, from the substrate side terminal array side to the electrode conductor thin film, the coupling conductor portion (either the coupling conductor portion of the thin film laminate or the substrate side coupling conductor portion) at a second arrangement interval wider than the first arrangement interval. ) Are connected to each other. In the present specification, the first arrangement interval and the second arrangement interval are both defined as meaning the average interval of the coupling conductor portions. By changing the positions of corresponding ones of the connecting conductor portions connected to the upper and lower sides of the gap converting thin film, the terminal gap can be converted very easily.

  There are also the following advantages. That is, in Patent Document 1, as shown in FIG. 2, a lead wiring portion (reference numeral 32: third conductor layer) for terminal interval conversion is placed at the uppermost layer position separately from the capacitor electrode. Not only does this increase the number of layers, but the manufacturing process is lengthened, and a long lead wiring is formed at a position directly connected to the terminal portion of the semiconductor element, so that the inductance of the terminal portion is greatly increased, resulting in low impedance. It is difficult to increase the frequency and bandwidth. However, if the electrode conductor thin film constituting the capacitor is used as a thin film for interval conversion, it is not necessary to form the long wiring portion as described above, or even if the length can be kept to a minimum, The inductance of the terminal portion can be greatly reduced.

  In this case, in the thin film laminate, at least one layer of the first-type electrode conductor thin film and at least one layer of the second-type electrode conductor thin film can each be a thin film for interval conversion. Thereby, it is possible to easily convert the terminal interval independently while maintaining the DC separation state of the first type terminal and the second type terminal. That is, the first type electrode conductor thin film is used for expanding the interval of the coupling conductor portion conducting to the first type terminal, and the second type electrode conductor thin film is used for expanding the interval of the coupling conductor portion conducting to the second type terminal. Thus, the intervals between the various types of terminals can be expanded and converted at different positions in the stacking direction.

  If spacing between different types of terminals is to be performed at the same position in the stacking direction, a through hole is formed in the electrode conductor thin film of the first polarity (one of the first type and the second type), and the first hole is inserted into the through hole. Bipolar (the other of the first type and the second type) conductive thin films must be arranged in a relatively large area in order to expand the terminal spacing in a form separated by a dielectric. This second polar conductive thin film has the same polarity as the adjacent conductive thin film across the dielectric thin film, and therefore hardly contributes to the formation of capacitance. On the other hand, the first polarity electrode conductor thin film has a different polarity from the adjacent conductor thin film across the dielectric thin film, so it is the main component of capacitance formation, but it penetrates to place the second polarity conductor thin film Since a large hole must be formed, the electrode effective area is reduced, leading to a decrease in capacitance.

  However, if the distance between various terminals is extended and converted at different positions in the stacking direction, the first polar conductor thin film must be mixed with the first polar conductor thin film at the same position in the stacking direction. Therefore, the capacitance can be prevented from decreasing. More specifically, the first-type electrode conductor thin film and the second-type electrode conductor thin film are defined as the pre-conversion thin film of the same type closest to the thin film laminate side terminal array side with respect to the distance conversion thin film, Similarly, when the same kind of electrode conductor thin film closest to the base-side terminal array side is defined as a thin film after conversion, the thin film between the thin film for conversion and the thin film for interval conversion, and between the thin film for interval conversion and the thin film for conversion, 2 in which the coupling positions of the coupling conductor portions coincide with each other in the in-plane direction, and are located between the thin film before conversion and the thin film for interval conversion, and between the thin film for interval conversion and the thin film after conversion, respectively. It can be set as the structure which formed the 2nd through-hole for letting a joint conductor part pass in the positional relationship which mutually shifted | deviated to one other kind of electrode conductor thin film. As a result, the through-holes formed in the first-type electrode conductor thin film and the second-type electrode conductor thin film need only have the minimum necessary area to pass through the coupling conductor portion, regardless of the terminal spacing conversion. The influence of the decrease in capacitance can be eliminated as much as possible.

  When expanding the terminal spacing as described above, the first-type electrode conductors arranged on the second main surface side of the thin film laminate using the area difference between the thin film laminate side terminal array and the substrate side terminal array A part of the combination of the thin film and the second type electrode conductor thin film may have a larger area than the combination of the first type electrode conductor thin film and the second type electrode conductor thin film arranged on the first main surface side. it can. As a result, the capacitance of the capacitor can be further increased.

  In addition to the first type terminal and the second type terminal, a signal terminal can be formed on the first main surface of the thin film laminate. In this case, the signal terminal is connected to the signal base in the thin film stack so as not to conduct to the electrode conductor thin film in the thin film stack with respect to the signal base side terminal formed on the second main surface of the plate base. The connection can be made via the conductor portion and the signal substrate-side coupling conductor portion in the plate-like substrate. According to this, the signal line can be simultaneously formed in the thin film laminate, and the signal line can be formed in a form avoiding the capacitor portion, so that the influence on the signal quality is small. In this case, the dielectric layer covering the signal coupling conductor in the thin film laminate may be formed of a material having a lower dielectric constant than the dielectric layer covering the electrode conductor thin film. This is desirable because it is possible to prevent undesired coupling and, in turn, it is difficult to cause impedance mismatching of the signal lines.

  Next, in the capacitor according to the present invention, the second main surface of the thin film laminate is bonded to the first main surface of the plate-like substrate, and the first main surfaces of the plate-like substrate are separated from each other in a direct current manner. A seed substrate side terminal and a second class substrate side terminal are formed, and the first type substrate side terminal and the second type substrate side terminal are closest to the second main surface of the thin film laminate. It can be set as the structure respectively couple | bonded with the thin film and the 2nd type electrode conductor thin film. The first type terminal and the second type terminal formed on the first main surface of the thin film laminate can be solder-connected to the power supply terminal and the ground terminal on the semiconductor element side formed of a silicon integrated circuit chip, respectively, A power supply terminal and a ground terminal on the main substrate side mainly composed of a polymer material can be connected to the first-type substrate-side terminal and the second-type substrate-side terminal on the second main surface side of the plate-like substrate. Here, the plate substrate can be a wiring board (package board), and the main board can be a mother board.

  Here, the wiring board includes an insulating layer and a conductor layer (wiring layer), and is particularly preferably a multilayer wiring board. In order to achieve interlayer connection between these conductor layers, a coupling conductor portion (base-side coupling conductor portion) is formed inside the substrate. The conductor layer may be formed on the substrate surface or may be formed inside the substrate. The conductor layer functions as a routing wiring and can convert the terminal interval. For example, the first-type electrode conductor thin film closest to the second main surface of the thin-film laminate and the upper substrate-side combined conductor portion respectively bonded to the second-type electrode conductor thin film, the first-type substrate-side terminal, and the second type A lower base-side coupled conductor portion respectively coupled to the seed substrate-side terminal is pitch-converted via a conductor layer (leading wiring portion) inside the base body, thereby obtaining a coupled structure. In this case, the arrangement interval of the first terminal coupling conductor portion and the second terminal coupling conductor portion on the second main surface of the thin film laminate is such that the first-type substrate-side coupling conductor on the second main surface of the plate-like substrate (wiring board). It is possible to make it smaller than the arrangement interval of the first and second type substrate-side coupling conductor portions.

In another aspect, in order to solve the problem, the capacitor of the present invention includes:
A first type having a thin film laminate in which a plurality of dielectric thin films and a plurality of electrode conductor thin films forming a capacitor are alternately laminated, and separated from each other in a direct current manner on the first main surface of the thin film laminate A terminal and a second type terminal are formed,
The electrode conductor thin film is alternately arranged in the stacking direction in such a manner that the first kind electrode conductor thin film conducting to the first kind terminal and the second kind electrode conductor thin film conducting to the second kind terminal are separated by the dielectric thin film. A first dielectric thin film, another kind of electrode conductor thin film, and a second dielectric thin film between one of the same kind of electrode conductor thin film and the other of the same kind of electrode conductor thin film adjacent to each other in the stacking direction. Arranged in this order,
In the inner region determined by projecting through-holes formed in the other-type electrode conductor thin film in the stacking direction, a coupling conductor portion formed by coupling one same-type electrode conductor thin film and the other same-type electrode conductor thin film is located,
Between the coupling conductor portion and the other-type electrode conductor thin film, a dielectric hole filling portion integrated with the first dielectric thin film and the second dielectric thin film is interposed,
The dielectric hole filling portion surrounds the coupling conductor portion in the inner region of the through hole, so that the outer circumferential surface of the coupling conductor portion and the inner circumferential surface of the through hole of the other electrode thin film are separated in a direct current manner. It is characterized by being made.

  According to this structure, the electrode conductor thin films of different polarities of the capacitor are alternately laminated as a first kind electrode conductor thin film and a second kind electrode conductor thin film via a plurality of dielectric thin films, and further, the first kind electrode conductor thin film And the second type electrode conductor thin film are coupled by a coupling conductor portion. A through hole is provided at a position intersecting with different types of electrode conductor thin films having different polarities, and the coupling conductor thin film portion is positioned inside the through hole, and the outer circumferential surface of the coupling conductor portion is formed by a dielectric hole filling portion. The inner peripheral surface of the through hole is separated in a direct current manner. As a result, two types of electrode conductor thin films of the same type (that is, those having the same polarity when a capacitor is used) are connected to each other in a DC manner by a plurality of layers and a coupling conductor portion, A plurality of layers having different polarities are completely separated in a direct current manner through the dielectric thin film and the dielectric hole filling portion. As a result, the total area of the electrode conductor thin film of each polarity is expanded by multilayering, and in combination with the thinning effect of the dielectric layer, the achievable capacitance is greatly increased even if the element size is small. Can be made.

Further, the capacitor of the present invention can be manufactured with high efficiency and high accuracy by employing the following method. That is, the method for manufacturing a capacitor according to the present invention produces a plate-like substrate in which the first-type substrate-side coupling conductor portion and the second-type substrate-side coupling conductor portion that are separated from each other in terms of DC are exposed on the first main surface. A thin film laminate forming step of forming on a plate substrate a thin film laminate in which a plurality of dielectric thin films forming a capacitor and a plurality of electrode conductor thin films are alternately laminated. The body formation process
a. Forming a first-type electrode conductor thin film on the first main surface of the plate-like substrate, which is electrically connected to the first-type substrate-side coupled conductor portion and separated from the second-type substrate-side coupled conductor portion in a direct current manner;
b. Forming a first dielectric thin film covering the first-type electrode conductor thin film;
c. A second type electrode conductor thin film that forms a cut in the first dielectric thin film, is electrically connected to the second type substrate side coupling conductor portion at the cut, and is DC-isolated from the first type substrate side coupling conductor portion. Forming a through-hole for exposing the first dielectric thin film in the second type electrode conductor thin film, and
d. The second type electrode conductor thin film and the second type electrode conductor thin film are integrated with the first dielectric thin film in the inner region determined by projecting through holes provided in the second type electrode conductor thin film in the stacking direction. Forming a second dielectric thin film covering the inner peripheral surface of the through-hole provided in
e. Forming a slit in the second dielectric thin film, and forming a conductive film that is electrically connected to the first type electrode conductor thin film at the cut and separated from the second type electrode conductor thin film in a direct current manner. It is characterized by.

  In the method of the present invention, the electrode conductor thin film and the dielectric thin film of the capacitor are alternately formed one by one using a photolithography technique or the like. When manufacturing multilayer thin film capacitors, one key is technology that connects electrode conductor thin films of the same polarity, such as power supplies and grounds, or dielectric thin films with high efficiency and high accuracy in the stacking direction. is there. In the method of the present invention, the step d. As described in 2. above, the second dielectric that is integrated with the first dielectric thin film in the inner region of the through hole provided in the second type electrode conductor thin film and covers the inner peripheral surface of the through hole of the second electrode conductor A thin film is formed. And step e. As described above, a slit is formed in the opening or the like in the dielectric thin film, and upper and lower similar electrode conductor thin films (first-type electrode conductor thin film and third electrode conductor thin film) are connected at the cut. According to such a procedure, for example, as shown in the lowermost stage of FIG. 18 and the upper two stages of FIG. 19, a process of separating different kinds of electrode conductor thin films from each other in a direct current and a process of connecting adjacent dielectric thin films As a result, the unit of the capacitor can be built with high efficiency and high accuracy. Therefore, a multilayer thin film capacitor can be manufactured with high efficiency by repeating the above steps.

  Specifically, the steps a. Is a step of forming a first-type electrode conductor thin film having a first through hole for exposing the second-type substrate-side coupling conductor portion. Step b. Is a step of forming the first dielectric thin film so that the surface of the first type electrode conductor thin film and the inner peripheral surface of the first through hole provided in the first type electrode conductor thin film are covered.

  In addition, step d. Forming a second dielectric thin film so that the surface of the second type electrode conductor thin film and the inner peripheral surface of the through hole provided in the second type electrode conductor thin film are covered; and the second type electrode conductor A part of the dielectric hole filling portion made of the first dielectric thin film and the second dielectric thin film integrated in the inner region of the through hole provided in the thin film is made to be second by the dielectric hole filling portion. And maintaining a state where the inner peripheral surface of the through hole of the seed electrode conductor thin film is covered, and providing a dielectric thin film side through hole leading to the first type electrode conductor thin film. In this case, step e. Is a step of forming an electrode conductor thin film separated from the second type electrode conductor thin film in direct current so as to be in direct contact with the first kind electrode conductor thin film exposed in the dielectric thin film side through-hole. According to such a method, direct current separation between the first-type electrode conductor thin film and the second-type electrode conductor thin film can be ensured, and the connection process between the electrode conductor thin films having the same polarity can be performed very easily. .

Also, the following steps can be performed.
Step a. Is a first type electrode having a first through hole etched in a donut shape, leaving a second type coupled conductor portion that is electrically connected to the second type substrate side coupled conductor portion and insulated from the first type electrode conductor thin film. The step is to form a conductive thin film. Step b. Is a step of forming the first dielectric thin film so that the surface of the first type electrode conductor thin film and the inner peripheral surface of the first through hole provided in the first type electrode conductor thin film are covered.

  And the above-mentioned process c. The through-hole is a through-hole etched into a donut shape, leaving a first-type coupling conductor portion that is electrically connected to the first-type substrate-side coupling conductor portion and insulated from the second-type electrode conductor thin film. In addition, step d. Forming a second dielectric thin film so that the surface of the second type electrode conductor thin film and the inner peripheral surface of the through hole provided in the second type electrode conductor thin film are covered; and the second type electrode conductor A part of the dielectric hole filling portion made of the first dielectric thin film and the second dielectric thin film integrated in the inner region of the through hole provided in the thin film is made to be second by the dielectric hole filling portion. And maintaining a state where the inner peripheral surface of the through hole of the seed electrode conductor thin film is covered, and providing a dielectric thin film side through hole that leads to the first type coupling conductor portion. In this case, step e. Is a step of forming an electrode conductor thin film DC-separated from the second type electrode conductor thin film so as to be in direct contact with the first type coupling conductor portion exposed in the dielectric thin film side through hole. Even with such a method, it is possible to reliably separate the first-type electrode conductor thin film and the second-type electrode conductor thin film from each other in a direct current manner, and it is possible to extremely easily perform the connection process between the electrode conductor thin films having the same polarity.

Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 shows an example in which a capacitor 1 according to an embodiment of the present invention is configured as an intermediate substrate disposed between a semiconductor integrated circuit element 2 and a main substrate 3 (hereinafter referred to as an intermediate substrate 1 if necessary). Also called). In the present embodiment, the first main surface of the plate-like member is a surface appearing on the upper side in the drawing, and the second main surface is a surface appearing on the lower side.

  The semiconductor integrated circuit element 2 has an element-side terminal array 4 composed of a plurality of signal terminals, a power supply terminal, and a ground terminal on the second main surface, and a thin film laminate-side terminal array formed on the first main surface of the intermediate substrate 1. 5 is flip-chip connected via a solder connection portion 9. On the other hand, the main substrate 3 is a mother board or an organic laminated package substrate forming a second-stage intermediate substrate, each of which is mainly composed of a polymer material reinforced with ceramic particles or fibers as fillers. In the main board side terminal array 8 made of metal pins, the base side terminal array 7 formed on the second main surface of the intermediate board 1 is connected via a solder connection portion 9. The capacitor 1 constituting the intermediate substrate functions as a decoupling capacitor connected in parallel to the power supply line of the semiconductor integrated circuit element 2 as shown in FIG. In the equivalent circuit of FIG. 2, it is drawn that an independent decoupling capacitor is provided for each power supply line, but these decoupling capacitors are all connected in parallel between the power supply line of the same voltage and the ground. Therefore, in the following embodiments, the decoupling capacitor will be described by being representatively represented by a configuration in which the power supply line is shared as a single capacitor (however, the present invention is not limited to this).

  As shown in FIG. 3, the capacitor 1 has a structure in which a thin film laminate 10 constituting a thin film capacitor is bonded to a plate-like substrate 50 and a first main surface of the plate-like substrate 50. On the first main surface of the thin film laminate 10, a first type terminal 5a and a second type terminal 5b, one of which is used as a power supply terminal and the other as a ground terminal, are arranged in a staggered grid (or may be staggered). The thin film laminate side terminal array 5 is arranged. Further, on the second main surface of the plate-like substrate 50, a first-type substrate-side terminal 7a and a second-type substrate-side terminal 7b, one of which is used as a power supply terminal and the other as a ground terminal, are thin-film laminate-side terminal arrays. The base-side terminal array 7 is formed by being arranged in an alternating grid pattern (or may be a staggered pattern) corresponding to the terminal array 5. Each of the arrays 5 and 7 has a plurality of signal terminals 5s and a signal base-side terminal 7s in a form surrounding a grid-like arrangement of power supply terminals and ground terminals.

FIG. 4 shows the detailed structure of the capacitor (intermediate substrate) 1.
The thin film laminate 10 is formed by alternately laminating a plurality of dielectric thin films 13 and a plurality of electrode conductor thin films 14 and 17 forming a capacitor. A first type terminal 5a and a second type terminal 5b are formed on the first main surface of the thin film laminate 10 so as to be separated from each other in terms of direct current. The electrode conductor thin films 14 and 17 are separated by a dielectric thin film 13 from a first kind electrode conductor thin film 14 conducting to the first kind terminal 5a and a second kind electrode conductor thin film 17 conducting to the second kind terminal 5b. Are arranged alternately in the stacking direction.

  On the other hand, the first-type substrate-side terminal 7 a and the second-type substrate-side terminal 7 b on the plate-like substrate 50 side are the first-type electrode conductor thin film 14 and the second-type electrode that are closest to the second main surface of the thin film laminate 10. The conductor thin film 17 is coupled to the thin film laminate 10 via the coupling conductor portions 15 and 19 on the thin film laminate 10 side. With this structure, as shown in FIG. 1, the first type terminal 5a and the second type terminal 5b formed on the first main surface of the thin film stack 10 have a semiconductor integrated circuit formed of a silicon integrated circuit chip or the like. The power supply terminal and the ground terminal (array 4) on the element 2 (FIG. 1) side can be connected by soldering. Further, a power terminal and a ground terminal (array 8) on the main substrate 3 side can be connected to the first-type substrate-side terminal 7a and the second-type substrate-side terminal 7b on the second main surface side of the plate-like substrate 50, respectively. Thus, the capacitor 1 can function as an intermediate substrate that is located between the semiconductor integrated circuit element 2 and the main substrate 3 and mediates the connection between the two.

  Returning to FIG. 4, as shown in a partially enlarged example, one of the same kind of electrode conductor thin films (here, the second kind of electrode conductor thin film) 17 (A) and the other of the same kind of electrode conductor thin film 17 (B ) Between the first dielectric thin film 13 (A), the other type electrode conductive thin film (here, the first type electrode conductive thin film) 14, and the second dielectric thin film 13 (B). Arranged in order. The first through-hole 13h (A) formed in the first dielectric thin film 13 (A) and the second through-hole 16 formed in the other-type electrode conductor thin film 14 are overlapped by in-plane projection. The second through-hole 16 and the third through-hole 13h (B) formed in the second dielectric thin film 13 (B) are overlapped by in-plane projection (in the illustrated portion, these Through-holes are arranged coaxially with a circular cross-section). The first through-hole 13h (A) and the third through-hole 13h (B) are filled, respectively, so that one homogeneous electrode conductor thin film 17 (A) and the other identical electrode conductor thin film 17 (B) A coupling conductor portion 19 is formed to couple the two. And in the 2nd through-hole 16, it couple | bonds by the dielectric material hole filling part 13v integrated (coupled) with the 1st dielectric thin film 13 (A) and the 2nd dielectric thin film 13 (B), respectively. The outer peripheral surface of the conductor portion 19 and the inner peripheral surface of the second through hole 16 are separated in a direct current manner. In the above structure, a structure part in which the first-type electrode conductor thin film 14 and the second-type electrode conductor thin film 17 are inverted is also formed in the same manner. In this embodiment, the first combined conductor thin film portion 19a protrudes from one homogeneous electrode conductor thin film 17 (A), the second coupled conductor thin film portion 19b protrudes from the other identical electrode conductor thin film 17 (B), and the second penetration In the hole 16, the first coupled conductor thin film portion 19a and the second coupled conductor thin film portion 19b are coupled to each other to form an integral coupled conductor portion 19 (however, protruding from one of the same kind of electrode conductor thin films). You may couple | bond the front-end | tip of a coupling | bonding conductor part directly with the other homogeneous electrode conductor thin film).

  The total area of the electrode conductor thin films 14 and 17 can be increased by combining the thin electrode conductor films 14 and 17, and the effect of reducing the thickness of the dielectric layer can greatly increase the achievable capacitance even if the element size is small. it can. In FIG. 4, the electrode conductor thin films 14 and 17 appear to be divided in the in-plane direction along with the illustration of the through holes 16 and 18, but in actuality, as shown in FIG. A continuous thin film is formed in the inward direction. The same applies to the dielectric thin film 13.

  The thickness of the dielectric thin film 13 is, for example, not less than 10 nm and not more than 1000 nm, and more preferably not less than 30 nm and not more than 500 nm. On the other hand, the thickness of the electrode conductor thin films 14 and 17 is, for example, not less than 10 nm and not more than 500 nm, and more preferably not less than 50 nm and not more than 500 nm. The electrode conductor thin films 14 and 17 and the coupling conductor portion 15 (19) can be made of, for example, a metal such as Cu, Ag, Au, or Pt, and are formed by a vapor deposition method such as sputtering or vacuum evaporation. On the other hand, the dielectric thin film 13 and the dielectric hole filling portion 13v are made of an inorganic dielectric such as oxide or nitride, and include high frequency sputtering, reactive sputtering, chemical vapor deposition (CVD), and the like. It is formed by the vapor phase film forming method. In this embodiment, the dielectric thin film 13 and the dielectric hole filling portion 13v are replaced with one or more of complex oxides having a perovskite crystal structure, for example, barium titanate, strontium titanate, and lead titanate. The oxide thin film configured as described above is formed by a sol-gel method.

  In addition, the same kind of electrode conductor thin film 14 (17) coupled by the coupling conductor portion 15 (19) is provided on the same main surface side for each electrode conductor thin film 14 (17) in order to prevent an increase in DC resistance. A plurality of coupling conductor portions 15 (19) that are electrically connected to the electrode conductor thin film 14 (17) are formed. Specifically, the coupling conductor portions 15 ( 19) is formed in a dispersed manner. The plurality of coupling conductor portions 15 (19) are different in kind, and the distance between the adjacent ones is set to 20 μm or more and 300 μm or less.

  In addition, the first-type terminal 5a and the second-type terminal 5b in the thin film laminate-side array 5 are respectively in relation to the first-type electrode conductor thin film 14 and the second-type electrode conductor thin film 17 that are closest to the first main surface. Directly (in this embodiment, the first-type electrode conductor thin film 14 side) or auxiliary coupling conductor portion 19 ′ (in this embodiment, the second-type electrode conductor thin film 17 side) is coupled in the layer thickness direction. Yes. Further, the distance between the edges of the first type terminal 5a and the second type terminal 5b that are closest to each other is set to 20 μm or more and 300 μm or less. When used for the decoupling capacitor 1, one of these different terminals functions as a power supply terminal and the other functions as a ground terminal. The apparent inductance can be reduced by a canceling effect between the alternating current waveforms, which contributes to further lowering the impedance of the capacitor 1. In addition, the same effect is produced between adjacent different types of coupling conductor portions 15 and 19.

  Capacitor 1 has base plate side terminals 7a, 7b, and 7s and base plate side coupling conductors 51a, 51b, and 51s formed in plate base plate 50 serving as a film formation base of thin film laminate 10 forming a thin film capacitor. The substrate 50 is incorporated as a component of the intermediate substrate. Therefore, the substrate peeling step as in Patent Document 1 is not required, and the rigidity of the intermediate substrate is greatly improved. Specifically, the plate-like substrate 50 is formed thicker than the thin film laminate 10 (for example, 100 μm or more and 2 mm or less), and in the present embodiment, alumina or glass ceramic is adopted as the constituent material. This material has an intermediate coefficient of linear expansion between the silicon forming the semiconductor integrated circuit element 2 and the polymer material forming the main substrate 3, and has a higher Young's modulus than the high dielectric constant ceramic forming the dielectric thin film 13. .

  Next, in the capacitor (intermediate substrate) 1 of the present embodiment, the terminal arrangement interval of the base-side terminal array 7 is set wider than the terminal arrangement interval of the thin film laminate-side terminal array 5. On the first main surface of the plate-like substrate 50, a first-type substrate-side coupling conductor portion 51a that conducts to the first-type substrate-side terminal 7a and a second-type substrate-side coupling conductor that conducts to the second-type substrate-side terminal 7b. Each end part with the part 51b is arranged at a larger interval (in average value) than the terminal interval of the thin film laminate side terminal array 5. In this case, in order to match the narrow terminal interval on the thin film laminate side terminal array 5 side with the terminal arrangement of the wide substrate side terminal array 7, it is necessary to convert the terminal interval inside the capacitor 1.

  In the present embodiment, on the second main surface of the thin film laminate 10 (the first main surface of the plate-like substrate 50), the first-type substrate-side coupling conductor portion 51a and the second-type substrate-side coupling conductor portion 51b are thin-film laminated. It is arranged at a larger interval than the body-side terminal array 5, and is directly (in this case) directly to the first-type electrode thin film conductor 14 and the second electrode thin film conductor 17 closest to the second main surface of the thin film laminate 10 In the embodiment, the first type electrode thin film conductor 14 side) or the auxiliary coupling conductor portion 15 ″ (in this embodiment, the second electrode thin film conductor 17 side) is coupled in the laminating direction. On the second main surface of the thin film laminate 10 (the first main surface of the plate-like substrate 50) that forms the boundary with the body 10, the first terminal coupling conductor portion 15 and the first terminal coupling conductor portion 15a and the first terminal coupling conductor portion 15 The distance between the two-terminal coupling conductors 19 is adjusted. Conversion of the terminal interval is performed in the interior of the thin film stack 10.

  Specifically, as shown in FIG. 4, at least one of the electrode conductor thin films 14 and 17, here, all the electrode conductor thin films 14 and 17 except for the uppermost layer are used as the distance converting thin film LT. In the distance conversion thin film LT, the electrode conductor thin films 14 and 17 are connected to the coupling conductor portions 15 (A) (19 (A)) from the thin film laminate side terminal array 5 side at the first arrangement interval d1. From the substrate side terminal array 7 side, the coupling conductor portions 15 (B) (19 (B)) are connected at a second arrangement interval d2 wider than the first arrangement interval d1. That is, the distance conversion thin film LT realizes the terminal distance conversion by making the connection positions of the coupling conductor portions 15 (19) connected to the upper and lower sides different from each other. Further, by using the electrode conductor thin films 14 and 17 constituting the capacitor 1 as the distance converting thin film LT, the first main surface side of the thin film laminate 10 to which the semiconductor integrated circuit element is connected is disclosed in Patent Document 1. It is no longer necessary to form a lead wiring portion for converting the terminal spacing, and the inductance of the capacitor terminal portion can be greatly reduced. The arrangement intervals of the coupling conductor portions 15 (A) (19 (A)) and the coupling conductor portions 15 (B) (19 (B)) connected to the upper and lower sides of the interval conversion thin film LT are basically, for example, an equal interval arrangement. However, the distance may be locally changed in order to avoid interference with the coupling conductors having different polarities, and the final arrangement interval is not necessarily equal. The first arrangement interval d1 and the second arrangement interval d2 are expressed by an average value of the intervals between the edges of the plurality of coupling conductor portions in consideration of such a case. For example, even if the array interval before conversion is distributed in the range of 100 μm or more and 200 μm or less, the array interval after conversion is distributed in the range of 150 μm or more and 300 μm, and there is an overlap of the interval range between them, the average It is only necessary that the second arrangement interval d2 expressed by the value is larger than the first arrangement interval d1.

  In FIG. 4, both the first-type electrode conductor thin film 14 and the second-type electrode conductor thin film 17 are used as the distance converting thin film LT, respectively. The first-type electrode conductor thin film 14 is used for expanding the interval of the coupling conductor portion 15 that conducts to the first-type terminal 5a, and the second-type electrode conductor thin film 17 is used to expand the interval of the coupling conductor portion 19 that conducts to the second-type terminal 5b. Is used.

  For example, in the modification of FIG. 10, the spacing between different types of terminals is expanded at the same position in the stacking direction in the thin film stack 10, that is, the formation position of the second-layer electrode conductor thin film 17 in the lowermost layer in FIG. ing. In this configuration, a large through hole 18 separated by a dielectric 13 is formed in the second type electrode conductor thin film 17 having the first polarity, and the second polarity (first type electrode conductor thin film is formed in the through hole 18. 14s) (which has the same polarity as that of No. 14) is arranged in a relatively large area for expanding the terminal interval. The auxiliary conductor thin film 14s has the same polarity as the first-type electrode conductor thin film 14 that is adjacent to the dielectric thin film 13, and therefore hardly contributes to the formation of capacitance. As a result, the second-type electrode conductor thin film 17 that is the main body for forming the capacitance is largely cut away by the through hole 18 to dispose the auxiliary conductor thin film 14s, the effective electrode area is reduced, and the capacitance is reduced. Leads to.

  However, as shown in FIG. 4, if the distance between the coupling conductors corresponding to various different terminals is extended and converted at different positions in the stacking direction in the thin film laminate 10, the capacitance is formed at the same position in the stacking direction. Therefore, it is not necessary to mix auxiliary conductor thin films having different polarities that do not contribute to the decrease in capacitance, and a reduction in capacitance can be prevented. In FIG. 4, for example, the same type of electrode conductor thin film 14 closest to the thin film laminate side terminal array 5 side with respect to the distance conversion thin film LT is defined as the pre-conversion thin film LB, and the same type of electrode conductor closest to the substrate side terminal array 7 side. When the thin film 14 is defined as the converted thin film LA, between the thin film LB before conversion and the distance converting thin film LT, and between the thin film for distance conversion LT and the converted thin film LA, each coupling conductor portion 15 (19) The coupling positions coincide with each other in the in-plane direction. On the other hand, the two other-type electrode conductor thin films 17 and 17 positioned between the thin films are coupled to the coupling conductor portion 15 in accordance with the conversion from the first arrangement interval d1 to the second arrangement interval d2 via the interval conversion thin film LT. The second through holes 16 and 16 for passing (A) and 15 (B) are formed so as to be shifted from each other. As a result, the auxiliary conductor thin film 14s as shown in FIG. As a result, the through-holes 16 and 18 formed in the first-type electrode conductor thin film 14 and the second-type electrode conductor thin film 17 need to pass through the coupling conductor portions 15 and 19, although the distance between the coupling conductor portions is changed. A minimum area is required, and the influence of the capacitance decrease due to the formation of the through hole can be eliminated as much as possible.

  Even when the auxiliary conductor thin film is used, as shown in FIG. 10, if the terminal spacing conversion is performed at once with a small number of layers, the area of the auxiliary conductor thin film 14s formed on the layer is extremely large. In other words, the decrease in capacitance becomes considerably remarkable. Therefore, as shown in FIG. 11, in each of the first-type electrode conductor thin film 14 and the second-type electrode conductor thin film 17, if the auxiliary conductor thin films 14s and 17s are dispersedly arranged in each layer, one auxiliary conductor thin film is obtained. The distance conversion amount to be handled is reduced, and the clearance for direct current separation from the coupling conductor thin film portions 15 and 19 in the through holes 16 and 18 can be kept in an area that does not deviate so much. As a result, a decrease in capacitance can be suppressed. In the structure illustrated in a partially enlarged manner in FIG. 4, the first dielectric between the one homogeneous electrode conductor thin film 17 (A) adjacent to the stacking direction and the other identical electrode conductor thin film 17 (B). The first through-hole 13h (A) formed in the body thin film 13 (A) and the second through-hole 16 formed in the other-type electrode conductor thin film 14 have an overlap by in-plane projection, and the second The through-hole 16 and the third through-hole 13h (B) formed in the second dielectric thin film 13 (B) are overlapped by in-plane projection, but in the configuration of FIGS. The three through holes are not necessarily arranged coaxially.

  Returning to FIG. 4, in the capacitor 1 of this embodiment, the terminal spacing is expanded as described above, and the base-side terminal array 7 has a larger array area than the thin-film laminate-side terminal array 5. Yes. Therefore, by utilizing the difference in area, a part of the set of the first type electrode conductor thin film 14 and the second type electrode conductor thin film 17 arranged on the second main surface side of the thin film laminate 10, here The lowermost two layers 14 (W) and 17 (W) have a larger area than the set of the first-type electrode conductor thin film 14 and the second-type electrode conductor thin film 17 arranged on the first main surface side. Thereby, the electrostatic capacitance of the capacitor 1 can be further increased.

  As shown in FIG. 7, only one layer of each of the first-type electrode conductor thin film 14 and the second-type electrode conductor thin film 17 can be used as the distance converting thin film LT. In this case, the distance conversion amount of the upper and lower coupling conductors 15, 15 ″ and 19, 51b in the distance conversion thin film LT is increased, but only the formation positions of the through holes 16 and 18 are changed. 7 has almost no influence, and therefore, the capacitance is hardly reduced.In the case of FIG. 7, since the distance conversion amount can be secured large, the first-type electrode conductor thin film 14 and the first electrode conductor thin film 14 whose area is expanded as compared with the other films are obtained. A pair with the two-type electrode conductor thin film 17 (that is, the lowermost two layers 14 (W) and 17 (W)) is used as the distance conversion thin films LT and LT.

  Returning to FIG. 4, in addition to the first type terminal 5a and the second type terminal 5b, the outer peripheral area of the thin film stack side terminal array 5 is allocated to the first main surface of the thin film stack 10 in the above-described signal use. A plurality of terminals 5s are formed. These signal terminals 5 s are not electrically connected to the electrode conductor thin films 14, 17 in the thin film laminate 10 with respect to the signal base-side terminals 7 s formed on the second main surface of the plate-like base 50 (this book In the embodiment, the electrode conductor thin films 14 and 17 are bypassed outward in the in-plane direction), and the signal coupling conductor portion 22 in the thin film laminate 10 and the signal substrate side coupling conductor portion 51s in the plate-like substrate 50 are provided. Connected through. In addition, the dielectric layer (hereinafter referred to as auxiliary dielectric layer) 12 covering the signal coupling conductor portion 22 in the thin film laminate 10 has a lower dielectric constant than the dielectric layer 13 covering the electrode conductor thin films 14 and 17. It is made of a material (in this embodiment, for example, silicon dioxide).

  In FIG. 4, the thin film laminate-side terminal array 5 is formed so as to be included in the base-side terminal array 7 in a projection relationship, and the terminals located on the outer side of the array are the corresponding terminals between the arrays as the arrangement interval increases. The amount of positional deviation between each other is large. Accordingly, the signal terminals 5 s arranged in the outer peripheral region of the thin film laminate side terminal array 5 are connected to the corresponding signal base side terminals 7 s so as to be routed in the in-plane direction formed in the thin film laminate 10. The part 21 also needs to be secured long. In the embodiment of FIG. 4, since the terminal interval conversion amount from the thin film laminate side terminal array 5 to the base side terminal array 7 is set to be relatively large, the routing wiring portion 21 of the signal terminal 5s located inside is In order to avoid interference in the in-plane direction with the routing wiring portion 21 of the outer signal terminal 5s, both wiring portions 21 and 21 are formed in different layers.

  On the other hand, when the terminal interval conversion amount is not so large, as shown in FIGS. 8 and 9, it is also possible to form the routing wiring portion 21 of the inner and outer signal terminals 5s in the same layer. In FIG. 8 and FIG. 9, since the terminal interval conversion amount is relatively small, all the electrode conductor thin films 14 and 17 are formed in the same area. Further, when only a part of the first-type electrode conductor thin film 14 and the second-type electrode conductor thin film 17 is used as the distance conversion thin films LT and LT, which thin film is set as the distance conversion thin films LT and LT is free. For example, in FIG. 8, one set of the lowermost layer is used as the thin film LT, LT for interval conversion, and in FIG. 9, the lowermost first-type electrode conductor thin film 14 and the uppermost-layer second-type electrode are used. The conductor thin film 17 is used as the distance converting thin films LT and LT. In the above-described embodiment, the signal terminal 5s is formed so as to allocate the outer peripheral region of the thin film laminate-side terminal array 5. However, in order to improve the signal line shielding property and suppress crosstalk, It is also possible to surround the terminal 5s (and the signal line conducting therewith) with the ground terminal (and the ground line conducting therethrough).

  Moreover, as shown in FIG. 12, it is also possible to set the same terminal arrangement interval between the thin film laminate side terminal array 5 and the base side terminal array 7. In this case, as shown in FIG. 13, the distance converting thin films LT and LT are not formed. In this case, the length of the signal line passing through the thin film stack 10 is equal to the thickness of the thin film stack and is sufficiently shorter than the signal wavelength. At this level, even if the dielectric layer of the thin film laminate 10 (including the portion covering the signal line) is entirely formed of a high dielectric constant ceramic, the influence on the signal quality is small, and the manufacturing cost can be reduced. Contribute. In FIG. 4, the first type terminal 5 a is directly connected to the first type electrode conductor thin film 14, and the second type terminal 5 b is connected to the second type electrode conductor thin film 17 via the auxiliary coupling conductor portion 19 ′. In FIG. 13, the first type terminal 5a is connected to the first type electrode conductor thin film 14 via the auxiliary coupling conductor portion 15 ', and the second type terminal 5b is connected to the second type electrode conductor thin film. 17 is directly connected to the structure.

  The capacitor 10 can be manufactured, for example, according to a process as shown in FIG. First, the above-mentioned substrate side is obtained by laminating and firing a known ceramic green sheet containing the raw material powder of the constituent ceramic of the substrate and a via hole formed by punching or laser drilling and filling a metal powder paste. A plate-like substrate 50 in which the coupling conductor portion 51 is formed as a laminated via is prepared. In each base-side coupling conductor portion 51, base-side terminals 7a, 7b, 7s (see FIG. 4) are formed in advance on the second main surface side of the plate-like base 50 by plating or the like.

  Next, as shown in step 1, the metal thin film 20 is formed on the first main surface of the plate-like substrate 50. Then, the process proceeds to step 2, and the formed metal thin film 20 separates the first-type electrode conductor thin film 14 and the second-type electrode conductor thin film 17 in a direct current manner. The problem is solved by etching using a lithography process. For example, when the metal thin film 20 is the second type electrode conductor thin film 17, the coupled conductor thin film portion (first coupled conductor thin film portion 15 a in Step 2 in FIG. 6) that is electrically connected to the first type electrode conductor thin film 14. The periphery is etched in a donut shape to form a through hole 18, and the metal thin film 20 remaining on the inside is used as a first coupled conductor thin film portion 15 a for the first-type electrode conductor thin film 14 (step A). In other words, the through-hole 18 is formed by etching in a donut shape, leaving the coupling conductor thin film portion 15a for electrical connection with the base-side coupling conductor portion. On the other hand, when the metal thin film 20 is the first type electrode conductor thin film 14, the through hole 16 is formed by etching the periphery of the coupled conductor thin film portion that will be electrically connected to the second type electrode conductor thin film 17 into a donut shape. The metal thin film 20 remaining on the inner side is used as a first coupled conductor thin film portion 19a for the second-type electrode conductor thin film 17 (step B). In other words, the through-hole 16 is formed by etching in a donut shape, leaving the coupled conductor thin film portion 19a for conducting with the electrode conductor thin film. In step 2 of FIG. 6, step A is performed.

  Then, it progresses to the process 3, and forms the dielectric thin film 13 so that the whole surface of the 2nd type electrode conductor thin film 17 (B process 1st type electrode conductor thin film 14) after completion | finish of an etching may be covered. When using the sol-gel method, for example, the following steps can be employed. First, when using an alkoxide as a raw material for a high dielectric constant oxide for forming a dielectric thin film, for example, barium titanate as a main dielectric material, titanium isopropoxide is dissolved in an alcohol-based organic solvent together with barium metal. At this time, barium metal reacts with an alcohol-based organic solvent and dissolves in the form of barium alkoxide. In addition, when adjusting strontium titanate or lead titanate for adjustment of dielectric constant characteristics, etc., strontium normal butoxide or lead acetate may be dissolved in the solution. In addition, as for the alcohol type organic solvent used as a solvent, it is desirable to use what has chelate formation property, for example, the mixed solvent of ethanol and acetylacetone, 2-ethoxyethanol, etc. In addition, in order to adjust the viscosity of the obtained solution, a small amount of water (equal to or less than that of the alcohol organic solvent) may be added to the solution, and each metal source may be appropriately polymerized. The solution obtained as described above is homogenized by heating or the like and then applied in a film form by a known application method such as a spin coating method. And after drying this, it baked at 500 degreeC or more and 1000 degrees C or less, and can obtain a crystalline high dielectric constant thin film. Note that sputtering or a CVD method may be used instead of the sol-gel method.

  At this time, the doughnut-shaped gap between the through hole 18 (the through hole 16 in the B process) and the first coupling conductor thin film portion 19a (the first coupling conductor thin film portion 15a in the B process) is a material of the dielectric thin film 13. The dielectric hole filling portion 13v is formed. At this time, the coupling conductor thin film portion 19a (15a) inside the dielectric hole filling portion 13v is once covered with the dielectric thin film 13, but is exposed by forming a through hole 13h by a photolithography process (as an etchant). For example, a hydrofluoric acid aqueous solution can be used). Moreover, in order to form the 1st coupling conductor thin film part 19a (The coupling conductor thin film part 15a in B process) for the 2nd kind electrode conductor thin film 17 (B process 1st class electrode conductor thin film 14), it respond | corresponds to this. A through hole 13h is also formed at the position. When the second-type electrode conductor thin film 17 (first-type electrode conductor thin film 14 in the process B) is the above-described distance conversion thin film LT, the formation position of the through hole 13h may be shifted in accordance with the distance change amount. .

  Then, as shown in step 4, a metal thin film 20 similar to that in step 1 is formed. The through-hole 13h formed in step 3 is filled with metal to form the second coupled conductor thin film portion 19b (15b), and the first coupled conductor thin film portion 19a (15a) inside the dielectric hole filling portion 13v The integrated conductor part 19 (15) is obtained. Thereafter, by returning to Step 2 and repeating the subsequent steps, as shown in Step 5, the first-type electrode conductor thin film 14 and the second-type electrode conductor thin film 17 can be sequentially stacked and formed in a DC separated form. (Step 4 repeats step A and step B alternately). In FIG. 4, after the formation of the first type electrode conductor thin film 14 and the second type electrode conductor thin film 17 is completed, the signal coupling conductor 22, the routing wiring portion 21, and the auxiliary dielectric layer 12 are connected. Layer formation is performed at once. Further, after the terminals 5s, 5b, and 5a are formed by plating or the like, the capacitor 1 is completed by forming the protective ceramic layer 11 that also serves as the solder resist layer using silicon dioxide or the like. In the manufacturing process described here, the electrode conductor thin film formed on the main surface of the substrate 52 is the second-type electrode conductor thin film 17, and the electrode conductor thin film that is insulated and opposed is the first-type electrode conductor thin film 14. However, there is no particular distinction between the first type and the second type. That is, the electrode conductor thin film formed on the main surface of the substrate 52 may be referred to as a first type electrode conductor thin film, and the electrode conductor thin film that is insulated and opposed may be referred to as a second type electrode conductor thin film.

  Note that, as in the capacitor (intermediate substrate) 200 shown in FIG. 14, the plate-like substrate has alternately a fired ceramic dielectric layer 52 and electrode conductor layers 54 and 57 fired simultaneously with the fired ceramic dielectric layer 52. It can also be configured as a laminated multilayer ceramic capacitor substrate 60. Such a multilayer ceramic capacitor substrate 60 can be manufactured using a ceramic green sheet similar to the plate-like substrate 50 of FIG. 4, and the electrode conductor layers 54 and 57 can be formed by printing and applying a metal paste. The electrode conductor layers 54 or 57 having the same polarity are connected in the stacking direction by base-side coupling conductor portions 55 and 59 forming vias, and the electrode conductor layers 54 and 57 and base-side coupling conductor portions 59 and 55 having different polarities are connected. They are separated from each other in a direct current manner by the through holes 56 and 58 formed in the electrode conductor layers 54 and 57 at the time of printing patterning of the metal paste.

  From the viewpoint of increasing the capacity, it is desirable that the dielectric layer 52 used in the multilayer ceramic capacitor 60 is composed of a high dielectric constant ceramic (the above-described perovskite oxide layer). On the other hand, when it is desired to positively set the capacitance on the monolithic ceramic capacitor 60 side in order to expand the band where low impedance is desired to the higher frequency side, the dielectric layer 52 used for the monolithic ceramic capacitor 60 is It can also be composed of a paraelectric ceramic such as alumina or glass ceramic.

Further, like the capacitor (intermediate substrate) 300 in FIG. 15, the electrode conductor layers 54 and 57 in the multilayer ceramic capacitor substrate 60 are connected to the upper and lower substrate-side coupling conductors in the same manner as the distance conversion thin film LT in the thin film laminate 10. A terminal interval conversion layer LT ′ having different connection positions of the portions 55 and 59 may be used, and the terminal interval conversion may be performed by the multilayer ceramic capacitor substrate 60. In FIG. 15, an interval converting thin film LT is also provided in the thin film laminate 10 to widen the arrangement interval of the coupling conductors 15 and 19 to an appropriate interval, and further, the terminal interval converting layer LT in the multilayer ceramic capacitor substrate 60. The terminal interval conversion is performed in two stages by increasing the arrangement interval of the base-side coupling conductor portions 59 and 55 by '. Further, even in the case of using a plate-like base body 50 ′ that does not incorporate a capacitor, such as the capacitor 400 shown in FIG. , 51b (upper substrate-side coupling conductors 51a ₁ , 51b ₁ , lower substrate-side coupling conductors 51a ₀ , 51b ₀ ) may be provided with a lead wiring part 53 to perform terminal interval conversion. It is. The plate-like substrate 50 ′ is a so-called wiring substrate (package substrate). In FIG. 16, the arrangement interval of the first terminal coupling conductor portion 15 and the second terminal coupling conductor portion 19 on the second main surface of the thin film laminate 10 is the first type substrate on the second main surface of the plate-like substrate 50 ′. It is smaller than the arrangement interval of the side coupling conductor portion 51a and the second type substrate side coupling conductor portion 51b.

  Although the manufacturing method of the capacitor | condenser 1,1A, 1B, 1C, 1D, 1E, 200,300,400 of this invention was demonstrated in FIG. 6, the manufacturing method of an aspect different from it is demonstrated below. That is, FIGS. 17 to 19 are process explanatory views showing a second embodiment of the capacitor manufacturing method according to the present invention. First, the plate-like substrate 50 in which the first-type substrate-side coupling conductor portion 51a and the second-type substrate-side coupling conductor portion 51b are exposed on the first main surface CP is produced. The manufacturing method of the plate-like substrate 50 is as already described.

  First, as shown in the first explanatory view from the top of FIG. 17, a resist is applied to the plate-like substrate 50 so that the first-type substrate-side coupled conductor portion 51 a exposed on the first main surface CP of the plate-like substrate 50 is covered. 70 is patterned so that the side surface is inversely tapered. The thickness of the resist 70 is adjusted to, for example, 1 μm or more and 5 μm or less. Next, as shown in the second explanatory view from the top in FIG. 17, a first-type electrode conductor thin film 71 that covers the first main surface CP of the plate-like substrate 50 and the resist 70 is formed by a method such as sputtering. The thickness and the like of the first type electrode conductor thin film 71 are as already described with reference to FIG. Here, the first-type electrode conductor thin film 71 is extremely thin, and the thickness of the resist 70 is adjusted to be larger than the thickness of the first-type electrode conductor thin film 71.

  After forming the first kind electrode conductor thin film 71, the resist 70 is brought into contact with a stripping solution. At this time, the stripping solution permeates from the side of the resist 70 and the first-type electrode conductor thin film 71 on the resist 70 is removed together with the resist 70. Such a technique is called a lift-off process. According to the lift-off process, since the conductive thin film itself is not etched, there are advantages that it is simple and low cost and does not depend on the material to be patterned. When producing a thin film capacitor that does not require as fine patterning as LSI, it is preferable to employ a lift-off process with excellent productivity.

  Of course, a so-called etch back process may be employed as the photolithography technique. That is, after forming the first type electrode conductor thin film 71 so as to cover the entire first main surface CP of the plate-like substrate 50, the resist is patterned to partially etch the first type electrode conductor thin film 71, etc. The second-type substrate-side coupling conductor portion 51b may be exposed by this method. By performing the above operation, as shown in the third explanatory view from the top of FIG. 17, the first-type electrode conductor thin film 71 having the first through-hole 71p for exposing the second-type substrate-side coupling conductor portion 51b. Is formed on the first main surface CP of the plate-like substrate 50. The first through hole 71p is larger in diameter than the second type substrate-side coupling conductor portion 51b, and is provided in a positional relationship such that the exposed surface of the second type substrate-side coupling conductor portion 51b is accommodated in the inner region. By such first through-holes 71p, the first type electrode conductor thin film 71 is separated from the second type substrate-side coupling conductor portion 51b in a direct current manner.

Next, as shown in the fourth explanatory view from the top of FIG. 17, the main surface of the first type electrode conductor thin film 71 and the portion exposed to the inside of the first through hole 71 p provided in the first type electrode conductor thin film 71. The first dielectric thin film 72 is formed so as to be covered. At this time, the second-type substrate-side coupling conductor portion 51b remains covered with the first dielectric thin film 72. Next, as shown in the first explanatory view from the top of FIG. 18, a through-hole 72 p is provided in the first dielectric thin film 72. By providing the through hole 72p, the second-type substrate-side coupling conductor portion 51b is exposed. The through hole 72p can be formed by patterning the first dielectric thin film 72 by dry etching or chemical etching. Further, since the through hole 72p has substantially the same diameter as the second type substrate-side coupling conductor portion 51b, the first type electrode conductor thin film 71 and the first through hole 71p provided in the first type electrode conductor thin film 71 The peripheral surface remains covered with the first dielectric thin film 72. As described above, the steps described from FIG. 17 to FIG. 18 cover the main surface of the first type electrode conductor thin film 71 and the inner peripheral surface of the first through hole 71p provided in the first type electrode conductor thin film 71. In this step, the first dielectric thin film 72 is formed. Note that the method described above can be employed as the method for forming the dielectric thin film.

  Next, as shown in the second explanatory view from the top of FIG. 18, the second-type substrate-side coupling conductor portion 51b is formed through the through-hole 72p (cut of the dielectric thin film 72) formed in the first dielectric thin film 72. A second-type electrode conductor thin film 73 is formed which is conductive and separated from the first-type base-side coupled conductor portion 51a in a direct current manner. However, the resist 74 is patterned on the main surface of the first dielectric thin film 72 prior to forming the second-type electrode conductive thin film 73. This resist 74 is for forming the second through-hole 73p in the second-type electrode conductor thin film 73 as shown in the third explanatory view from the top in FIG. As described above, the lift-off process in which the resist is formed before the material to be patterned (here, the second-type electrode conductor thin film 73) has already been described with reference to FIG.

  When the resist 74 is removed with a stripping solution, the second type electrode conductor thin film 73 is partially removed together with the resist 74, thereby forming a second through hole 73 p in the second type electrode conductor thin film 73. The second through hole 73p may be formed so as to have a very shallow cylindrical shape. Since the second through hole 73p is a hole that communicates with the first dielectric thin film 72, the first dielectric thin film 72 is exposed in the second through hole 73p. Further, the second through hole 73p has a surface in which the inner region HL when the second through hole 73p is projected in the stacking direction is adjacent to the first type electrode conductor thin film 71 adjacent to the lower side of the first dielectric thin film 72. Are formed so as to have an overlap. Precisely, the entire inner region HL of the second through-hole 73p is in a positional relationship where it overlaps with the first-type electrode conductor thin film 71.

  Next, as shown in the fourth explanatory view from the top in FIG. 18, the first dielectric thin film 72 is integrated in the inner region HL of the second through-hole 73p, and the second-type electrode conductor thin film 73 and the A second dielectric thin film 75 that covers the inner peripheral surface of the second through hole 73p provided in the second type electrode conductor thin film 73 is formed. However, if the second dielectric thin film 75 is formed by sputtering or spin coating, the second dielectric thin film 75 is naturally formed in the second through hole 73p. No special operation for integrating the thin film 72 and the second dielectric thin film 75 is required. The integrated first dielectric thin film 72 and second dielectric thin film 75 constitute a dielectric hole filling portion 76k.

  Next, as shown in the first explanatory view from the top of FIG. 19, the first dielectric thin film 72 integrated in the inner region HL of the second through hole 73 p provided in the second type electrode conductor thin film 73 and the first A dielectric thin film side through-hole 76p that penetrates the dielectric hole filling portion 76k made of the second dielectric thin film 75 in a donut shape and communicates with the first-type electrode conductor thin film 71 is provided. However, the inner peripheral surface of the second through hole 73p is still covered with the dielectric hole filling portion 76k having a donut shape. The dielectric thin film side through hole 76p is for exposing the first type electrode conductor thin film 71. As shown in the second explanatory diagram from the top of FIG. 19, if a metal having an appropriate thickness is sputtered / deposited, the coupling conductor portion in the dielectric thin film side through hole 76p or the inner region HL of the second through hole 73p. At 77k, an upper-layer first-type electrode conductor thin film 77 that conducts with the lower-layer first-type electrode conductor thin film 71 is laminated.

  Thus, the coupling conductor portion 77k that couples the first-type electrode conductor thin films 71 and 77 having the same polarity (for example, power source) and the second-type electrode conductor thin film 73 having a different polarity (for example, ground) from them. A dielectric hole filling portion 76k formed by integrating the first dielectric thin film 72 and the second dielectric thin film 75 is interposed therebetween. The dielectric hole filling portion 76k surrounds the coupling conductor portion 77k over the entire circumferential direction in the inner region HL of the second through-hole 73p of the second type electrode conductor thin film 73, whereby the coupling conductor portion 77k. Are separated from the inner peripheral surface of the second through-hole 73p of the second-type electrode conductor thin film 73 in a direct current manner.

  In the present embodiment, the dielectric thin film side through hole 76p has a smaller diameter than the second through hole 73p of the second type electrode conductor thin film 73. Moreover, both the through holes 73p and 76p are arranged coaxially. Therefore, even after the dielectric thin film side through hole 76p is formed, the state in which the dielectric hole filling portion 76k covers the inner peripheral surface of the second through hole 73p is maintained. According to such a method, it is possible to reliably separate the first-type electrode conductor thin films 71 and 77 and the second-type electrode conductor thin film 73 from each other in a direct current manner, and it is very easy to connect the electrode conductor thin films having the same polarity. Can be done.

  In addition, the axial line of the second through hole 73p is in a positional relationship shifted in the in-plane direction with respect to the axial line of the first-type substrate-side coupling conductor portion 51a. That is, while maintaining a direct current separation state between the electrode conductor thin film having the polarity of the power supply and the electrode conductor thin film having the polarity of the ground, the terminal interval of the base-side terminal array 7 is set to the terminals of the thin-film laminate-side terminal array 5. The main part of the structure (what is called a fanout structure) for adjusting to a space | interval is shown. These points are as described above.

  Further, as shown in the third explanatory view from the top of FIG. 19, the third dielectric thin film 78 is formed on the first-type electrode conductor thin film 77 by using the steps described so far. The third dielectric thin film 78 is integrated with the second dielectric thin film 75 below through the through-hole 77p provided in the first kind electrode conductor thin film 77 to form a dielectric hole filling portion 78k. Then, as shown in the fourth explanatory diagram from the top of FIG. 19, in the same manner as described above, the dielectric thin film side through-hole 78p is formed through the center of the dielectric hole filling portion 78k, The upper and lower second-type electrode conductor thin films 73 and 79 are connected to each other through the dielectric thin film side through hole 78p. Thus, the step of laminating and patterning the electrode conductor thin films 71 and 77 on the power source side, the step of laminating and patterning the dielectric thin films 72, 75 and 78, and the layering and patterning of the electrode conductor thin films 73 and 79 on the ground side. The process to perform is repeated in order. Then, after the lamination of the electrode conductor thin film and the dielectric thin film is completed, the signal coupling conductor 22, the routing wiring portion 21, and the auxiliary dielectric layer 12 are collectively formed. Furthermore, after forming the terminals 5s, 5b, and 5a by plating or the like, the protective layer 11 that also serves as a solder resist layer is formed using silicon dioxide or the like, whereby the capacitor according to the present invention is completed.

  In addition, in the capacitor manufactured by adopting the manufacturing method of FIGS. 17 to 19, as shown in the fourth explanatory view from the top of FIG. 19, the portions connecting the upper and lower electrode conductor thin films are somewhat in a bowl shape. It will have a concave shape. However, since the thickness of the electrode conductor thin film and the thickness of the dielectric thin film are about 1 μm or less, in practice, there is not so much unevenness. In addition, as a method for forming the dielectric thin film, a method capable of forming a film while eliminating irregularities on the surface of the film, such as a spin coating method, can be appropriately selected.

  Next, FIG. 20 to FIG. 22 are process explanatory views showing a third embodiment of the capacitor manufacturing method according to the present invention. Since the description of each process can mostly be used for the description of the second embodiment, the description will focus on the differences. First, as shown in the first explanatory view from the top of FIG. 20, a resist 81 is patterned in a donut shape around the second-type substrate-side coupling conductor portion 51b exposed on the first main surface CP of the plate-like substrate 50. . Then, as shown in the second and third explanatory diagrams from the top of FIG. 20, after depositing the metal by a method such as sputtering, the resist 81 is removed to thereby provide a first type electrode having a ring-shaped through hole 82p. A conductive thin film 82 is formed. An electrode conductor thin film portion 83 is formed adjacent to and directly above the second type substrate side coupling conductor portion 51b. This electrode conductor thin film portion 83 is separated from the first type electrode conductor thin film portion 82 in a direct current manner. ing. Thus, by forming the electrode conductor thin film portion 83, it is possible to prevent the unevenness from increasing as the plurality of electrode conductor thin films and the plurality of dielectric thin films are laminated. This is the same as the first embodiment described in FIG.

  Next, as shown in the fourth explanatory view from the top of FIG. 20, a first dielectric thin film 84 is formed. Since the inner peripheral surface of the donut-shaped through hole 82p is covered with the first dielectric thin film 84, the first-type electrode conductor thin film portion 82 and the second-type substrate-side coupling conductor portion 51b are surely connected. Separated. Next, as shown in the first explanatory view from the top of FIG. 21, a part of the first dielectric thin film 84 is so exposed that the electrode conductor thin film portion 83 covering the second-type substrate-side coupling conductor portion 51b is exposed. Are removed by photolithography. At this time, a through hole 84p for exposing a part of the first type electrode conductor thin film portion 82 is also formed.

  Next, as shown in the second explanatory view from the top of FIG. 21, a resist 85 is patterned in a donut shape on the opening peripheral edge of the through hole 84p formed in the first dielectric thin film 84, and the second type electrode conductor thin film A portion 86 is formed. Then, as shown in the third explanatory view from the top of FIG. 21, by removing the resist 84, the second-type electrode conductor thin film portion 86 is coupled to the first-type electrode conductor thin film portion 82 at the center. A donut-shaped through hole 86p is formed in a form in which the portion 87k is located. The second-type electrode conductor thin film portion 86 is electrically connected to the second-type substrate-side coupled conductor portion 51b through the electrode conductor thin film portion 83. That is, the electrode conductor thin film portion 83 functions as a coupling conductor portion that connects the second type substrate-side coupling conductor portion 51 b and the second type electrode conductor thin film portion 86.

  Then, as shown in the fourth explanatory diagram from the top in FIG. 21, by forming the second dielectric thin film 89, the first dielectric thin film 84 and the second dielectric thin film are formed in the donut-shaped through hole 86p. The dielectric thin film 89 is integrated to form a dielectric hole filling portion 89k. The dielectric hole filling portion 89k is interposed between the coupling conductor portion 87k formed adjacent to the first type electrode conductor thin film portion 82 and the inner peripheral surface of the through hole 86p of the second type electrode conductor thin film portion 86. is doing. As a result, the first-type electrode conductor thin film portion 82 and the second-type electrode conductor thin film portion 86 are separated in a direct current manner. And as shown in FIG. 22, the same procedure is repeated and the lamination process of an electrode conductor thin film and a dielectric thin film is complete | finished.

  As mentioned above, although several embodiment of the capacitor | condenser and several embodiment of the manufacturing method of the capacitor | condenser were shown in this specification, it mentions that description of each embodiment can mutually be used. . Further, it goes without saying that various embodiments can be combined in various ways without departing from the scope of the invention.

The side surface schematic diagram which shows an example which comprised the capacitor | condenser of this invention as an intermediate | middle board | substrate. The equivalent circuit diagram which shows an example of the usage condition of the decoupling capacitor for integrated circuits. The top view and side cross-sectional schematic diagram which take out and show the capacitor | condenser of this invention of FIG. Sectional drawing which shows the detailed structure of the capacitor | condenser of FIG. The schematic diagram which illustrates and illustrates the planar form of an electrode conductor thin film. Process explanatory drawing which shows an example of the manufacturing method of the capacitor | condenser of FIG. Sectional drawing which shows the 1st modification of the capacitor | condenser of FIG. Sectional drawing which similarly shows a 2nd modification. Sectional drawing which shows a 3rd modification similarly. Sectional drawing which shows a 4th modification similarly. Sectional drawing which shows a 5th modification similarly. The top view and side surface schematic diagram which show a 6th modification similarly. The principal part expanded sectional schematic diagram of FIG. Sectional drawing which shows the 7th modification of the capacitor | condenser of FIG. Sectional drawing which similarly shows the 8th modification. Sectional drawing which shows a 9th modification similarly. Process explanatory drawing which shows the 2nd Example of the manufacturing method of the capacitor | condenser concerning this invention. Process explanatory drawing following FIG. Process explanatory drawing following FIG. Process explanatory drawing which shows the 3rd Example of the manufacturing method of the capacitor | condenser concerning this invention. Process explanatory drawing following FIG. Process explanatory drawing following FIG.

Explanation of symbols

1, 1A, 1B, 1C, 1D, 1E, 200, 300, 400 Capacitor (intermediate substrate)
5 thin film laminate side terminal array 5a first type terminal 5b second type terminal 5s signal terminal 7 base side terminal array 7a first type base side terminal 7b second type base side terminal 7s signal base side terminal 10 thin film stack 12 Auxiliary dielectric layer 13 Dielectric thin film 13h Through hole 13v, 76k, 78k, 89k Dielectric hole filling portion 14, 71, 77 First type electrode conductor thin film 15, 19, 77k, 87k Coupling conductor portion 15 ', 15'',19' Auxiliary coupling conductor portion 17, 73, 79, 86 Second-type electrode conductor thin film 16, 18 Through hole 22 Signal coupling conductor portion 50 Plate-like substrate 51a First-type substrate-side coupling conductor portion 51b Second-type substrate Side coupling conductor portion 51s Signal substrate side coupling conductor portion 52 Sintered ceramic dielectric layer 54, 57 Electrode conductor layer LT Thin film for interval conversion

Claims (20)

A first type having a thin film laminate in which a plurality of dielectric thin films and a plurality of electrode conductor thin films forming a capacitor are alternately laminated, and separated from each other in a direct current manner on the first main surface of the thin film laminate A terminal and a second type terminal are formed,
The electrode conductor thin film is laminated in such a manner that a first type electrode conductor thin film conducting to the first type terminal and a second type electrode conductor thin film conducting to the second type terminal are separated by the dielectric thin film. The first dielectric thin film, the other kind of electrode conductor thin film, and the second dielectric between the same kind of electrode conductor thin film and the other of the same kind of electrode conductor thin film adjacent to each other in the stacking direction. The body thin film is arranged in this order,
The first through hole formed in the first dielectric thin film and the second through hole formed in the other-type electrode conductor thin film have an overlap by in-plane projection, and the second through hole and the The third through hole formed in the second dielectric thin film has an overlap by in-plane projection,
The two same-type electrode conductor thin films are formed in such a manner that a coupling conductor portion that connects the one same-type electrode conductor thin film and the other same-type electrode conductor thin film fills the first through-hole and the third through-hole, respectively. And a dielectric hole filling portion integrated with the first dielectric thin film and the second dielectric thin film in the second through hole. The capacitor is characterized in that the outer peripheral surface of the coupling conductor portion and the inner peripheral surface of the second through hole are separated in a direct current manner.   The capacitor according to claim 1, wherein the through hole is formed by photolithography on the electrode conductor thin film and the dielectric thin film.   The capacitor according to claim 1 or 2, wherein a thickness of the dielectric thin film is 10 nm or more and 1000 nm or less.   For each of the electrode conductor thin films, a plurality of the coupling conductor portions that are electrically connected to the electrode conductor thin film are formed on the same main surface side, and the plurality of coupling conductor portions are different and closest to each other The capacitor according to claim 3, wherein an interval between edges is 20 μm or more and 300 μm or less. A plurality of the first type terminals and the second type terminals are respectively arranged at predetermined intervals on the first main surface of the thin film laminate, and the first type terminals and the second type terminals are, For the first-type electrode conductor thin film and the second-type electrode conductor thin film closest to the first main surface, each bonded directly or via an auxiliary coupling conductor portion in the stacking direction,
On the first main surface of the thin film laminate, a terminal array in which the plurality of first-type terminals and second-type terminals are mixed is formed, and between adjacent edges of the adjacent terminals in the terminal array. The capacitor according to claim 4, wherein the interval is 20 μm or more and 300 μm or less.   The electrode conductor thin film and the coupling conductor portion are formed by a vapor deposition method, and the dielectric thin film and the dielectric hole filling portion are formed by a vapor deposition method or a chemical solution deposition method. The capacitor according to any one of claims 1 to 5.   The capacitor according to any one of claims 1 to 6, wherein the dielectric thin film and the dielectric hole filling portion are formed of a high dielectric constant ceramic.   The capacitor according to claim 7, wherein the high dielectric constant ceramic comprises one or more of barium titanate, strontium titanate, and lead titanate.   The second main surface of the thin film laminate is bonded to the first main surface of the plate-like substrate, and the first type substrate-side terminal and the second type separated from each other in a direct current manner on the second main surface of the plate-like substrate. A base-side terminal is formed, and the first-type base-side terminal and the second-type base-side terminal are connected to the thin film laminate through a base-side coupling conductor portion that penetrates the plate-like base in the thickness direction. The capacitor according to any one of claims 1 to 8, wherein the capacitor is connected to the first-type electrode conductor thin film and the second-type electrode conductor thin film closest to the second main surface. On the first main surface of the thin film laminate, a thin film laminate side terminal array in which a plurality of the first type terminals and a plurality of the second type terminals are mixed is formed,
A base-side terminal array in which a plurality of the first-type base-side terminals and a plurality of the second-type base-side terminals are mixed is formed on the second main surface of the plate-like base,
The capacitor according to claim 9, wherein a terminal arrangement interval of the substrate-side terminal array is set wider than a terminal arrangement interval of the thin film laminate-side terminal array. In the thin film laminate side terminal array on the thin film laminate, the first type terminal and the second type terminal are the first type electrode conductor thin film and the second type electrode conductor thin film closest to the first main surface. On the other hand, it is coupled in the stacking direction directly or via an auxiliary coupling conductor part,
On the first main surface of the plate-like substrate, a first-type substrate-side coupling conductor portion conducting to the first-type substrate-side terminal, and a second-type substrate-side coupling conductor portion conducting to the second-type substrate-side terminal; Are arranged at a larger interval than the terminal interval of the thin film laminate-side terminal array, and each of the first type electrode thin film conductor and the first electrode closest to the second main surface of the thin film laminate, respectively. The capacitor according to claim 10, wherein the capacitor is coupled to the two-electrode thin film conductor in the stacking direction directly or via an auxiliary coupling conductor portion.   In the thin film laminate, at least one layer of the electrode conductor thin film is connected to the electrode conductor thin film from the thin film laminate side terminal array side at the first array interval, while the base conductor side terminal array side is connected. The capacitor according to claim 10 or 11, wherein the thin film for distance conversion is formed such that the coupling conductor portion is connected to the electrode conductor thin film at a second arrangement interval wider than the first arrangement interval.   13. The capacitor according to claim 12, wherein in the thin film laminate, at least one layer of the first-type electrode conductor thin film and at least one layer of the second-type electrode conductor thin film are respectively used as the interval conversion thin film.   The first-type electrode conductor thin film and the second-type electrode conductor thin film are the same type of electrode conductor thin film closest to the gap converting thin film on the thin film laminate side terminal array side as the pre-conversion thin film, and also on the base side When the same type of electrode conductor thin film closest to the terminal array side is defined as a thin film after conversion, between the thin film before conversion and the thin film for interval conversion, and between the thin film for interval conversion and the thin film after conversion In addition, the coupling positions of the coupling conductor portions coincide with each other in the in-plane direction, and between the pre-conversion thin film and the interval conversion thin film, and the interval conversion thin film and the post-conversion thin film. The capacitor according to claim 13, wherein the second through holes for passing the coupling conductor portion are formed in a positional relationship shifted from each other in the other types of electrode conductor thin films positioned between each other.   The second main surface of the thin film laminate is bonded to the first main surface of the plate-like substrate, and the first type substrate-side terminal and the second type separated from each other in a direct current manner on the second main surface of the plate-like substrate. The first-type electrode conductor thin film and the second-type electrode closest to the second main surface of the thin-film laminate are formed with a base-side terminal. The capacitor according to any one of claims 1 to 8, wherein the capacitor is connected to each conductor thin film. The first through hole and the third through hole are located within an inner region determined by projecting the second through hole in the stacking direction;
By forming the first dielectric thin film into a form that sinks into the second through hole, the height position of the first through hole in the stacking direction is substantially equal to the second through hole. The capacitor according to any one of claims 1 to 15, wherein the capacitor is adjusted to a vertical position or a height position pulled down toward the plate-like substrate with respect to the second through hole. A first type having a thin film laminate in which a plurality of dielectric thin films and a plurality of electrode conductor thin films forming a capacitor are alternately laminated, and separated from each other in a direct current manner on the first main surface of the thin film laminate A terminal and a second type terminal are formed,
The electrode conductor thin film is laminated in such a manner that a first type electrode conductor thin film conducting to the first type terminal and a second type electrode conductor thin film conducting to the second type terminal are separated by the dielectric thin film. The first dielectric thin film, the other kind of electrode conductor thin film, and the second dielectric between the same kind of electrode conductor thin film and the other of the same kind of electrode conductor thin film adjacent to each other in the stacking direction. The body thin film is arranged in this order,
A coupling conductor in which the one same-type electrode conductor thin film and the other same-type electrode conductor thin film are coupled to an inner region defined by projecting through holes formed in the other-type electrode conductor thin film in the stacking direction. Part is located,
Between the coupling conductor portion and the other-type electrode conductor thin film, a dielectric hole filling portion formed by integrating the first dielectric thin film and the second dielectric thin film is interposed,
The dielectric hole filling portion surrounds the coupling conductor portion in the inner region of the through hole, whereby the outer circumferential surface of the coupling conductor portion and the inner circumferential surface of the through hole of the other electrode conductor thin film Is a capacitor separated from each other in a direct current manner. A substrate manufacturing step for manufacturing a plate-like substrate in which the first-type substrate-side coupling conductor portion and the second-type substrate-side coupling conductor portion separated from each other in a direct current are exposed on the first main surface; A thin film laminate forming step in which a thin film laminate in which dielectric thin films and a plurality of electrode conductor thin films are alternately laminated is formed on the plate-like substrate, the thin film laminate forming step,
a. Forming on the first main surface of the plate-like substrate a first-type electrode conductor thin film that is electrically connected to the first-type substrate-side coupling conductor and is DC-isolated from the second-type substrate-side coupling conductor. And a process of
b. Forming a first dielectric thin film covering the first-type electrode conductor thin film;
c. A cut is formed in the first dielectric thin film, and the second type separated from the first type substrate side coupling conductor portion in a DC manner while being electrically connected to the second type substrate side coupling conductor portion at the cut. Forming an electrode conductor thin film and providing a through hole in the second type electrode conductor thin film for exposing the first dielectric thin film; and
d. The second type electrode conductor thin film and the second type electrode conductor thin film are integrated with the first dielectric thin film in an inner region determined by projecting the through hole provided in the second type electrode conductor thin film in the stacking direction. Forming a second dielectric thin film covering the inner peripheral surface of the through hole provided in the seed electrode conductor thin film;
e. Forming a slit in the second dielectric thin film, and forming an electrode conductor thin film that is electrically connected to the first type electrode conductor thin film at the cut and separated from the second type electrode conductor thin film in a direct current manner; ,
A method for producing a capacitor, comprising: Step a. Is a step of forming the first-type electrode conductor thin film having a first through hole for exposing the second-type substrate-side coupling conductor portion,
Step b. Is a step of forming the first dielectric thin film so that the surface of the first type electrode conductor thin film and the inner peripheral surface of the first through hole provided in the first type electrode conductor thin film are covered. The method for manufacturing a capacitor according to claim 18. Step d. Is
Forming the second dielectric thin film so that the surface of the second type electrode conductor thin film and the inner peripheral surface of the through hole provided in the second type electrode conductor thin film are covered;
A portion of the dielectric hole filling portion made of the first dielectric thin film and the second dielectric thin film integrated in the inner region of the through hole provided in the second type electrode conductor thin film, Dielectric thin film side penetration that penetrates the first type electrode conductor thin film while maintaining the state where the inner peripheral surface of the through hole of the second type electrode conductor thin film is covered by the filling portion in the dielectric hole. Providing a hole,
Said step e. Is
The step of forming the electrode conductor thin film DC-separated from the second type electrode conductor thin film so as to directly contact the first type electrode conductor thin film exposed in the dielectric thin film side through-hole. Item 20. A method for manufacturing a capacitor according to Item 18 or Item 19.

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