JP2005026491A - Method for manufacturing wiring board - Google Patents

Method for manufacturing wiring board Download PDF

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Publication number
JP2005026491A
JP2005026491A JP2003190865A JP2003190865A JP2005026491A JP 2005026491 A JP2005026491 A JP 2005026491A JP 2003190865 A JP2003190865 A JP 2003190865A JP 2003190865 A JP2003190865 A JP 2003190865A JP 2005026491 A JP2005026491 A JP 2005026491A
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JP
Japan
Prior art keywords
wiring
copper foil
wiring pattern
layer
wiring board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
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JP2003190865A
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Japanese (ja)
Inventor
Koji Kamoto
浩二 加本
Toru Saito
徹 斉藤
Satoshi Nakao
敏 中尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yamaichi Electronics Co Ltd
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Yamaichi Electronics Co Ltd
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Filing date
Publication date
Application filed by Yamaichi Electronics Co Ltd filed Critical Yamaichi Electronics Co Ltd
Priority to JP2003190865A priority Critical patent/JP2005026491A/en
Publication of JP2005026491A publication Critical patent/JP2005026491A/en
Pending legal-status Critical Current

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Abstract

<P>PROBLEM TO BE SOLVED: To obtain a highly reliable and compact wiring board with a projecting bump with a high yield. <P>SOLUTION: A wiring material plate 11 having a copper foil 9 adhered to one main surface and a wiring pattern 8 adhered to the other main surface of an insulator layer 10 with the foil 9 and the pattern 8 electrically connected by a conductor 12 which penetrates through the insulator layer 10 is manufactured. A plating resist layer 12 is provided on the surface of the pattern 8 of the plate 11 by providing an opening part 12a for forming a predetermined connecting bump. A connecting bump 14 is grown at the opening part 12a of the layer 12 by processing an electrolytic plating with the foil 9 of the plate 11 as a power supplying body. A wiring pattern 16 is formed by removing the layer 12 and etching by providing an etching resist layer 15 on the pattern 8 formed surface and the foil 9 surface. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【0001】
【発明の属する技術分野】
本発明は、配線基板の製造方法に係り、さらに詳しくは実装に供されるバンプ付き配線基板の製造方法に関する。
【0002】
【従来の技術】
電子機器類の短小軽薄化などに伴って、電気回路を形成する配線基板についても、高密度配線化や短小軽薄化だけでなく高信頼性さが要求されている。このような要求に対応して、多層型配線基板が開発されている。例えばポリイミド樹脂等を層間絶縁体とし、配線パターン層を内装させる一方、主面の配線パターン面に電子部品の端子を接続するための突起状バンプを形設、具備させた構成の多層型配線基板が実用されている。なお、この多層型配線基板の各配線パターン層間は、それぞれ介挿する層間絶縁体を貫挿する導体で電気的に接続されている。
【0003】
そして、この種の多層型配線基板は、一般的に、次のような手段で製造されている。先ず、ポリイミド樹脂フイルム等の両主面に、接着剤層を介して銅箔を貼り合わせた銅箔貼りシートを用意する。次いで、この銅箔貼りシートの所定領域に穿孔加工を施し、層間接続用のビア貫通孔を設けた後、貫通孔内壁面をメッキ導体化するか、あるいは導電性組成物を充填して層間接続導体を形成、配置する。その後、両面の銅箔にフォトエッチング処理を施して配線パターンを形成し、配線パターン間が接続された配線基板とする。そして、3層以上の多層配線基板は、上記に準じた工程の繰り返しで製造している(特許文献1)。
【0004】
なお、上記層間接続の構成を簡略する手段として、次のような構成も知られている。すなわち、第1の銅箔の所定領域面に、導電性組成物や導電性金属などを素材とした突起状導電体(山形バンプ)を形設する。次いで、前記銅箔の突起状導電体の形設面に、熱可塑性樹脂層、及び第2の銅箔を順次積層、配置する。その後、この積層体を加熱、加圧して接合一体化して、両面銅箔が熱可塑性樹脂層を貫挿した突起状導電体で電気的に接続した両面銅箔貼り板を製作し、この両面銅箔貼り板の両面銅箔をエッチング処理して配線パターン化する(特許文献1)。
【0005】
上記製造した配線基板は、電子回路のコンパクト化などのため、実装回路装置に使用されている。そして、実装回路装置化に当たっては、少なくとも一主面の配線パターン形成面に、例えばベアチップ、BGA(ボールグリッドアレイ)、CSP(チップサイズパッケージ)、抵抗チップなどの電子部品を位置決め、搭載配置し、リフロー処理などによって半田を溶融させ、実装電子部品の実装、接続を行う必要がある。つまり、搭載、実装する電子部品の端子バンプに対応させ、予め、ニッケルなどを素材とした接続用の突起状バンプを搭載、実装部の配線パターン面に形成しておき、この突起状バンプに端子バンプを位置合わせし、互いに絶縁離隔した状態での電気的な接続を確保する。一方、バンプ同士の接続部にかかる微小応力の低減化、外部の湿度や衝撃から実装電子部品を保護するため、被実装面間にアンダーフィル材と呼称される液状材料の注入、充填が行われる(特許文献2)。
【0006】
ところで、上記配線基板面の突起状バンプの形成は、通常、次のような手段で行われている。例えば図2に平面的に示すように、突起状バンプ(接続用バンプ)1a,1b,1c,1d,1eを形設する配線パターン2を基板周縁部まで給電部3として延設しておき、図3(a),(b),(c),(d)に模式的に示すような工程順で電解メッキ処理を施して突起状バンプ1a,1b,1c,(1d,1e略)を肉盛、成長させている。
【0007】
すなわち、図3(a)に要部を断面的に示すように、絶縁体層4の両主面に貫挿する導電バンプ5で接続された配線パターン2を配設して成る配線素板6を用意し、最終的な外形加工で切断分離する線c外を除いて両配線パターン2配設面にメッキレジスト層7を設ける。ここで、メッキレジスト層7は、図3(b)に要部を断面的に示すように、配線パターン2のうち突起状バンプ1a,1b,・・・を形設する領域が選択的に開口(7a)処理されている。
【0008】
次いで、前記メッキレジスト層7を設けた配線素板6は、硫酸ニッケルなどを主要成分とする電解ニッケルメッキ液に浸漬され、不溶性の対極と給電部3との間に電圧を印加して、図3(c)に要部を断面的に示すように、ニッケル系の突起状バンプ1a,1b,・・・を成長、形成する。その後、メッキレジスト層7を除去する一方、外形加工(切断分離線c)を施すことによって、図3(d)に要部を断面的に示すような突起状バンプ1a,1b,・・・付き配線基板を得ている。なお、配線パターン層同士の接続手段として、片面に銅箔付きの絶縁層に予め穿孔し、前記銅箔を一方の電気メッキ電極に利用し、穿孔内をメッキ金属で充填することも知られている。
【0009】
【特許文献1】
特開平8−264939号公報([0003][0010]参照)
【0010】
【特許文献2】
特開平11−307586号公報([0002][0005][0010][0014]参照)
【0011】
【発明が解決しようとする課題】
しかし、上記配線基板の製造工程は、次のような不都合がある。すなわち、電子部品を搭載、実装するための突起状バンプ1a,1b,1c,1dを電解メッキで肉盛、成長させるに当たっては、同一平面に対応する給電部3を延設している。このように、同一主面で給電部3を周縁部に延設することは、配線パターニングが煩雑化するだけでなく、主面における配線パターン形成領域の制約となって、配線の高密度化乃至コンパクト化を阻害する。
【0012】
また、突起状バンプ1a,1b,・・・に対応する各給電部3によって、それぞれ電解メッキを進める際、一様な電解メッキの成長を行うため、各給電部3に一定、一様の電圧を印加することも実際的に困難であり、電解メッキのバラツキを生じる恐れがある。つまり、全体的に所定寸法、形状の突起状バンプ1a,1b,・・・の形成が困難で、信頼性の低下や不良品の発生も懸念され、歩留まりや生産性の点で実用上問題がある。
【0013】
本発明は、上記事情に対処してなされたもので、信頼性が高くて、よりコンパクト化が図られた突起状バンプ付き配線基板を歩留まりよく得ることができる製造方法の提供を目的とする。
【0014】
【課題を解決するための手段】
本発明は、層間絶縁体層の一主面に銅箔が貼着され他主面に配線パターンを有し、かつ銅箔及び配線パターンが前記層間絶縁体層を貫挿する導体で電気的に接続された配線素板を製造する工程と、
前記配線素板の配線パターン面に所要の接続バンプ形成部を開口してメッキレジスト層を設ける工程と、
前記配線素板の銅箔を共通の給電部として前記層間絶縁体層を貫挿する導体を介して前記配線パターンに電解メッキ処理を施してメッキレジスト層の開口部に接続バンプを成長させる工程と、
前記メッキレジスト層を除去し、配線パターン形成面及び銅箔面にエッチングレジスト層を設けエッチング処理して銅箔を配線パターンニングする工程と、
を有することを特徴とする配線基板の製造方法にある。
【0015】
すなわち、この出願に係る発明は、▲1▼絶縁体層の片面側の銅箔を共通の給電部とし、絶縁体層を貫挿する導電性バンプで接続する他面側配線パターン面に、選択的な電解メッキで突起状バンプを成長させること、▲2▼突起状バンプの成長、形成後、共通の給電部として機能させた銅箔を配線パターンニングすることを骨子とする。そして、このような構成を採ることによって、短小軽薄化や高密度配線を容易に達成し、また、電子部品の実装に当たって、信頼性の高い搭載、実装を確実に達成できる突起状バンプ付き配線基板を歩留まりよく、量産的に提供できる。
【0016】
なお、本発明において、層間絶縁体としては、例えばフェノキシ樹脂、ポリエーテルスルフォン樹脂、ポリスルフォン樹脂、ポリフェニレンスルフォン樹脂、ポリフェニレンサルファイド樹脂、ポリフェニールエーテル樹脂、ポリエーテルイミド樹脂、熱可塑性ポリイミド樹脂、液晶ポリマー、ポリテトラフロロエチレン樹脂などの熱可塑性樹脂、あるいはセミキュア状態に保持された例えばエポキシ樹脂、ビスマレイミドトリアジン樹脂、ポリイミド樹脂、ポリエステル樹脂などの熱硬化性樹脂が挙げられる。特に、液晶ポリマーの選択は、耐熱性、誘電率の安定性が活かされ、高周波伝送用などにも適するからである。液晶ポリマーの選択は、耐熱性、電気絶縁特性、寸法安定性などが優れているので有利である。なお、液晶ポリマーは、例えばキシダール(商品名,Dartco社製)、ベクトラ(商品名,Clanese社製)で代表される多軸配向の熱可塑性ポリマーである。そして、ベクトランAタイプ(融点285℃)、ベクトランCタイプ(融点325℃)、BIACフイルム(融点325℃)などが市販されている。
【0017】
【発明の実施の形態】
以下、図1(a)〜(g)を参照して発明の実施形態を説明する。図1(a)〜(g)は、実施形態に係る突起状バンプ付き配線基板の製造方法の実施態様を模式的に示す要部断面図である。先ず、厚さ9〜35μm銅箔を用意し、この銅箔の一主面側に、例えばステンレス薄鋼板の所定箇所へ0.1〜0.3mm径の孔を明けたメタルマスクを位置決め配置して導電性ペーストを印刷する。この印刷した導電性ペーストが乾燥後、同一メタルマスクを用いて同一位置に再度印刷する方法で、複数回印刷を繰り返し、略円錐状もしくは角錐状の山形バンプを形設する。
【0018】
その後、前記銅箔の山形バンプ形設面側に厚さ25〜100μmの液晶ポリマーフィルム、たとえば融点335℃のBIACフィルム及び厚さ9〜35μmの銅箔を積層的に配置して積層体化する。次いで、この積層体の両銅箔面に当て板を配置して、樹脂圧として4〜8Mpa程度で加圧、一体化し、両面銅箔貼り板を製作する。なお、上記加圧、一体化において、山形バンプは、組成変形性を呈する熱可塑性樹脂フイルム(層間絶縁体)を貫挿し、その先端部が対向する銅箔面に到達して潰れた状態で、電気的には0.01Ω以下の抵抗で対接、接続する。また、熱可塑性樹脂層の厚さは、内装する配線パターン層数、配線基板の厚さ、仕様などによっても異なるが、一般的に、25〜100μm程度である。
【0019】
上記製作した両面銅箔貼り板の一主面側の銅箔について、例えば塩化第2銅水溶液、塩化鉄水溶液、硫酸−過酸化水素水溶液等のエッチング液使用し、フォトエッチング処理して、図1(a)に示すように、所要の配線パターン8化を行って片面配線パターの銅箔9張り板(配線素板)11を作成する。ここで、配線パターン8は、熱可塑性樹脂フイルム10を貫挿する山形バンプ12によって層間接続されている。
【0020】
次に、図1(b)に示すように、前記配線素板11の配線パターン8形成面及び銅箔9面に、メッキレジスト層13を設け、かつこのメッキレジスト層13の所定位置、換言すると接続用の突起状バンプの形設を要する配線パターン8面に、対応する個所を選択的に穿孔13a加工して、配線パターン8面を選択的に露出させる。つまり、図1(c)に示すように、他主面側の銅箔9が露出し、配線パターン8面側にメッキレジスト層13を設けた配線素板11とする。
【0021】
その後、例えばニッケル系の電解メッキ液に浸漬して、所要の電解メッキを施す。ここで、銅箔9が一方の電極として使用され、不溶性の電極(アノード)が対向電極として電解メッキ液中に浸漬され、電源20からメッキ電流が供給される。また、電気メッキによって成長、形成する突起状バンプ14の形状、寸法、数等に応じて、メッキ液温度や電流密度など適宜選択する。
【0022】
次いで、図1(d)に示すように、前記メッキレジスト層13を除去してから、図1(e)に示すように、前記メッキレジスト層13を除去した面全体、及び共通の電解メッキ電極として機能させた他主面の銅箔9面に、それぞれエッチングレジスト15をパターンニングする。その後に、エッチング液による選択的なエッチング処理を施し、図1(f)に示すように、他主面の銅箔9を配線パターン16化する。
【0023】
この配線パターンニング終了後に、前記エッチングレジスト層15をそれぞれ除去することによって、図1(g)に示すような接続用の突起状バンプ14付き配線基板が容易に、また、歩留まりよく得られる。なお、上記エッチングレジスト15層の除去後に、要すればソルダーレジスト処理や外形加工を施す。
【0024】
上記配線基板の製造方法では、一主面側における電子部品搭載領域の接続用バンプ14の電解メッキによる形成に当たって、他主面側の銅箔9を共通の電極として利用する。そして、電解メッキ処理後に配線パターンニング16する。つまり、メッキ処理面側の複数個の接続用バンプ14に対応して複数条の給電部をパターニングする必要がないので、製造工程の煩雑さを低減できるし、また、給電部形成面の不要化に伴って、配線パターンの自由化や、高密度の配線パターン化(インターポーザー等の配線基板のコンパクト化)も行える。
【0025】
そして、実装電子部品の搭載、実装に当たっては、例えばBGA型半導体装置を位置決め、配置する。すなわち、配線基板の突起状バンプ14に対応させ、半田層を介してBGA型半導体装置の端子バンプを位置決め、配置し、この状態で半田が溶融する温度に加熱する一方、半導体装置を配線基板側に圧着することによって実装が行われる。なお、上記半田層は、半導体装置の端子バンプ面、及び配線基板の突起状バンプ14面の少なくともいずれか一方に配置しておけばよい。ここで、実装する電子部品は、BGA型半導体装置の代わりに、CSP型半導体装置、QFP半導体装置、チップ抵抗体であってもよい。
【0026】
本発明は、上記実施形態に限定されるものでなく、発明の主旨を逸脱しない範囲でいろいろの変形を採ることができる。例えば内蔵される配線パターン数は、3層形や5層以上の多層形でもよく、また、層間絶縁体は、熱可塑性樹脂層、熱可塑性樹脂の複層、セミキュア状の熱硬化性樹脂、またはこれらの組み合わせであってもよい。
【0027】
【発明の効果】
本発明によれば、実装電子部品を搭載、実装する配線基板の配線パターン面に、電解メッキ処理で接続用のバンプを突起状に形成するに当たり、配線素板の状態で、他主面に貼着されている銅箔を共通のメッキ電極として利用する。そして、メッキ電極として機能した後には、配線パーンニングされて配線回路の形成に使用される。従って、配線基板面は、より効果的に利用されることになり、高密度配線乃至コンパクトな配線基板を容易に提供できる。また、電子部品を搭載、実装する場合、突起状バンプの形状、寸法なども一様に制御され易いので、例えばアンダーフィル材の注入、充填も容易となり、信頼性の高い実装、接続及び耐湿性等の付与も可能となる。
【図面の簡単な説明】
【図1】(a)〜(g)は実施形態に係る配線基板の製造実施態様を工程順に模式的に示す要部断面図。
【図2】従来の配線基板の製造方法における電解メッキ処理で突起状バンプを形成する配線パターン図。
【図3】(a)〜(d)は従来の配線基板の製造実施態様を工程順に模式的に示す要部断面図。
【符号の説明】
8,16:配線パターン
9:銅箔
10:絶縁体層
11:配線素板
12:山形バンプ
13:メッキレジスト層
13a:メッキレジスト層の開口部
14:突起状バンプ(接続バンプ)
15:エッチングレジスト層
16:配線パターン
[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for manufacturing a wiring board, and more particularly to a method for manufacturing a wiring board with bumps used for mounting.
[0002]
[Prior art]
As electronic devices become shorter, smaller, and thinner, wiring boards that form electrical circuits are required to have high reliability as well as high-density wiring, shorter, smaller, and thinner thicknesses. In response to such demands, multilayer wiring boards have been developed. For example, a multilayer wiring board having a structure in which a polyimide resin or the like is used as an interlayer insulator and a wiring pattern layer is internally provided, while a bump bump for connecting a terminal of an electronic component is formed and provided on the main wiring pattern surface. Is in practical use. In addition, each wiring pattern layer of this multilayer wiring board is electrically connected by a conductor penetrating an interlayer insulator interposed therebetween.
[0003]
And this type of multilayer wiring board is generally manufactured by the following means. First, a copper foil-bonded sheet is prepared by bonding a copper foil to both main surfaces of a polyimide resin film or the like via an adhesive layer. Next, after drilling a predetermined area of this copper foil-bonded sheet and providing via through holes for interlayer connection, the inner wall surface of the through hole is made into a plated conductor, or filled with a conductive composition to connect the interlayer. A conductor is formed and arranged. Thereafter, a photo-etching process is performed on the copper foils on both sides to form a wiring pattern, thereby obtaining a wiring board in which the wiring patterns are connected. And the multilayer wiring board of 3 layers or more is manufactured by repeating the process according to the above (patent document 1).
[0004]
The following configuration is also known as means for simplifying the configuration of the interlayer connection. That is, a protruding conductor (mountain bump) made of a conductive composition, a conductive metal, or the like is formed on a predetermined region surface of the first copper foil. Next, a thermoplastic resin layer and a second copper foil are sequentially laminated and arranged on the forming surface of the protruding conductor of the copper foil. Then, this laminated body was heated and pressurized to be joined and integrated, and a double-sided copper foil bonded plate in which the double-sided copper foil was electrically connected by a protruding conductor having a thermoplastic resin layer inserted therethrough was produced. The double-sided copper foil on the foil-clad plate is etched to form a wiring pattern (Patent Document 1).
[0005]
The manufactured wiring board is used in a mounting circuit device in order to make the electronic circuit compact. For mounting circuit devices, electronic components such as bare chips, BGAs (ball grid arrays), CSPs (chip size packages), and resistor chips are positioned, mounted and arranged on at least one main surface wiring pattern forming surface, Solder must be melted by reflow processing or the like to mount and connect the mounted electronic components. In other words, a bump bump for connection made of nickel or the like is mounted in advance and formed on the wiring pattern surface of the mounting part, corresponding to the terminal bump of the electronic component to be mounted and mounted, and the terminal is connected to this bump bump The bumps are aligned to ensure electrical connection in a state of being separated from each other. On the other hand, in order to reduce the minute stress applied to the connection part between the bumps and protect the mounting electronic component from external humidity and impact, a liquid material called an underfill material is injected and filled between the mounted surfaces. (Patent Document 2).
[0006]
By the way, the formation of the protruding bumps on the wiring board surface is usually performed by the following means. For example, as shown in a plan view in FIG. 2, a wiring pattern 2 forming protruding bumps (connection bumps) 1 a, 1 b, 1 c, 1 d, and 1 e is extended as a power feeding portion 3 to the peripheral portion of the substrate, Electrolytic plating is performed in the order of steps as schematically shown in FIGS. 3A, 3B, 3C, and 3D so that the protruding bumps 1a, 1b, 1c, (1d, 1e are omitted) are formed. Sheng, growing.
[0007]
That is, as shown in a sectional view of the main part in FIG. 3A, a wiring base plate 6 in which wiring patterns 2 connected by conductive bumps 5 penetrating both main surfaces of the insulator layer 4 are disposed. Are prepared, and a plating resist layer 7 is provided on the surfaces where both the wiring patterns 2 are disposed, except for the outside of the line c that is cut and separated in the final outer shape processing. Here, as shown in FIG. 3B, the plating resist layer 7 is selectively opened in the region of the wiring pattern 2 where the bumps 1a, 1b,. (7a) Processed.
[0008]
Next, the wiring base plate 6 provided with the plating resist layer 7 is immersed in an electrolytic nickel plating solution containing nickel sulfate or the like as a main component, and a voltage is applied between the insoluble counter electrode and the power feeding unit 3. As shown in cross section in FIG. 3 (c), nickel-based protruding bumps 1a, 1b,... Are grown and formed. Thereafter, the plating resist layer 7 is removed, and an outer shape process (cutting separation line c) is performed to attach the protruding bumps 1a, 1b,... Shown in FIG. A wiring board is obtained. In addition, as a means for connecting the wiring pattern layers, it is also known that an insulating layer with copper foil is drilled in advance on one side, the copper foil is used as one electroplating electrode, and the inside of the drill is filled with plating metal. Yes.
[0009]
[Patent Document 1]
JP-A-8-264939 (see [0003] [0010])
[0010]
[Patent Document 2]
Japanese Patent Laid-Open No. 11-307586 (see [0002] [0005] [0010] [0014])
[0011]
[Problems to be solved by the invention]
However, the manufacturing process of the wiring board has the following disadvantages. That is, when the bumps 1a, 1b, 1c, and 1d for mounting and mounting the electronic components are built up and grown by electrolytic plating, the power feeding portion 3 corresponding to the same plane is extended. As described above, extending the power feeding portion 3 to the peripheral portion on the same main surface not only complicates the wiring patterning but also restricts the wiring pattern formation region on the main surface, thereby increasing the wiring density. Inhibits compactification.
[0012]
In addition, when the electroplating is advanced by each of the power supply portions 3 corresponding to the protruding bumps 1a, 1b,..., A uniform and uniform voltage is applied to each power supply portion 3 in order to perform uniform electrolytic plating growth. It is also practically difficult to apply, and there is a risk of variations in electrolytic plating. In other words, it is difficult to form the protruding bumps 1a, 1b,... Having a predetermined size and shape as a whole, and there is a concern about a decrease in reliability and the occurrence of defective products, and there are practical problems in terms of yield and productivity. is there.
[0013]
SUMMARY OF THE INVENTION The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a manufacturing method capable of obtaining a highly reliable wiring board with protruding bumps with high yield and high yield.
[0014]
[Means for Solving the Problems]
In the present invention, a copper foil is attached to one main surface of an interlayer insulator layer, a wiring pattern is provided on the other main surface, and the copper foil and the wiring pattern are electrically connected with a conductor penetrating the interlayer insulator layer. Manufacturing a connected wiring base plate;
Providing a plating resist layer by opening a required connection bump forming portion on the wiring pattern surface of the wiring base plate;
A process of subjecting the wiring pattern to electrolytic plating through a conductor penetrating the interlayer insulator layer using the copper foil of the wiring base plate as a common feeding portion, and growing connection bumps in the opening of the plating resist layer; ,
Removing the plating resist layer, providing an etching resist layer on the wiring pattern forming surface and the copper foil surface, etching the copper foil, and patterning the copper foil;
A method for manufacturing a wiring board, comprising:
[0015]
That is, in the invention according to this application, (1) the copper foil on one side of the insulator layer is used as a common power feeding part, and the other side wiring pattern surface connected by the conductive bump penetrating the insulator layer is selected. It is essential to grow bumps by typical electrolytic plating, and (2) after the growth and formation of bumps, patterning the copper foil functioning as a common power feeding portion. By adopting such a configuration, it is possible to easily achieve shortening, lightening and thinning and high-density wiring, and wiring boards with protruding bumps that can reliably achieve reliable mounting and mounting when mounting electronic components. Can be provided in mass production.
[0016]
In the present invention, examples of the interlayer insulator include phenoxy resin, polyether sulfone resin, polysulfone resin, polyphenylene sulfone resin, polyphenylene sulfide resin, polyphenyl ether resin, polyether imide resin, thermoplastic polyimide resin, and liquid crystal polymer. And thermoplastic resins such as polytetrafluoroethylene resin, or thermosetting resins such as epoxy resin, bismaleimide triazine resin, polyimide resin, and polyester resin held in a semi-cured state. This is because the selection of the liquid crystal polymer is particularly suitable for high-frequency transmission and the like because the heat resistance and the stability of the dielectric constant are utilized. The selection of the liquid crystal polymer is advantageous because it has excellent heat resistance, electrical insulation characteristics, dimensional stability, and the like. The liquid crystal polymer is a multiaxially oriented thermoplastic polymer represented by, for example, xidar (trade name, manufactured by Dartco) or Vectra (trade name, manufactured by Clanese). Vectran A type (melting point 285 ° C.), Vectran C type (melting point 325 ° C.), BIAC film (melting point 325 ° C.) and the like are commercially available.
[0017]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the invention will be described with reference to FIGS. FIG. 1A to FIG. 1G are main-part cross-sectional views schematically showing an embodiment of a method for manufacturing a wiring board with protruding bumps according to an embodiment. First, a copper foil having a thickness of 9 to 35 μm is prepared, and a metal mask having a hole having a diameter of 0.1 to 0.3 mm is positioned and arranged on one main surface side of the copper foil, for example, at a predetermined portion of a stainless steel sheet. Print the conductive paste. After the printed conductive paste is dried, printing is repeated a plurality of times by a method of printing again at the same position using the same metal mask to form a substantially conical or pyramidal chevron bump.
[0018]
Thereafter, a liquid crystal polymer film having a thickness of 25 to 100 μm, for example, a BIAC film having a melting point of 335 ° C. and a copper foil having a thickness of 9 to 35 μm are laminated on the mountain-shaped bump-shaped surface side of the copper foil to form a laminate. . Subsequently, a backing plate is arrange | positioned to both the copper foil surfaces of this laminated body, and it pressurizes and integrates by about 4-8 Mpa as a resin pressure, and manufactures a double-sided copper foil bonding board. In the above pressurization and integration, the chevron bump is inserted through a thermoplastic resin film (interlayer insulator) exhibiting compositional deformability, and its tip reaches the opposing copper foil surface and is crushed. Electrically contact and connect with a resistance of 0.01Ω or less. In addition, the thickness of the thermoplastic resin layer is generally about 25 to 100 μm, although it varies depending on the number of wiring pattern layers to be installed, the thickness of the wiring board, specifications, and the like.
[0019]
The copper foil on one main surface side of the produced double-sided copper foil-clad plate is subjected to photoetching using, for example, an etching solution such as cupric chloride aqueous solution, iron chloride aqueous solution, sulfuric acid-hydrogen peroxide aqueous solution, etc. As shown in (a), a required wiring pattern 8 is formed to produce a copper foil 9-clad plate (wiring base plate) 11 of a single-sided wiring pattern. Here, the wiring pattern 8 is interlayer-connected by a chevron bump 12 that penetrates the thermoplastic resin film 10.
[0020]
Next, as shown in FIG. 1B, a plating resist layer 13 is provided on the wiring pattern 8 forming surface and the copper foil 9 surface of the wiring base plate 11, and a predetermined position of the plating resist layer 13, in other words, Corresponding portions are selectively perforated 13a on the surface of the wiring pattern 8 that requires the formation of the protruding bumps for connection, so that the surface of the wiring pattern 8 is selectively exposed. In other words, as shown in FIG. 1C, the copper foil 9 on the other main surface side is exposed, and the wiring base plate 11 is provided with the plating resist layer 13 on the wiring pattern 8 surface side.
[0021]
Thereafter, for example, the substrate is immersed in a nickel-based electrolytic plating solution to perform required electrolytic plating. Here, the copper foil 9 is used as one electrode, an insoluble electrode (anode) is immersed in the electrolytic plating solution as a counter electrode, and a plating current is supplied from the power source 20. In addition, the plating solution temperature, current density, and the like are appropriately selected according to the shape, size, number, and the like of the bumps 14 that are grown and formed by electroplating.
[0022]
Next, as shown in FIG. 1 (d), after removing the plating resist layer 13, the entire surface from which the plating resist layer 13 has been removed and a common electrolytic plating electrode as shown in FIG. 1 (e). The etching resist 15 is patterned on the surface of the copper foil 9 of the other main surface that functions as the above. Thereafter, a selective etching process using an etching solution is performed, and the copper foil 9 on the other main surface is formed into a wiring pattern 16 as shown in FIG.
[0023]
After the wiring patterning is completed, the etching resist layer 15 is removed to obtain a wiring board with protruding bumps 14 for connection as shown in FIG. 1 (g) with good yield. In addition, after removing the etching resist 15 layer, if necessary, a solder resist process or an outer shape process is performed.
[0024]
In the method of manufacturing the wiring board, the copper foil 9 on the other main surface side is used as a common electrode in forming the connection bump 14 in the electronic component mounting region on one main surface side by electrolytic plating. Then, wiring patterning 16 is performed after the electrolytic plating process. That is, since it is not necessary to pattern a plurality of power supply portions corresponding to the plurality of connection bumps 14 on the plated surface side, it is possible to reduce the complexity of the manufacturing process and eliminate the need for a power supply portion forming surface. Along with this, it is possible to liberalize the wiring pattern and to form a high-density wiring pattern (compact wiring board such as an interposer).
[0025]
In mounting and mounting the mounting electronic component, for example, a BGA type semiconductor device is positioned and arranged. That is, the terminal bumps of the BGA type semiconductor device are positioned and arranged through the solder layer so as to correspond to the protruding bumps 14 of the wiring board, and the semiconductor device is heated to a temperature at which the solder melts in this state, while the semiconductor device is placed on the wiring board side. Mounting is performed by pressure bonding to the substrate. The solder layer may be disposed on at least one of the terminal bump surface of the semiconductor device and the projecting bump surface 14 of the wiring board. Here, the electronic component to be mounted may be a CSP type semiconductor device, a QFP semiconductor device, or a chip resistor instead of the BGA type semiconductor device.
[0026]
The present invention is not limited to the above embodiment, and various modifications can be made without departing from the spirit of the invention. For example, the number of built-in wiring patterns may be a three-layered form or a multilayered form of five or more layers, and the interlayer insulator may be a thermoplastic resin layer, a multilayered thermoplastic resin, a semi-cured thermosetting resin, or A combination of these may also be used.
[0027]
【The invention's effect】
According to the present invention, in forming a bump for connection on the wiring pattern surface of the wiring board on which the mounting electronic component is mounted and mounted by the electrolytic plating process, it is pasted on the other main surface in the state of the wiring base plate. The applied copper foil is used as a common plating electrode. Then, after functioning as a plating electrode, the wiring is panned and used to form a wiring circuit. Therefore, the wiring board surface is used more effectively, and a high-density wiring or a compact wiring board can be easily provided. In addition, when mounting and mounting electronic components, the shape and dimensions of the bumps can be easily controlled. For example, underfill material can be easily injected and filled, and reliable mounting, connection and moisture resistance can be achieved. Etc. can also be given.
[Brief description of the drawings]
FIGS. 1A to 1G are main part cross-sectional views schematically showing a manufacturing mode of a wiring board according to an embodiment in order of processes.
FIG. 2 is a wiring pattern diagram for forming protruding bumps by electrolytic plating in a conventional method for manufacturing a wiring board.
FIGS. 3A to 3D are main part cross-sectional views schematically showing a conventional embodiment of manufacturing a wiring board in the order of steps;
[Explanation of symbols]
8, 16: Wiring pattern 9: Copper foil 10: Insulator layer 11: Wiring base plate 12: Mountain-shaped bump 13: Plating resist layer 13a: Plating resist layer opening 14: Protruding bump (connection bump)
15: Etching resist layer 16: Wiring pattern

Claims (2)

層間絶縁体層の一主面に銅箔が貼着され他主面に配線パターンを有し、かつ銅箔及び配線パターンが前記層間絶縁体層を貫挿する導体で電気的に接続された配線素板を製造する工程と、
前記配線素板の配線パターン面に所要の接続バンプ形成部を開口してメッキレジスト層を設ける工程と、
前記配線素板の銅箔を共通の給電部として前記層間絶縁体層を貫挿する導体を介して前記配線パターンに電解メッキ処理を施してメッキレジスト層の開口部に接続バンプを成長させる工程と、
前記メッキレジスト層を除去し、配線パターン形成面及び銅箔面にエッチングレジスト層を設けエッチング処理して銅箔を配線パターンニングする工程と、
を有することを特徴とする配線基板の製造方法。
A wiring in which a copper foil is attached to one main surface of an interlayer insulator layer, a wiring pattern is provided on the other main surface, and the copper foil and the wiring pattern are electrically connected by a conductor penetrating the interlayer insulator layer Manufacturing the base plate;
Providing a plating resist layer by opening a required connection bump forming portion on the wiring pattern surface of the wiring base plate;
A process of subjecting the wiring pattern to electrolytic plating through a conductor penetrating the interlayer insulator layer using the copper foil of the wiring base plate as a common feeding portion, and growing connection bumps in the opening of the plating resist layer; ,
Removing the plating resist layer, providing an etching resist layer on the wiring pattern forming surface and the copper foil surface, etching the copper foil, and patterning the copper foil;
A method of manufacturing a wiring board, comprising:
層間絶縁体層が熱可塑性液晶ポリマーであることを特徴とする請求項1記載の配線基板の製造方法。2. The method of manufacturing a wiring board according to claim 1, wherein the interlayer insulator layer is a thermoplastic liquid crystal polymer.
JP2003190865A 2003-07-03 2003-07-03 Method for manufacturing wiring board Pending JP2005026491A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
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Publications (1)

Publication Number Publication Date
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Family

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Family Applications (1)

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Country Status (1)

Country Link
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008211152A (en) * 2007-02-28 2008-09-11 Meiko:Kk Printed wiring board and electronic component mounting board

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008211152A (en) * 2007-02-28 2008-09-11 Meiko:Kk Printed wiring board and electronic component mounting board

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