JP2005020393A - Semiconductor integrated circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor integrated circuit provided with a voltage controlled oscillation circuit capable of suppressing jitters generated in oscillation signals and obtaining a stable oscillation frequency. <P>SOLUTION: The oscillation frequency of a ring oscillator 2 is decided by the delay time of the delay cell 10 of an odd-numbered stage. For the delay cell 10, the delay time becomes short when the voltage of signals S7 drops and the delay time becomes long when the voltage rises. The oscillation signals S1 of the ring oscillator 2 are inputted through a frequency divider 3 to a first delay circuit 2 and the output is inputted to a second delay circuit 5. The first delay time of the first delay circuit 4 and the second delay time of the second delay circuit 5 are compared, the voltage of the signals S7 is dropped in the case that the second delay time is longer than the first delay time, and the voltage of the signals S7 is raised in the case that it is shorter. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor integrated circuit including a voltage controlled oscillation circuit.
[0002]
[Prior art]
Conventionally, there has been known a ring oscillator in which an odd number of inverting circuits are cascaded as a voltage controlled oscillation circuit and an oscillation signal is obtained by inputting the output signal of the last inverting circuit to the inverting circuit of the first stage. Yes.
[0003]
The oscillation frequency of the ring oscillator is determined by the delay time of the output of the inverting circuit. Therefore, it is possible to set the oscillation frequency of the ring oscillator by connecting a delay element to the output terminal of these inverting circuits and controlling the control voltage (see, for example, Patent Document 1).
[0004]
[Patent Document 1]
Japanese Patent Laid-Open No. 2002-185290
[Problems to be solved by the invention]
However, if a voltage fluctuation occurs in the power supply (VDD) supplied to the inverting circuit due to some factor, the signal propagation speed in the inverting circuit changes, resulting in jitter of the generated oscillation signal.
[0006]
In addition, when the noise is superimposed on the control voltage of the delay element, the delay time of the inverting circuit is changed and becomes jitter of the oscillation signal.
[0007]
SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit including a voltage controlled oscillation circuit that can suppress jitter generated in an oscillation signal and obtain a stable oscillation frequency.
[0008]
[Means for Solving the Problems]
In order to solve the above problem, according to one aspect of the present invention, a ring oscillator that generates an oscillation signal using a delay element that can control a propagation delay time using a control voltage applied between control voltage terminals, and a control voltage A delay element capable of controlling a propagation delay time by a control voltage applied between the terminals, a first delay circuit for giving a first delay time to the oscillation signal, and the first delay circuit substantially And a second delay circuit for providing a second delay time to the oscillation signal to which the first delay time is given, and comparing the first delay time with the second delay time. The control voltage is increased when the second delay time is longer than the first delay time, and the control voltage is decreased when the second delay time is shorter than the first delay time. Control voltage generator The semiconductor integrated circuit, wherein the obtaining is provided.
[0009]
According to another aspect of the present invention, a ring oscillator that generates an oscillation signal using a delay element capable of controlling a propagation delay time by a control voltage applied between control voltage terminals, an output terminal of the ring oscillator, A first delay circuit connected and capable of controlling a propagation delay time, and a second delay connected to the output terminal of the first delay circuit and having substantially the same function as the first delay circuit A first exclusive OR circuit having a first input terminal connected to an input terminal of the first delay circuit and a second input terminal connected to an output terminal of the first delay circuit; A second exclusive OR circuit having a first input terminal connected to the input terminal of the second delay circuit and a second input terminal connected to the output terminal of the second delay circuit; The terminal is the output terminal of the first exclusive OR circuit and the second exclusive OR circuit When the output of the first exclusive OR circuit is 1 level, the first polarity current is generated when the output of the first exclusive OR circuit is 1 level, and when the output of the second exclusive OR circuit is 1 level. A charge pump element that generates a current having a second polarity opposite to the first polarity, and an output terminal of the charge pump element. The charge generated by the charge pump element is charged to generate the control voltage. There is provided a semiconductor integrated circuit comprising a capacitor to be provided.
[0010]
According to another aspect of the present invention, when the voltage difference between the first control voltage applied to the first control voltage terminal and the second control voltage applied to the second control voltage terminal increases. When the propagation delay time is shortened and the voltage difference is reduced, a ring oscillator that generates an oscillation signal using a delay element that can be controlled so as to increase the propagation delay time and a first control voltage terminal are provided. When the voltage difference between the first control voltage and the second control voltage applied to the second control voltage terminal increases, the propagation delay time decreases, and when the voltage difference decreases, the propagation delay time increases. A delay element that can be controlled so as to have a first delay circuit that gives a first delay time to the oscillation signal, and a function that is substantially the same as the first delay circuit. The oscillation signal is given a delay time of A second delay circuit for providing a second delay time to the second delay circuit, and comparing the first delay time with the second delay time, and if the second delay time is longer than the first delay time, A control voltage generation unit that increases a voltage difference between the first control voltage and the second control voltage and decreases the voltage difference when the second delay time is shorter than the first delay time; A semiconductor integrated circuit is provided.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
A semiconductor integrated circuit including a voltage controlled oscillation circuit according to an embodiment of the present invention will be described with reference to the drawings.
[0012]
FIG. 1 is a circuit diagram of a semiconductor integrated circuit 1 including a voltage controlled oscillation circuit according to an embodiment of the present invention.
[0013]
A semiconductor integrated circuit 1 including a voltage controlled oscillation circuit includes a ring oscillator 2, a frequency divider 3, first and second delay circuits 4 and 5, first and second exclusive OR circuits 6 and 7, charge It consists of a pump element 8 and a capacitor 9.
[0014]
Here, the first and second exclusive OR circuits 6, 7, the charge pump element 8 and the capacitor 9 constitute a control voltage generation unit 20, and the control given to the ring oscillator 2 and the first and second delay circuits. Generating voltage.
[0015]
The ring oscillator 2 has three delay cells 10 connected in cascade, and a signal output from the last-stage delay cell 10 is input to the front-stage delay cell 10.
[0016]
Specifically, as shown in FIG. 2, the delay cell 10 includes an inverter circuit 11 and a delay element 12, and each delay cell 10 has the same structure.
[0017]
The ring oscillator 2 shown in FIG. 2 has three delay cells 10 connected in cascade. However, the number of delay cells 10 is not limited to this, and the inverter circuit 11 in the delay cell 10 has an odd number of cascade connections. I just need it.
[0018]
In the inverter circuit 11, the source electrode of the PMOS transistor Q1 is grounded (GND) and the source electrode of the NMOS transistor Q2 is grounded (GND).
[0019]
The delay time of the delay element 12 is controlled by the control voltages V1 and V2. Specifically, the oscillation frequency of the ring oscillator 2 changes in proportion to the voltage difference (V2−V1) between the control voltages V1 and V2, that is, the delay time of the delay element 12 is the voltage difference (V2−V1). ) And is controlled in inverse proportion. Therefore, when the control voltage V1 is increased, the delay time of the delay element is increased, and when the control voltage V2 is increased, the delay time of the delay element is decreased.
[0020]
In this embodiment, for simplification of explanation, the control voltage V2 is fixed to a constant voltage, and the delay time of the delay cell 10 is controlled only by the control voltage V1 which is the voltage of the signal S7. Therefore, when the voltage V1 of the signal S7 increases, the delay time of the delay element 12 becomes longer, and when the voltage V1 decreases, the delay time becomes shorter.
[0021]
In the present embodiment, the ring oscillator 2 is configured by the cascade connection of the delay cells 10 in three stages. However, the present invention is not limited to this, and the delay cells 10 in the odd stages may be connected in cascade. The configuration of the delay cell 10 is not limited to this embodiment, and it is sufficient that the delay time can be voltage-controlled and has a function capable of inverting the input signal.
[0022]
The frequency divider 3 is a circuit that converts the frequency of the oscillation signal generated by the ring oscillator 2 described above to a frequency of 1 / N. Here, the frequency of the oscillation signal is converted to a quarter frequency.
[0023]
The first and second delay circuits 4 and 5 have the same circuit configuration, and the delay cells 10 are cascaded in the same manner as the ring oscillator 2 described above. The circuit configuration of the delay cell 10 of the first and second delay circuits 4 and 5 is the same as that of the delay cell 10 of the ring oscillator 2 and includes an inverter circuit 11 and a delay element 12 as shown in FIG. . The delay elements 12 of the first and second delay circuits 4 and 5 are controlled in delay time by the same control voltages V 1 and V 2 as the delay elements 12 of the ring oscillator 2.
[0024]
The number of delay cells 10 in the first and second delay circuits 4 and 5 is the same.
[0025]
In FIG. 1, first and second exclusive OR circuits 6 and 7 are 1-bit mismatch circuits, and output is 0 level only when 2 input signals are both 0 level or 1 level. This is a circuit for setting the output at different times to one level.
[0026]
The charge pump element 8 is a circuit that controls an output current according to an input signal. The control voltage V1 is determined by charging the capacitor 9 with the current output from the charge pump element 8.
[0027]
The oscillation signal generated by the ring oscillator 2 is input to the frequency divider 3 and divided by four. The frequency-divided oscillation signal is input to the first input terminal of the first delay circuit 4 and the first exclusive OR circuit 6.
[0028]
The oscillation signal delayed by the first delay circuit 4 is supplied to the second input terminal of the second delay circuit 5 and the first exclusive OR circuit 6 and the first input of the second exclusive OR circuit 7. Input to the input terminal.
[0029]
The oscillation signal delayed by the second delay circuit 5 is input to the second input terminal of the second exclusive OR circuit 7.
[0030]
The output signals of the first and second exclusive OR circuits 6 and 7 are input to the charge pump element 8, respectively.
[0031]
The output current of the charge pump element 8 is controlled by the output signals of the first and second exclusive OR circuits 6 and 7. By charging this output current to the capacitor 9, the voltage of the signal S7 is determined.
[0032]
In this way, the control voltage generator 20 compares the delay times of the first and second delay circuits 4 and 5, and increases or decreases the control voltage V1 according to the increase or decrease of the voltage difference.
[0033]
The signal S7 is input to the ring oscillator 2 and the delay element 12 in the first and second delay circuits 4 and 5.
[0034]
Next, timing charts of respective signals showing the operation of the voltage control circuit 1 shown in FIG. 1 will be described with reference to FIGS.
[0035]
In each figure, signal S1 is an oscillation signal output from ring oscillator 2, signal S2 is a signal obtained by dividing signal S1, signal S3 is a signal obtained by delaying signal S2 by first delay circuit 4, and signal S4 is A signal obtained by delaying the signal S3 by the second delay circuit 5 is shown. The signal S5 is an output signal of the first exclusive OR circuit 6, the signal S6 is an output signal of the second exclusive OR circuit 7, CPI is an output current from the charge pump element 8, and a signal S7 is a charge pump. The output voltage V1 generated when the output current of the element 8 is charged by the capacitor 9 is shown.
[0036]
The signal S1 is an oscillation signal generated by the ring oscillator 2, but the frequency may fluctuate due to a change in external temperature or external voltage, and jitter may occur. Here, T is the wavelength of the signal S1. For comparison, the signal REF is shown as an oscillation signal without jitter.
[0037]
Since the signal S2 is obtained by dividing the signal S1 by 4, the wavelength of the signal S2 is 4T.
[0038]
Signal S3 is delayed by T / 2 with respect to signal S2. This is because the first delay circuit 4 of the present embodiment has three delay cells 10 that are the same as the delay cells 10 of the ring oscillator 2 connected in cascade, so that the delay time is T / 2.
[0039]
Note that the delay time of the first delay circuit 4 need not be T / 2. Therefore, the number of delay cells 10 in the first delay circuit 4 is not necessarily the same as the number of delay cells 10 in the ring oscillator 2.
[0040]
Signal S4 is delayed by T / 2 with respect to signal S3. This is a delay time due to the delay of the second delay circuit 5, and can be explained in the same manner as the relationship between the signal S3 and the signal S2.
[0041]
Since the signal S5 is an exclusive OR of the signal S2 and the signal S3, it becomes 1 level when the two signals do not match. Accordingly, the delay time T / 2 by the first delay circuit 4 becomes one level.
[0042]
Since the signal S6 is an exclusive OR of the signal S3 and the signal S4, the signal S6 becomes 1 level when the two signals do not match. Accordingly, the delay time T / 2 by the second delay circuit 5 becomes one level.
[0043]
The CPI outputs a positive current when the signal S6 is 1 level, and outputs a negative current when the signal S7 is 1 level.
[0044]
The signal S7 is a voltage V1 generated by charging the output current of the charge pump element 8 by the capacitor 9.
[0045]
FIG. 3 shows an operation timing chart when the oscillation signal S1 has no jitter and maintains a constant frequency.
[0046]
Signal S5 indicates a delay time of the first delay circuit 4, the delay time is t _1. On the other hand, signal S6 represents the delay time of the second delay circuit 5, the delay time is t _2.
[0047]
Since there is no jitter in FIG. 3, the delay times t1 and t2 are equal. Accordingly, since the positive and negative currents output from the charge pump element 8 are equal, the voltage of the signal S7 charged in the capacitor 9 maintains a constant value.
[0048]
This signal S7 controls the delay time of the ring oscillator 2 and the first and second delay circuits 4 and 5, but since the voltage of the signal S7 is a constant value, these delay times can be kept constant.
[0049]
FIG. 4 shows an operation timing chart when jitter occurs due to some influence and the frequency of the oscillation signal is small, that is, the oscillation signal tends to expand.
[0050]
Since the delay time is extended each time, towards the delay time t ₂ of the second delay circuit 5 is longer than the delay time t ₁ of the first delay circuit 4. Therefore, since the positive current is output from the charge pump element 8 longer than the negative current, the voltage value of the signal S7 charged in the capacitor 9 increases.
[0051]
This signal S7 is the control voltage V1 of the ring oscillator 2 and the first and second delay circuits 4 and 5. Since the voltage of the signal S7 is increased by the charge pump element 8, the delay time of the delay element 12 in the ring oscillator 2 is controlled to be shortened.
[0052]
In this way, by detecting the tendency of the delay time of the delay element 12 to increase and shortening the delay time of the ring oscillator 2, it is possible to return to the original oscillation signal without jitter.
[0053]
FIG. 5 shows an operation timing chart when jitter occurs due to some influence and the frequency of the oscillation signal is large, that is, the oscillation signal tends to be shortened.
[0054]
Since the delay time has shrunk every time, towards the delay time t ₂ of the second delay circuit 5 is shorter than the delay time t ₁ of the first delay circuit 4. Accordingly, since the negative current is output from the charge pump element 8 longer than the positive current, the voltage value of the signal S7 charged in the capacitor 9 decreases.
[0055]
Since the voltage of the signal S7 is lowered by the charge pump element 8, the delay time of the delay element 12 in the ring oscillator 2 is controlled to be longer.
[0056]
In this way, by detecting the tendency of the delay time of the delay element 12 to be shortened and increasing the delay time of the ring oscillator 2, it is possible to return to the original oscillation signal without jitter.
[0057]
As described above, the oscillation frequency of the ring oscillator 2 is controlled by comparing the delay times of the signals that have passed through the first and second delay circuits 4 and 5 having two identical structures connected in cascade. Can do.
[0058]
That is, when the delay time of the second delay circuit 5 is longer than the delay time of the first delay circuit 4, it is considered that the frequency of the oscillation signal is reduced, and the delay time of the delay element 12 is controlled to be longer. As a result, the oscillation frequency of the ring oscillator 2 is increased. On the contrary, when the delay time of the second delay circuit 5 is shorter than the delay time of the first delay circuit 4, it is considered that the frequency of the oscillation signal is increased, and the delay time of the delay element 12 is controlled to be short. As a result, the oscillation frequency of the ring oscillator 2 is reduced.
[0059]
As described above, the oscillation frequency of the ring oscillator 2 is detected as the delay time of the delay element 12 being short and long, and the jitter of the ring oscillator 2 can be eliminated by controlling the delay time.
[0060]
If voltage fluctuation occurs in the power supply (VDD) due to some influence and the propagation speed of the inverter circuit 11 changes, jitter is generated. This jitter is calculated as the difference between the delay times of the first and second delay circuits 4 and 5. Since the propagation speed of the delay element 12 is controlled by relatively comparing, the generated jitter can be suppressed.
[0061]
In the above-described embodiment, the oscillation frequency is divided by 4 by the frequency divider 3 before the oscillation signal generated from the ring oscillator 2 is input to the first delay circuit 4.
[0062]
This gives a time margin to the processing speed of the control voltage generator 20 and facilitates the measurement of the comparison between the delay time of the first delay circuit 4 and the delay time of the second delay circuit 5. If the delay time can be easily measured by other means, the frequency divider is not necessarily used.
[0063]
The ring oscillator 2 and the delay elements 12 in the first and second delay circuits 4 and 5 have the control voltage V2 fixed, and the delay time is controlled only by the control voltage V1, but the present invention is not limited to this. For example, when the voltage controlled oscillation circuit of the present embodiment is used in a PLL (Phase Locked Loop) circuit, the control voltage V2 is configured to be controlled by a loop filter. Since the voltage difference between the two control voltages V1 and V2 controls the delay time, it is sufficient that the delay time can be controlled by increasing or decreasing the voltage difference.
[0064]
Further, the ring oscillator 2 and the delay cells 10 of the first and second delay circuits 4 and 5 do not have to have completely the same configuration, as long as they provide at least substantially the same delay time. Good.
[0065]
【The invention's effect】
As described above in detail, the present invention can provide a voltage-controlled oscillation circuit that suppresses jitter generated in an oscillation signal and has a stable oscillation frequency.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a semiconductor integrated circuit including a voltage controlled oscillation circuit according to an embodiment of the present invention.
FIG. 2 is a circuit diagram of the ring oscillator shown in FIG.
FIG. 3 is a diagram showing the operation timing of the voltage controlled oscillation circuit when there is no variation in the delay time of the delay cell.
FIG. 4 is a diagram showing the operation timing of the voltage-controlled oscillation circuit when the delay time of the delay cell tends to expand.
FIG. 5 is a diagram showing the operation timing of the voltage controlled oscillation circuit when the delay time of the delay cell tends to be shortened.
[Explanation of symbols]
1 Voltage controlled oscillator (VCO)
2 ... Ring oscillator 3 ... Frequency divider 4 ... First delay circuit 5 ... Second delay circuit 6 ... First exclusive OR circuit 7 ... Second Exclusive OR circuit 8 ... charge pump element 9 ... capacitor 10 ... delay cell 11 ... inverter circuit 12 ... delay element 20 ... control voltage generator

Claims (5)

A ring oscillator that generates an oscillation signal using a delay element capable of controlling a propagation delay time by a control voltage applied between control voltage terminals;
A delay element capable of controlling a propagation delay time by a control voltage applied between control voltage terminals, and a first delay circuit for giving a first delay time to the oscillation signal;
A second delay circuit having substantially the same function as the first delay circuit, and further giving a second delay time to the oscillation signal to which the first delay time is given;
The first delay time is compared with the second delay time, and if the second delay time is longer than the first delay time, the control voltage is increased, and the first delay time is longer than the first delay time. A semiconductor integrated circuit, comprising: a control voltage generation unit configured to decrease the control voltage when the second delay time is short. A ring oscillator that generates an oscillation signal using a delay element capable of controlling a propagation delay time by a control voltage applied between control voltage terminals;
A first delay circuit connected to the output terminal of the ring oscillator and capable of controlling a propagation delay time;
A second delay circuit connected to the output terminal of the first delay circuit and having substantially the same function as the first delay circuit;
A first exclusive OR circuit having a first input terminal connected to an input terminal of the first delay circuit and a second input terminal connected to an output terminal of the first delay circuit;
A second exclusive OR circuit having a first input terminal connected to an input terminal of the second delay circuit and a second input terminal connected to an output terminal of the second delay circuit;
When the input terminal is connected to the output terminal of the first exclusive OR circuit and the output terminal of the second exclusive OR circuit, and the output of the first exclusive OR circuit is 1 level, A charge pump element that generates a current having a polarity of 1 and generates a current having a second polarity opposite to the first polarity when the output of the second exclusive OR circuit is at a level of 1;
A semiconductor integrated circuit, comprising: a capacitor connected to an output terminal of the charge pump element, and charged with the charge generated by the charge pump element to give the control voltage. When the voltage difference between the first control voltage applied to the first control voltage terminal and the second control voltage applied to the second control voltage terminal increases, the propagation delay time becomes shorter, and the voltage difference becomes smaller. A ring oscillator that generates an oscillation signal using a delay element that can be controlled so that the propagation delay time becomes longer when reduced,
When the voltage difference between the first control voltage applied to the first control voltage terminal and the second control voltage applied to the second control voltage terminal increases, the propagation delay time becomes shorter, and the voltage difference becomes smaller. A first delay circuit that includes a delay element that can be controlled to increase a propagation delay time when decreased, and that provides a first delay time to the oscillation signal;
A second delay circuit having substantially the same function as the first delay circuit, and further giving a second delay time to the oscillation signal to which the first delay time is given;
The first delay time and the second delay time are compared, and if the second delay time is longer than the first delay time, the voltage difference between the first control voltage and the second control voltage And a control voltage generator that reduces the voltage difference when the second delay time is shorter than the first delay time. 4. The ring oscillator and the first and second delay circuits are connected in cascade with the same number of stages of the delay elements having substantially the same function. The semiconductor integrated circuit according to Item. 4. The oscillation signal generated by the ring oscillator is divided into N frequencies by a frequency divider and input to the first delay circuit. 5. Semiconductor integrated circuit.

Images