JP2005017361A - Electro-optical device and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent the occurrence of stripe-patterned unevenness caused by a lateral electric field. <P>SOLUTION: A electro-optical device comprises: first and second substrates placed opposite to each other; a plurality of pixel electrodes 9a which are disposed on the first substrate in a matrix and in which driving voltages with mutually opposite polarities are applied to every two neighboring lines; a common electrode disposed on the second substrate; an electro-optical material interposed between the first and second substrates; and a protruding part 111 formed on at least a position on a strip-shaped region along the inside of an edge of the pixel electrode on the first substrate in a range F where the electro-optical material is affected by an electric field generated by the driving voltages with the mutually opposite polarities between every two neighboring pixel electrodes 9a. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an electro-optical device and an electronic apparatus suitable for a liquid crystal device or the like.
[0002]
[Prior art]
The liquid crystal device is configured by sealing liquid crystal between two substrates such as a glass substrate and a quartz substrate. In a liquid crystal device, active elements such as thin film transistors (hereinafter referred to as TFTs) are arranged in a matrix on one substrate, a counter electrode is arranged on the other substrate, and sealed between both substrates. An image can be displayed by changing the optical characteristics of the liquid crystal layer according to the image signal.
[0003]
That is, an image signal is supplied to pixel electrodes (ITO) arranged in a matrix by TFT elements, and a voltage based on the image signal is applied to the liquid crystal layer between the pixel electrode and the counter electrode to change the arrangement of liquid crystal molecules. Let As a result, the transmittance of the pixel is changed, and light passing through the pixel electrode and the liquid crystal layer is changed according to the image signal to perform image display.
[0004]
In order to define the alignment of liquid crystal molecules when no voltage is applied, an alignment film is formed on the surface of one substrate (active matrix substrate (also referred to as element substrate)) and the other substrate (counter substrate) in contact with the liquid crystal layer. The alignment film is rubbed. By rubbing, liquid crystal molecules when no voltage is applied are aligned in the rubbing direction. For example, when a rubbing process in which the element substrate and the counter substrate are twisted by 90 degrees is performed, the liquid crystal molecules continuously change directions in the liquid crystal panel, and the substrates are arranged in different directions by 90 degrees.
[0005]
Polarizers are provided on the front and back surfaces of the liquid crystal panel, and only a predetermined polarization component of the incident light is allowed to pass through. In the normally white mode, the polarization axes of the polarizing plates on the front surface and the back surface of the liquid crystal panel are made to differ by 90 degrees to match the rubbing direction of the substrate.
If it does so, the light which injected through the polarizing plate of the back surface of a liquid crystal panel will rotate 90 degree | times according to the arrangement | sequence of a liquid crystal molecule in a liquid crystal layer at the time of no voltage application, and will be radiate | emitted through a polarizing plate from the front surface of a liquid crystal panel. Thereby, white display is performed.
[0006]
When a voltage is applied to the liquid crystal, the alignment direction of the liquid crystal changes, that is, the major axis direction of the liquid crystal molecules is tilted according to the voltage, and the rotation of the vibration direction of the light by the liquid crystal in the liquid crystal panel is limited. The emitted light is absorbed by the polarizing plate. An image is displayed by applying a voltage corresponding to the image signal to the liquid crystal and transmitting light with a transmittance corresponding to the image signal.
[0007]
As described above, the alignment of the liquid crystal molecules when no voltage is applied is determined by forming an alignment film and performing a rubbing treatment. The alignment film is formed, for example, by applying polyimide with a thickness of about several tens of nanometers. By forming an alignment film on the surfaces of both substrates facing the liquid crystal layer, the liquid crystal molecules can be aligned along the substrate surface. In the rubbing process, fine grooves are formed on the surface of the alignment film to form an alignment anisotropic film, and the alignment of liquid crystal molecules can be defined by performing a rubbing process in a certain direction on the alignment film.
[0008]
In addition, in order to make the direction in which the tilt angle of the liquid crystal molecules changes when a voltage is applied between all the liquid crystal molecules, the major axis of the liquid crystal molecules is set to a predetermined angle (pretilt angle) with respect to the substrate when no voltage is applied. It is inclined and arranged.
[0009]
By the way, in the liquid crystal device, application of a DC voltage to the liquid crystal causes deterioration of the liquid crystal such as decomposition of liquid crystal components, contamination by impurities generated in the liquid crystal cell, and burn-in of a display image. Therefore, in general, inversion driving is performed in which the polarity of the driving voltage of each pixel electrode is inverted at a constant period such as one frame or one field in an image signal.
[0010]
When the polarity of the drive voltage of all the pixel electrodes constituting the image display area is simply inverted at a fixed period (ie, so-called video inversion drive method), flicker and crosstalk occur at a fixed period, especially when the number of pixels is large. Resulting in. Therefore, in order to prevent the occurrence of flicker and crosstalk with a constant cycle, for example, 1H inversion drive method for inverting the polarity of the drive voltage for each row of pixel electrodes or 1S for inverting for each column of pixel electrodes at a constant cycle. A line inversion driving method such as an inversion driving method has been developed. Furthermore, a dot inversion driving method has been developed in which the polarity of the driving voltage is inverted every dot (that is, every row and every column) at a constant cycle.
[0011]
[Patent Document 1]
JP 2003-131257 A
[0012]
[Problems to be solved by the invention]
However, in the case of the line inversion driving method, an electric field (hereinafter referred to as a lateral electric field) is generated between adjacent pixel electrodes on the same substrate in the column direction or the row direction to which voltages having different polarities are applied. . In the case of the dot inversion driving method, a horizontal electric field is generated between pixel electrodes adjacent to each other in the row direction and the column direction to which voltages having different polarities are applied.
[0013]
FIG. 12 is an explanatory view schematically showing the influence of the pretilt of the liquid crystal molecules and the lateral electric field when no voltage is applied. FIG. 13 is an explanatory diagram schematically showing a planar shape of the liquid crystal device.
[0014]
As described above, the liquid crystal molecules are arranged with a predetermined pretilt angle. A drive voltage having a reverse polarity is applied to the adjacent pixel electrode 121 as shown by + and − in FIGS. 12 and 13. Then, a lateral electric field 123 indicated by a broken line in FIG. 12 is generated between adjacent pixel electrodes 121. When such a horizontal electric field 123 is generated between adjacent pixels, a portion where the inclination direction of the liquid crystal molecules 124 is different from the other liquid crystal molecules 122 is generated on one end side of the pixel electrode 121 due to the influence of the horizontal electric field 123. Cheap.
[0015]
The liquid crystal molecules have a characteristic in which the arrangement of the liquid crystal molecules is continuously changed between adjacent liquid crystal molecules, and is indicated by the hatched portion in FIG. 13 due to the disorder of the arrangement of the liquid crystal molecules (disclination) generated at a predetermined position. Thus, a streak-like pattern (streaks unevenness) appears in the horizontal direction along the poorly aligned portion.
[0016]
In recent years, in order to improve the uniformity of alignment, a liquid crystal device in which the surface of a liquid crystal substrate is flattened as in Patent Document 1 has been developed. In particular, in such a flattened liquid crystal device, there is a problem that the above-described horizontal stripe unevenness is likely to appear.
[0017]
The present invention has been made in view of such a problem, and is formed by forming a portion that suppresses the disorder of the continuous arrangement of liquid crystal molecules at a position corresponding to the edge of the pixel electrode that is affected by a lateral electric field. Another object of the present invention is to provide an electro-optical device and an electronic apparatus that can prevent the occurrence of uneven horizontal stripes.
[0018]
[Means for Solving the Problems]
The electro-optical device according to the present invention is arranged in a matrix on the first and second substrates disposed opposite to each other and on the first substrate, and drive voltages having opposite polarities are applied to adjacent lines. A plurality of pixel electrodes, a common electrode provided on the second substrate, an electro-optic material sandwiched between the first and second substrates, and the pixel electrodes adjacent to each other by the driving voltage having the opposite polarity And a projection formed on the first substrate in at least one band-like region along the inner side of one edge of the pixel electrode, the range being affected by the electro-optic material. It is characterized by.
[0019]
According to such a configuration, drive voltages having opposite polarities are applied to adjacent pixel electrodes, and a horizontal electric field is generated between adjacent pixel electrodes. Due to this lateral electric field, striped stripe irregularities are likely to occur along the inside of one edge of the pixel electrode. The protrusion is formed on at least one first substrate in the band-like region, and suppresses the occurrence of stripe unevenness.
[0020]
The electro-optical device according to the present invention is arranged in a matrix on the first and second substrates disposed opposite to each other and on the first substrate, and drive voltages having opposite polarities are applied to adjacent lines. A plurality of pixel electrodes, a common electrode provided on the second substrate, an electro-optic material sandwiched between the first and second substrates, and the pixel electrodes adjacent to each other by the driving voltage having the opposite polarity And a projection formed on the second substrate in at least one band-like region along the inner side of one edge of the pixel electrode, the range being affected by the electro-optic material. It is characterized by.
[0021]
According to such a configuration, drive voltages having opposite polarities are applied to adjacent pixel electrodes, and a horizontal electric field is generated between adjacent pixel electrodes. Due to this lateral electric field, striped stripe irregularities are likely to occur along the inside of one edge of the pixel electrode. The protrusion is formed on at least one second substrate in the band-like region, and suppresses the occurrence of stripe unevenness.
[0022]
The protrusion is formed in a non-opening region between the plurality of pixel electrodes.
[0023]
According to such a configuration, the aperture ratio is not lowered by the protrusion, and the occurrence of streak unevenness can be prevented and a high aperture ratio can be displayed.
[0024]
Further, the protrusion is formed over at least the entire width of the belt-like region.
[0025]
According to such a structure, generation | occurrence | production of a stripe unevenness can be reliably prevented by the protrusion.
[0026]
The protrusion is formed in a pole shape.
[0027]
According to such a configuration, it is possible to form a protrusion having a relatively high size relatively easily, and it is possible to reliably prevent the occurrence of stripe unevenness.
[0028]
The protrusion is a non-opening region between the plurality of pixel electrodes, and is formed in a stripe shape in a direction perpendicular to the longitudinal direction of the band-like region.
[0029]
According to such a configuration, one stripe-like protrusion extends over a plurality of band-like regions in the entire width direction, and the protrusion can be formed at all locations where stripe unevenness is likely to occur relatively easily. .
[0030]
In addition, an upper end of the protrusion is in contact with the second substrate.
[0031]
According to such a configuration, the occurrence of streak irregularity can be reliably prevented by the sufficiently high-sized protrusion.
[0032]
The protrusion is formed below the alignment film formed on the first and second substrates in contact with the electro-optical material.
[0033]
According to such a configuration, the protrusion can be formed under the alignment film by using, for example, a semiconductor process.
[0034]
The protrusion may be formed on the first and second substrates above an alignment film formed in contact with the electro-optic material.
[0035]
According to such a configuration, the protrusion can be formed above the alignment film by using, for example, a semiconductor process or a printing technique.
[0036]
The insulating layer below the alignment film is a planarized insulating film.
[0037]
According to such a configuration, it is possible to easily obtain good rubbing by flattening and to surely prevent the occurrence of stripe unevenness.
[0038]
An electrical apparatus according to the present invention is configured using the electro-optical device.
[0039]
According to such a configuration, it is possible to prevent the occurrence of stripe unevenness and display a high-quality image.
[0040]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a schematic plan view showing an electro-optical device according to an embodiment of the present invention. This embodiment is applied to a liquid crystal device using a TFT substrate. FIG. 2 is a plan view of the liquid crystal device, which is the electro-optical device of the present embodiment, viewed from the counter substrate side together with the components formed thereon. FIG. 3 is a cross-sectional view of the liquid crystal device after the assembly process in which the TFT substrate, which is an active matrix substrate, and the counter substrate are bonded together to enclose the liquid crystal is completed, cut along the line HH ′ in FIG. . FIG. 4 is an equivalent circuit diagram of various elements, wirings, and the like in a plurality of pixels constituting the pixel region of the liquid crystal device that is the electro-optical device of the present embodiment. FIG. 5 is a cross-sectional view showing in detail the pixel structure of the liquid crystal device of FIGS. FIG. 6 is an explanatory diagram schematically showing a cross section of the liquid crystal device in the present embodiment. In each of the above drawings, the scale is different for each layer and each member so that each layer and each member can be recognized in the drawing.
[0041]
This embodiment is a position corresponding to the edge of the pixel electrode that is affected by the lateral electric field on the TFT substrate, and is a protrusion for suppressing the disorder of the continuous arrangement of liquid crystal molecules at a position other than the opening region. By forming the portion, the occurrence of uneven horizontal stripes is prevented.
[0042]
First, an overall configuration of a liquid crystal device which is an electro-optical device according to the present embodiment will be described with reference to FIGS.
As shown in FIGS. 2 and 3, the liquid crystal device includes a TFT substrate 10 made of, for example, a quartz substrate, a glass substrate, or a silicon substrate, and a counter substrate 20 made of, for example, a glass substrate or a quartz substrate. The liquid crystal 50 is sealed between the two. The TFT substrate 10 and the counter substrate 20 that are arranged to face each other are bonded together by a sealing material 52.
[0043]
On the TFT substrate 10, pixel electrodes (ITO) 9a constituting pixels are arranged in a matrix. A counter electrode (ITO) 21 is provided on the entire surface of the counter substrate 20. On the pixel electrode 9 a of the TFT substrate 10, an alignment film 16 that has been subjected to a rubbing process is provided. On the other hand, an alignment film 22 subjected to a rubbing process is also provided on the counter electrode 21 formed over the entire surface of the counter substrate 20. The alignment films 16 and 22 are made of a transparent organic film such as a polyimide film, for example.
[0044]
FIG. 4 shows an equivalent circuit of elements on the TFT substrate 10 constituting the pixel. As shown in FIG. 4, in the pixel region, a plurality of scanning lines 11a and a plurality of data lines 6a are wired so as to cross each other, and a pixel electrode is formed in a region partitioned by the scanning lines 11a and the data lines 6a. 9a are arranged in a matrix. A TFT 30 is provided corresponding to each intersection of the scanning line 11 a and the data line 6 a, and the pixel electrode 9 a is connected to the TFT 30.
[0045]
The TFT 30 is turned on by the ON signal of the scanning line 11a, whereby the image signal supplied to the data line 6a is supplied to the pixel electrode 9a. A voltage between the pixel electrode 9 a and the counter electrode 21 provided on the counter substrate 20 is applied to the liquid crystal 50. In addition, a storage capacitor 70 is provided in parallel with the pixel electrode 9a, and the storage capacitor 70 makes it possible to hold the voltage of the pixel electrode 9a for a time that is, for example, three orders of magnitude longer than the time when the source voltage is applied. The storage capacitor 70 improves the voltage holding characteristic and enables image display with a high contrast ratio.
[0046]
A plurality of pixel electrodes 9a are provided in a matrix on the TFT substrate 10, and data lines 6a and scanning lines 11a are provided along the vertical and horizontal boundaries of the pixel electrodes 9a. As will be described later, the data line 6a has a laminated structure including an aluminum film, and the scanning line 11a is made of, for example, a conductive polysilicon film. The scanning line 11a is electrically connected to a gate electrode 3a facing a channel region 1a ′ described later. That is, the pixel switching TFT 30 is configured by disposing the gate electrode 3a connected to the scanning line 11a and the channel region 1a ′ so as to face each other at the intersection of the scanning line 11a and the data line 6a.
[0047]
FIG. 1 shows some pixel electrodes 9a arranged in a matrix. As described above, the data line 6a and the scanning line 11a are provided along the vertical and horizontal boundaries of the pixel electrode 9a. 1 indicates a pixel electrode to which a positive driving voltage for line inversion driving is applied at a predetermined timing, and − indicates a pixel electrode to which a negative driving voltage for line inversion driving is applied at a predetermined timing. Is shown. The positive and negative drive voltages are represented as positive or negative with the center voltage of the drive voltage as a reference voltage, and the reference voltage is not limited to 0V.
[0048]
A range E indicated by an arrow in FIG. 1 indicates a range of a portion affected by a lateral electric field in the line inversion driving method. In the range E that receives the horizontal electric field, the range in which horizontal stripe unevenness occurs due to the rubbing direction or the like is a range F indicated by an arrow in FIG.
[0049]
In the present embodiment, at least a range G (band-like region) adjacent to the pixel electrode 9a in one end portion of the pixel electrode 9a and in a range F in which streak unevenness occurs due to the influence of a lateral electric field in the line inversion driving method. Is configured to form a protrusion 111 (shaded portion) in a non-opening region. FIG. 1 shows an example in which the protrusion 111 is provided on the data line which is a non-opening region.
[0050]
In FIG. 1, the protrusions 111 are formed in the range G on the data line. However, the protrusions 111 may be formed in a range wider than the range G as long as the range G is included. Furthermore, although the protrusion 111 has been described as being formed in the non-opening region, the protrusion 111 may be applied to the end on the pixel electrode 9a as long as a slight decrease in the aperture ratio is allowed.
[0051]
In FIG. 1, the protrusions 111 are formed at positions adjacent to one corner of all the pixel electrodes 9 a, but one or more protrusions 111 are formed on the extension of the band-like region where the stripe unevenness of each line occurs. Thus, there is an effect of suppressing the unevenness of the stripes to some extent.
[0052]
FIG. 6 schematically shows a cross section taken along the line AA of FIG. The protrusion 111 is formed so as to protrude from the surface on the TFT substrate 10 toward the counter substrate 20. The protrusion 111 is such that the height of the member (the protrusion 111 or the alignment film 16) facing the liquid crystal layer 50 is higher than the height of the alignment film 16 on the pixel electrode 9a at the position where the protrusion 111 is formed. Yes, the height of the protrusion 111 may be set to a height that is equal to or higher than the height at which unevenness due to the influence of the transverse electric field can be suppressed.
[0053]
Further, the protrusion 111 may be formed below the alignment film 16 or may be formed above the alignment film 16. It is also conceivable that the alignment film 16 may not be formed in the region where the protrusion 111 is formed. Further, the protrusion 111 may be formed to a height at which the upper surface thereof is in contact with the alignment film 22 of the counter substrate 20.
[0054]
The protrusion 111 can be formed by printing or baking a resin or the like. Alternatively, it can also be formed by a semiconductor process film formation or a photolithography process. For example, the protrusion 111 can be formed below the alignment film 16 by using a semiconductor process, and can also be formed above the alignment film 16 by using a semiconductor process. Further, when the protrusion 111 is formed above the alignment film 16, a rubbing process may be performed after the protrusion 111 is formed. The protrusion 111 may be formed on the alignment film 16 after the rubbing process is performed on the alignment film 16. May be formed.
[0055]
Furthermore, even if the protrusions are formed on the counter substrate 20 side, a certain degree of stripe unevenness suppression effect can be obtained. That is, in this case, in the plan view, the protrusions are formed at the corresponding positions on the counter substrate 20 side, on the extension of the band-like region where the stripe unevenness due to the transverse electric field is likely to occur.
[0056]
FIG. 7 schematically shows a cross section in this case. In FIG. 7, the protrusion 112 is formed to protrude from the surface of the counter substrate 20 toward the TFT substrate 10. The protrusion 112 is formed on the counter substrate 20 facing the formation position of the protrusion 111 in FIG. 6, for example, above or below the alignment film 22. Since the protrusion 112 is formed in the band-like region where the stripe unevenness due to the influence of the lateral electric field is likely to occur, the occurrence of the stripe unevenness can be suppressed.
[0057]
Further, a portion higher than the alignment film 16 on the pixel electrode 9a may be formed in the middle of the strip-shaped region where stripe unevenness is likely to occur, and various shapes of the protrusions are conceivable.
[0058]
FIG. 8 is an explanatory view showing an example in which a pole-shaped protrusion is employed. FIG. 8 schematically shows the planar shape of the liquid crystal device. The protrusions 113 are formed in a pole shape at a plurality of locations in the middle of the belt-shaped region where stripe unevenness is likely to occur. For example, the pole-shaped protrusion 113 can be formed by printing or baking a resin or the like.
[0059]
Moreover, FIG. 9 is explanatory drawing which shows the example which employ | adopted the strip | belt-shaped thing as a protrusion. FIG. 9 schematically shows the planar shape of the liquid crystal device. The protrusion 114 has, for example, a band shape along the data line. That is, the protrusion 114 is also formed at a plurality of locations in the middle of the band-like region where stripe unevenness is likely to occur, and the occurrence of stripe unevenness can be suppressed.
[0060]
FIG. 5 is a schematic cross-sectional view of a liquid crystal device that is an electro-optical device focusing on one pixel. FIG. 5 shows an example in which the protrusion 111 is formed on the alignment film 16.
[0061]
On the TFT substrate 10, in addition to the TFT 30 and the pixel electrode 9a, various configurations including these are provided in a laminated structure. As shown in FIG. 5, this stacked structure includes a first layer (film formation layer) including the scanning line 11a, a second layer including the TFT 30 including the gate electrode 3a, and a third layer including the storage capacitor 70 in order from the bottom. A fourth layer including the data line 6a, a fifth layer including the shield layer 400, and a sixth layer (uppermost layer) including the pixel electrode 9a and the alignment film 16 and the like. Further, the base insulating film 12 is provided between the first layer and the second layer, the first interlayer insulating film 41 is provided between the second layer and the third layer, and the second interlayer insulating film 42 is provided between the third layer and the fourth layer. A third interlayer insulating film 43 is provided between the fourth layer and the fifth layer, and a fourth interlayer insulating film 44 is provided between the fifth layer and the sixth layer, so that the above-described elements are short-circuited. Is preventing. Further, these various insulating films 12, 41, 42, 43 and 44 are also provided with, for example, a contact hole for electrically connecting the high concentration source region 1d in the semiconductor layer 1a of the TFT 30 and the data line 6a. It has been.
Hereinafter, each of these elements will be described in order from the bottom.
[0062]
The first layer includes, for example, a simple metal, an alloy containing at least one of refractory metals such as Ti (titanium), Cr (chromium), W (tungsten), Ta (tantalum), and Mo (molybdenum). A scanning line 11a made of metal silicide, polysilicide, a laminate of these, or conductive polysilicon is provided.
The scanning line 11a is planarly patterned in a stripe shape and has a protruding portion along the data line 6a. Note that the protrusions extending from the adjacent scanning lines 11a are not connected to each other, and therefore the scanning lines 11a are divided one by one.
[0063]
Thus, the scanning line 11a has a function of simultaneously controlling ON / OFF of the TFTs 30 existing in the same row. In addition, since the scanning line 11a is formed so as to substantially fill a region where the pixel electrode 9a is not formed, it also has a function of blocking light entering the TFT 30 from below. Thereby, generation of light leakage current in the semiconductor layer 1a of the TFT 30 is suppressed, and high-quality image display without flicker or the like is possible.
[0064]
In the second layer, the TFT 30 including the gate electrode 3a is provided. As shown in FIG. 5, the TFT 30 has an LDD (Lightly Doped Drain) structure, and includes the above-described gate electrode 3a, for example, a polysilicon film, and the channel is formed by the electric field from the gate electrode 3a. The channel region 1a ′ of the semiconductor layer 1a to be formed, the insulating film 2 including a gate insulating film that insulates the gate electrode 3a from the semiconductor layer 1a, the low concentration source region 1b and the low concentration drain region 1c in the semiconductor layer 1a, and the high concentration. A source region 1d and a high concentration drain region 1e are provided.
[0065]
In the second layer, a relay electrode 719 is formed as the same film as the gate electrode 3a described above. The relay electrode 719 is formed in an island shape so as to be positioned approximately at the center of one side of each pixel electrode 9a when seen in a plan view. Since the relay electrode 719 and the gate electrode 3a are formed as the same film, when the latter is made of a conductive polysilicon film or the like, the former is also made of a conductive polysilicon film or the like.
[0066]
The above-described TFT 30 preferably has an LDD structure as shown in FIG. 5, but may have an offset structure in which impurities are not implanted into the low-concentration source region 1b and the low-concentration drain region 1c. A self-aligned TFT that implants impurities at a high concentration as a mask and forms a high concentration source region and a high concentration drain region in a self-aligning manner may be used. In the present embodiment, only one gate electrode of the pixel switching TFT 30 is disposed between the high-concentration source region 1d and the high-concentration drain region 1e. However, two or more gates are interposed between these gate electrodes. An electrode may be arranged. If the TFT is configured with dual gates or triple gates or more in this way, leakage current at the junction between the channel and the source and drain regions can be prevented, and the current during OFF can be reduced.
Further, the semiconductor layer 1a constituting the TFT 30 may be a non-single crystal layer or a single crystal layer. A known method such as a bonding method can be used for forming the single crystal layer. By making the semiconductor layer 1a a single crystal layer, it is possible to improve the performance of peripheral circuits in particular.
[0067]
A base insulating film 12 made of, for example, a silicon oxide film is provided on the scanning line 11a described above and below the TFT 30. In addition to the function of insulating the scanning line 11a and the TFT 30, the base insulating film 12 is formed on the entire surface of the TFT substrate 10 so that pixel switching due to roughness during polishing of the surface of the TFT substrate 10 or dirt remaining after cleaning is performed. The TFT 30 has a function of preventing characteristic changes.
[0068]
In the base insulating film 12, grooves (contact holes) 12cv having the same width as the channel length of the semiconductor layer 1a extending along the data line 6a described later are dug on both sides of the semiconductor layer 1a in plan view. Corresponding to the groove 12cv, the gate electrode 3a stacked above includes a portion formed in a concave shape on the lower side. Further, since the gate electrode 3a is formed so as to fill the entire groove 12cv, a side wall portion 3b formed integrally with the gate electrode 3a is extended. Yes. As a result, the semiconductor layer 1a of the TFT 30 is covered from the side as viewed in a plan view, and at least light from this portion is prevented from entering.
[0069]
Further, the side wall 3b is formed so as to fill the groove 12cv and so that the lower end thereof is in contact with the scanning line 11a. Accordingly, the scanning line 11a and the gate electrode 3a in the same row have the same potential. A structure in which another scanning line including the gate electrode 3a is formed so as to be parallel to the scanning line 11a may be employed. In this case, the scanning line 11a and the other scanning line have a redundant wiring structure. Thereby, for example, even when a part of the scanning line 11a has some defect and normal energization is impossible, another scanning line in the same row as the scanning line 11a is not present. As long as it is sound, the operation control of the TFT 30 can still be normally performed through the soundness.
[0070]
In the third layer, a storage capacitor 70 is provided. The storage capacitor 70 includes a lower electrode 71 as a pixel potential side capacitor electrode connected to the high concentration drain region 1e of the TFT 30 and the pixel electrode 9a, and a capacitor electrode 300 as a fixed potential side capacitor electrode. It is formed by arrange | positioning through. According to the storage capacitor 70, it is possible to remarkably improve the potential holding characteristic in the pixel electrode 9a.
Further, since the storage capacitor 70 is formed so as not to reach the light transmission region substantially corresponding to the formation region of the pixel electrode 9a (in other words, formed so as to be within the light shielding region), The pixel aperture ratio of the entire electro-optical device is kept relatively large, and thus a brighter image can be displayed.
[0071]
More specifically, the lower electrode 71 is made of, for example, a conductive polysilicon film and functions as a pixel potential side capacitor electrode. However, the lower electrode 71 may be composed of a single layer film or a multilayer film containing a metal or an alloy. In addition to the function as a pixel potential side capacitor electrode, the lower electrode 71 has a function of relay-connecting the pixel electrode 9a and the high concentration drain region 1e of the TFT 30. This relay connection is performed via the relay electrode 719 as described later.
[0072]
The capacitor electrode 300 functions as a fixed potential side capacitor electrode of the storage capacitor 70. In order to set the capacitor electrode 300 to a fixed potential, the capacitor electrode 300 is electrically connected to a shield layer 400 described later, which is set to a fixed potential.
[0073]
The capacitor electrode 300 is formed in an island shape on the TFT substrate 10 so as to correspond to each pixel, and the lower electrode 71 is formed to have substantially the same shape as the capacitor electrode 300. . As a result, the storage capacitor 70 does not have a wasteful spread in a plane, that is, without decreasing the pixel aperture ratio, and can achieve the maximum capacitance value under the circumstances. That is, the storage capacitor 70 has a smaller area and a larger capacitance value.
[0074]
As shown in FIG. 5, the dielectric film 75 is, for example, a relatively thin HTO (High Temperature oxide) film having a film thickness of about 5 to 200 nm, a silicon oxide film such as an LTO (Low Temperature oxide) film, or a silicon nitride film. Consists of From the viewpoint of increasing the storage capacitor 70, the thinner the dielectric film 75 is, the better as long as the reliability of the film is sufficiently obtained. As shown in FIG. 5, the dielectric film 75 has a two-layer structure including a silicon oxide film 75a in the lower layer and a silicon nitride film 75b in the upper layer. The presence of the silicon nitride film 75b having a relatively large dielectric constant makes it possible to increase the capacitance value of the storage capacitor 70, and the presence of the silicon oxide film 75a reduces the pressure resistance of the storage capacitor 70. I won't let you down. Thus, by making the dielectric film 75 have a two-layer structure, it is possible to enjoy two conflicting effects.
[0075]
In addition, the presence of the silicon nitride film 75b makes it possible to prevent water from entering the TFT 30 in advance. As a result, a situation in which the threshold voltage of the TFT 30 rises is not caused, and a relatively long-term apparatus operation is possible. In the present embodiment, the dielectric film 75 has a two-layer structure. However, the dielectric film 75 has a three-layer structure such as a silicon oxide film, a silicon nitride film, and a silicon oxide film, or more. You may comprise so that it may have the laminated structure of these.
[0076]
On the TFT 30 to the gate electrode 3a and the relay electrode 719 described above and below the storage capacitor 70, for example, NSG (non-silicate glass), PSG (phosphosilicate glass), BSG (boron silicate glass), BPSG ( A silicate glass film such as boron phosphorus silicate glass), a silicon nitride film, a silicon oxide film, or the like, or a first interlayer insulating film 41 preferably made of NSG is formed. In the first interlayer insulating film 41, a contact hole 81 that electrically connects the high-concentration source region 1d of the TFT 30 and a data line 6a described later opens while penetrating the second interlayer insulating film 42 described later. It is holed. The first interlayer insulating film 41 is provided with a contact hole 83 that electrically connects the high-concentration drain region 1 e of the TFT 30 and the lower electrode 71 constituting the storage capacitor 70.
[0077]
Further, the first interlayer insulating film 41 is provided with a contact hole 881 for electrically connecting the lower electrode 71 serving as a pixel potential side capacitor electrode constituting the storage capacitor 70 and the relay electrode 719. . In addition, a contact hole 882 that electrically connects the relay electrode 719 and a second relay electrode 6a2 described later is formed in the first interlayer insulating film 41 while penetrating the second interlayer insulating film 42 described later. Has been.
[0078]
As shown in FIG. 5, the contact hole 882 is formed in a region other than the storage capacitor 70, and the lower electrode 71 is once detoured to the lower relay electrode 719 and drawn out to the upper layer through the contact hole 882. Therefore, even when the lower electrode 71 is connected to the upper pixel electrode 9 a, it is not necessary to form the lower electrode 71 wider than the dielectric film 75 and the capacitor electrode 300. Therefore, the lower electrode 71, the dielectric film 75, and the capacitor electrode 300 can be simultaneously patterned in one etching process. As a result, the etching rates of the lower electrode 71, the dielectric film 75, and the capacitor electrode 300 can be easily controlled, and the degree of freedom in designing the film thickness and the like can be increased.
[0079]
In addition, since the dielectric film 75 is formed in the same shape as the lower electrode 71 and the capacitor electrode 300 and does not have a spread, in the case of performing a hydrogenation process on the semiconductor layer 1 a of the TFT 30, It is also possible to obtain an effect that it is possible to easily reach the semiconductor layer 1a through the opening around the storage capacitor 70.
[0080]
The first interlayer insulating film 41 may be fired at about 1000 ° C. to activate ions implanted into the polysilicon film constituting the semiconductor layer 1a and the gate electrode 3a.
[0081]
A data line 6a is provided in the fourth layer. The data line 6a is formed in a stripe shape so as to coincide with the extending direction of the semiconductor layer 1a of the TFT 30. As shown in FIG. 5, the data line 6a includes, in order from the lower layer, a layer made of aluminum (reference numeral 41A in FIG. 5), a layer made of titanium nitride (see reference numeral 41TN in FIG. 5), and a layer made of a silicon nitride film (see FIG. The film is formed as a film having a three-layer structure 401) in FIG. The silicon nitride film is patterned to a slightly larger size so as to cover the lower aluminum layer and titanium nitride layer. Of these, the data line 6a contains aluminum, which is a relatively low resistance material, so that the supply of image signals to the TFT 30 and the pixel electrode 9a can be realized without delay. On the other hand, the formation of a silicon nitride film that is relatively excellent in preventing moisture from entering on the data line 6a can improve the moisture resistance of the TFT 30, and can achieve a long life. The silicon nitride film is preferably a plasma silicon nitride film.
[0082]
In addition, a shield layer relay layer 6a1 and a second relay electrode 6a2 are formed on the fourth layer as the same film as the data line 6a. These are not formed so as to have a planar shape continuous with the data line 6a when viewed in plan, but are formed so as to be divided by patterning. That is, when paying attention to the data line 6a, the shield layer relay layer 6a1 having a substantially quadrilateral shape on the right side thereof, and further having a substantially quadrilateral shape having an area slightly larger than that of the shield layer relay layer 6a1 on the right side thereof. A second relay electrode 6a2 is formed. The shield layer relay layer 6a1 and the second relay electrode 6a2 are in the same process as the data line 6a, and have a three-layer structure of an aluminum layer, a titanium nitride layer, and a plasma nitride film layer in order from the lower layer. It is formed as. The plasma nitride film is patterned to a slightly larger size so as to cover the lower aluminum layer and titanium nitride layer. The titanium nitride layer functions as a barrier metal for preventing etching through of the contact holes 803 and 804 formed for the shield layer relay layer 6a1 and the second relay electrode 6a2. Further, by forming a plasma nitride film that is relatively excellent in the action of blocking moisture ingress on the shield layer relay layer 6a1 and the second relay electrode 6a2, the moisture resistance of the TFT 30 can be improved. Longer service life can be realized. The plasma nitride film is preferably a plasma silicon nitride film.
[0083]
Above the storage capacitor 70 and below the data line 6a, for example, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like, or preferably a plasma CVD method using TEOS gas A second interlayer insulating film 42 formed by the above is formed. In the second interlayer insulating film 42, a contact hole 81 for electrically connecting the high concentration source region 1d of the TFT 30 and the data line 6a is opened, and the shield layer relay layer 6a1 and the storage capacitor 70 are formed. A contact hole 801 is formed to electrically connect the capacitor electrode 300, which is the upper electrode. Further, a contact hole 882 for electrically connecting the second relay electrode 6a2 and the relay electrode 719 is formed in the second interlayer insulating film.
[0084]
A shield layer 400 is formed on the fifth layer. The shield layer 400 is formed in a lattice shape in plan view. A portion of the shield layer 400 that extends in the direction along the data line 6a is formed so as to cover the data line 6a and wider than the data line 6a. Further, the portion extending in the direction along the scanning line 11a has a notch portion near the center of one side of each pixel electrode 9a in order to secure a region for forming a third relay electrode 402 described later. Yes.
[0085]
Furthermore, at the corner of the intersecting portion of the shield layer 400, a substantially triangular portion is provided so as to fill the corner. By providing the substantially triangular portion on the shield layer 400, it is possible to effectively shield light from the semiconductor layer 1a of the TFT 30. That is, the light entering the semiconductor layer 1a obliquely from above is reflected or absorbed by the triangular portion and does not reach the semiconductor layer 1a. Therefore, it is possible to suppress the occurrence of light leakage current and display a high-quality image without flicker or the like.
[0086]
The shield layer 400 extends from the image display region 10a in which the pixel electrode 9a is disposed to the periphery thereof, and is electrically connected to a constant potential source to have a fixed potential. The constant potential source may be a positive potential source or a negative potential constant source supplied to the data line driving circuit 101 described later, or a constant potential source supplied to the counter electrode 21 of the counter substrate 20.
[0087]
In this way, the presence of the shield layer 400 that is formed so as to cover the entire data line 6a and has a fixed potential can reduce the influence of capacitive coupling generated between the data line 6a and the pixel electrode 9a. It becomes possible to eliminate. That is, it is possible to avoid a situation in which the potential of the pixel electrode 9a fluctuates in response to the energization of the data line 6a, and the possibility of causing display unevenness along the data line 6a on the image. Can be reduced. Since the shield layer 400 is formed in a lattice shape, it is possible to suppress this so that unnecessary capacitance coupling does not occur in the portion where the scanning line 11a extends.
[0088]
Further, a third relay electrode 402 as a relay layer is formed on the fourth layer as the same film as the shield layer 400. The third relay electrode 402 has a function of relaying an electrical connection between the second relay electrode 6a2 and the pixel electrode 9a through a contact hole 89 described later. The shield layer 400 and the third relay electrode 402 are not continuously formed in a planar shape, but are formed so as to be separated by patterning.
[0089]
On the other hand, the shield layer 400 and the third relay electrode 402 described above have a two-layer structure in which a lower layer is made of aluminum and an upper layer is made of titanium nitride. In the third relay electrode 402, the lower layer made of aluminum is connected to the second relay electrode 6a2, and the upper layer made of titanium nitride is connected to the pixel electrode 9a made of ITO or the like. Yes. When aluminum and ITO are directly connected, electric corrosion occurs between the two, and preferable electrical connection cannot be realized due to disconnection of aluminum or insulation due to formation of alumina. On the other hand, since titanium nitride and ITO are connected, contact resistance is low and good connectivity is obtained.
[0090]
As described above, since the electrical connection between the third relay electrode 402 and the pixel electrode 9a can be satisfactorily realized, the voltage application to the pixel electrode 9a or the potential holding characteristic in the pixel electrode 9a is maintained well. It becomes possible.
[0091]
Furthermore, since the shield layer 400 and the third relay electrode 402 include aluminum that is relatively excellent in light reflection performance and include titanium nitride that is relatively excellent in light absorption performance, the shield layer 400 and the third relay electrode 402 can function as a light shielding layer. That is, according to these, it is possible to block the progress of incident light (see FIG. 5) on the semiconductor layer 1a of the TFT 30 on the upper side. Such a light shielding function can be similarly applied to the capacitor electrode 300 and the data line 6a described above. The shield layer 400, the third relay electrode 402, the capacitor electrode 300, and the data line 6 a form an upper light-shielding film that blocks light incident on the TFT 30 from the upper side while forming a part of the laminated structure constructed on the TFT substrate 10. Function.
[0092]
Over the data line 6a and under the shield layer 400, a silicate glass film such as NSG, PSG, BSG, BPSG, a silicon nitride film, a silicon oxide film, or the like, or preferably a plasma CVD method using TEOS gas A third interlayer insulating film 43 is formed. In the third interlayer insulating film 43, a contact hole 803 for electrically connecting the shield layer 400 and the shield layer relay layer 6a1, and a third relay electrode 402 and the second relay electrode 6a2 are electrically connected. Contact holes 804 for connecting to each are opened.
[0093]
The second interlayer insulating film 42 may be relieved of stress generated in the vicinity of the interface of the capacitor electrode 300 by not performing the above-described firing with respect to the first interlayer insulating film 41.
[0094]
In the sixth layer, the pixel electrodes 9a are formed in a matrix as described above, and the alignment film 16 is formed on the pixel electrodes 9a. Under the pixel electrode 9a, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like, or preferably plasma formed by plasma CVD using TEOS gas is used. A fourth interlayer insulating film 44 made of TEOS is formed. In the fourth interlayer insulating film 44, a contact hole 89 for electrically connecting the pixel electrode 9a and the third relay electrode 402 is opened.
[0095]
The surfaces of the third and fourth interlayer insulating films 43 and 44 are planarized by a CMP (Chemical Mechanical Polishing) process or the like. Alignment defects of the liquid crystal layer 50 due to steps due to various wirings, elements, etc. existing below the planarized interlayer insulating films 43 and 44 are reduced. However, instead of or in addition to performing the planarization process on the third and fourth interlayer insulating films 43 and 44 in this way, the TFT substrate 10, the base insulating film 12, the first interlayer insulating film 41, and the second interlayer A planarization process may be performed by digging a groove in at least one of the insulating film 42 and the third interlayer insulating film 43 and embedding a wiring such as the data line 6a or the TFT 30 or the like.
[0096]
In addition, the storage capacitor 70 has a three-layer structure of a pixel potential side capacitor electrode, a dielectric film, and a fixed potential side capacitor electrode in order from the bottom, but may have a structure opposite to this. .
[0097]
In the present embodiment, a region on the planarized alignment film 16 adjacent to one corner of the pixel electrode 9a and in which stripe unevenness due to the influence of a lateral electric field is likely to occur is not projected. A portion 111 is formed.
[0098]
On the other hand, as shown in FIGS. 2 and 3, the counter substrate 20 is provided with a light shielding film 53 as a frame for partitioning the display area. As described above, a transparent conductive film such as ITO is formed on the entire surface of the counter substrate 20 as the counter electrode 21, and a polyimide-based alignment film 22 is formed on the entire surface of the counter electrode 21. The alignment film 22 is rubbed in a predetermined direction so as to give a predetermined pretilt angle to the liquid crystal molecules.
[0099]
In a region outside the light shielding film 53, a sealing material 52 that encloses liquid crystal is formed between the TFT substrate 10 and the counter substrate 20. The sealing material 52 is disposed so as to substantially match the contour shape of the counter substrate 20, and fixes the TFT substrate 10 and the counter substrate 20 to each other.
The sealing material 52 is missing at a part of one side of the TFT substrate 10, and a liquid crystal injection port 108 for injecting the liquid crystal 50 is formed in the gap between the TFT substrate 10 and the counter substrate 20 that are bonded together. The After the liquid crystal is injected from the liquid crystal injection port 108, the liquid crystal injection port 108 is sealed with a sealing material 109.
[0100]
In an area outside the sealing material 52, an image signal is supplied to the data line 6a at a predetermined timing to drive the data line 6a and an external connection terminal 102 for connection to an external circuit. Are provided along one side of the TFT substrate 10. A scanning line driving circuit 104 that drives the gate electrode 3a by supplying a scanning signal to the scanning line 11a and the gate electrode 3a at a predetermined timing is provided along two sides adjacent to the one side. The scanning line driving circuit 104 is formed on the TFT substrate 10 at a position facing the light shielding film 53 inside the sealing material 52. On the TFT substrate 10, wiring 105 connecting the data line driving circuit 101, the scanning line driving circuit 104, the external connection terminal 102, and the vertical conduction terminal 107 is provided to face the three sides of the light shielding film 53. Yes.
[0101]
The vertical conduction terminals 107 are formed on the four TFT substrates 10 at the corners of the sealing material 52. Between the TFT substrate 10 and the counter substrate 20, there is provided a vertical conductive material 106 whose lower end is in contact with the vertical conduction terminal 107 and whose upper end is in contact with the counter electrode 21. 10 and the counter substrate 20 are electrically connected.
[0102]
Also regarding the three-dimensional layout of each component, the present invention is not limited to the form as in the above embodiment, and various other forms can be considered.
[0103]
(Manufacturing process)
Next, a method for manufacturing a liquid crystal device, which is an electro-optical device according to this embodiment, will be described with reference to FIG. FIG. 10 shows a manufacturing method of each film formation layer.
[0104]
First, a TFT substrate 10 such as a quartz substrate, glass, or silicon substrate is prepared (step S1 in FIG. 10). Here, annealing is preferably performed at a high temperature of about 900 to 1300 ° C. in an inert gas atmosphere such as N (nitrogen), and pretreatment is performed so that distortion generated in the TFT substrate 10 is reduced in a high-temperature process performed later. Keep it.
[0105]
Next, a metal alloy film such as metal or metal silicide such as Ti, Cr, W, Ta, or Mo, or a metal alloy film such as metal silicide is formed on the entire surface of the TFT substrate 10 treated in this manner, and the film thickness is preferably about 100 to 500 nm. Is deposited to a thickness of 200 nm. Then, the metal alloy film is patterned by photolithography and etching to form a scanning line 11a having a stripe shape in plan view (step S2).
[0106]
Next, on the scanning line 11a, for example, TEOS (tetra-ethyl ortho-silicate) gas, TEB (tetra-ethyl boat rate) gas, TMOP (tetra-methyl oxy. A silicate glass film such as NSG (non-silicate glass), PSG (phosphorus silicate glass), BSG (boron silicate glass), BPSG (boron phosphorus silicate glass), silicon nitride film, silicon oxide film, etc. A base insulating film 12 made of, for example, is formed (step S3). The thickness of the base insulating film 12 is, for example, about 500 to 2000 nm.
[0107]
In the next step S4, the semiconductor layer 1a is formed. That is, first, low pressure CVD (for example, using a monosilane gas, a disilane gas, or the like at a flow rate of about 400 to 600 cc / min on a base insulating film 12 in a relatively low temperature environment of about 450 to 550 ° C., preferably about 500 ° C. An amorphous silicon film is formed by CVD at a pressure of about 20-40 Pa. Next, heat treatment is performed in a nitrogen atmosphere at about 600 to 700 ° C. for about 1 to 10 hours, preferably 4 to 6 hours, so that the p-Si (polysilicon) film has a thickness of about 50 to 200 nm. The solid phase growth is preferably performed until the thickness becomes about 100 nm. As a method for solid phase growth, annealing using RTA or laser annealing using an excimer laser or the like may be used. At this time, a dopant of a group V element or a group III element may be slightly doped by ion implantation or the like depending on whether the pixel switching TFT 30 is an n-channel type or a p-channel type. Then, a semiconductor layer 1a having a predetermined pattern is formed by photolithography and etching.
[0108]
Next, in step S5, the semiconductor layer 1a constituting the TFT 30 is thermally oxidized at a temperature of about 900 to 1300 ° C., preferably about 1000 ° C., to form a lower gate insulating film. Subsequently, an upper gate green film is formed by a low pressure CVD method or the like, thereby forming an insulating film 2 (including a gate insulating film) made of one or multiple layers of a high-temperature silicon oxide film (HTO film) or a silicon nitride film. . As a result, the semiconductor layer 1a has a thickness of about 30 to 150 nm, preferably about 35 to 50 nm, and the insulating film 2 has a thickness of about 20 to 150 nm, preferably about 30 to 100 nm. It becomes thickness.
[0109]
Next, in order to control the threshold voltage Vth of the TFT 30 for pixel switching, the n-channel region or the p-channel region of the semiconductor layer 1a is doped with a predetermined amount of a dopant such as boron by ion implantation or the like. To do.
[0110]
Next, a groove 12cv that communicates with the scanning line 11a is formed in the base insulating film 12. The groove 12cv is formed by dry etching such as reactive ion etching or reactive ion beam etching.
[0111]
Next, a polysilicon film is deposited by low pressure CVD or the like, and phosphorus (P) is further thermally diffused to make this polysilicon film conductive. Instead of this thermal diffusion, a doped silicon film in which P ions are introduced simultaneously with the formation of the polysilicon film may be used. The thickness of this polysilicon film is about 100 to 500 nm, preferably about 350 nm. Then, a gate electrode 3a having a predetermined pattern including the gate electrode portion of the TFT 30 is formed by photolithography and etching (step S6). When the gate electrode 3a is formed, a side wall 3b extending to the gate electrode 3a is also formed at the same time. The sidewall 3b is formed by depositing the polysilicon film described above also on the inside of the groove 12cv. At this time, since the bottom of the groove 12cv is in contact with the scanning line 11a, the side wall 3b and the scanning line 11a are electrically connected. Further, the relay electrode 719 is also formed simultaneously with the patterning of the gate electrode 3a.
[0112]
Next, a low concentration source region 1b and a low concentration drain region 1c, and a high concentration source region 1d and a high concentration drain region 1e are formed for the semiconductor layer 1a.
[0113]
Here, the case where the TFT 30 is an n-channel TFT having an LDD structure will be described. Specifically, first, in order to form the low concentration source region 1b and the low concentration drain region 1c, the gate electrode 3a is used as a mask. Dopant of group V elements such as P at a low concentration (for example, P ions of 1 to 3 × 10 ¹³ cm ₂ Dope). As a result, the semiconductor layer 1a under the gate electrode 3a becomes a channel region 1a ′. At this time, the gate electrode 3a serves as a mask, so that the low concentration source region 1b and the low concentration drain region 1c are formed in a self-aligned manner. Next, in order to form the high concentration source region 1d and the high concentration drain region 1e, a resist layer having a planar pattern wider than the gate electrode 3a is formed on the gate electrode 3a. Thereafter, a dopant of a group V element such as P is used at a high concentration (for example, P ions are added to 1 to 3 × 10 ¹⁵ / Cm ₂ Dope).
[0114]
In addition, it is not necessary to dope by dividing into two steps of low concentration and high concentration. For example, a TFT having an offset structure may be used without doping at a low concentration, or a self-aligned TFT may be formed by an ion implantation technique using P ions, B ions, or the like using the gate electrode 3a (gate electrode) as a mask. Good. By doping the impurities, the gate electrode 3a is further reduced in resistance.
[0115]
Next, a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, or an oxide film is formed on the gate electrode 3a by, for example, atmospheric pressure or low pressure CVD using TEOS gas, TEB gas, TMOP gas, or the like. A first interlayer insulating film 41 made of a silicon film is formed (step S7). The film thickness of the first interlayer insulating film 41 is, for example, about 500 to 2000 nm. Here, preferably, annealing is performed at a high temperature of about 800 ° C. to improve the film quality of the first interlayer insulating film 41.
[0116]
Next, in step S8, the contact hole 83 and the contact hole 881 are opened by dry etching such as reactive ion etching and reactive ion beam etching for the first interlayer insulating film 41. At this time, the former is formed so as to communicate with the high-concentration drain region 1e of the semiconductor layer 1a, and the latter is formed so as to communicate with the relay electrode 719.
[0117]
Next, in step S9, a metal film such as Pt or a polysilicon film is formed on the first interlayer insulating film 41 to a film thickness of about 100 to 500 nm by low pressure CVD or sputtering, and a predetermined pattern is formed. A metal film of the lower electrode 71 is formed. In this case, the metal film is formed so that both of the contact hole 83 and the contact hole 881 are filled, whereby the high-concentration drain region 1e, the relay electrode 719, and the lower electrode 71 are electrically connected. It is done.
[0118]
Next, a dielectric film 75 is formed on the lower electrode 71. The dielectric film 75 can be formed by various known techniques generally used for forming a TFT gate insulating film, as in the case of the insulating film 2. The silicon oxide film 75a is formed by the above-described thermal oxidation, CVD method or the like, and then the silicon nitride film 75b is formed by low pressure CVD method or the like. As the dielectric film 75 becomes thinner, the storage capacitor 70 becomes larger. Therefore, it is advantageous to form a very thin insulating film with a film thickness of 50 nm or less on the condition that no defects such as film breakage occur after all. It is. Next, a metal film such as a polysilicon film or AL (aluminum) is formed on the dielectric film 75 to a thickness of about 100 to 500 nm by low pressure CVD or sputtering, and the metal film of the capacitive electrode 300 is formed. Form.
[0119]
Next, the lower electrode 71, the dielectric film 75, and the capacitor electrode 300 are patterned at once to form the lower electrode 71, the dielectric film 75, and the capacitor electrode 300, and the storage capacitor 70 is completed.
[0120]
Next, for example, a normal glass or low pressure CVD method using TEOS gas or the like, preferably a plasma CVD method is used to form a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like. A two-layer insulating film 42 is formed (step S10). When aluminum is used for the capacitor electrode 300, it is necessary to form a film at a low temperature by plasma CVD. The film thickness of the second interlayer insulating film 42 is about 500 to 1500 nm, for example. Next, in step S11, contact holes 81, 801 and 882 are opened by dry etching such as reactive ion etching and reactive ion beam etching for the second interlayer insulating film. At this time, the contact hole 81 is formed so as to communicate with the high concentration source region 1d of the semiconductor layer 1a, the contact hole 801 is communicated with the capacitor electrode 300, and the contact hole 882 is formed so as to communicate with the relay electrode 719. The
[0121]
Next, in step S12, a thickness of about 100 to 500 nm is preferably formed on the entire surface of the second interlayer insulating film 42 by sputtering or the like using a low resistance metal such as light-shielding aluminum or metal silicide as a metal film. Deposits at about 300 nm. Then, the data line 6a having a predetermined pattern is formed by photolithography and etching. At this time, at the time of the patterning, the shield layer relay layer 6a1 and the second relay layer 6a2 are also formed at the same time. The shield layer relay layer 6a1 is formed to cover the contact hole 801, and the second relay layer 6a2 is formed to cover the contact hole 882.
[0122]
Next, after a film made of titanium nitride is formed on the entire surface of these upper layers by a plasma CVD method or the like, a patterning process is performed so that the film remains only on the data line 6a. However, the titanium nitride layer may be formed so as to remain on the shield layer relay layer 6a1 and the second relay layer 6a2, or may be formed so as to remain on the entire surface of the TFT substrate 10. Also good. Alternatively, the aluminum film may be formed at the same time as the aluminum film and etched in a lump.
[0123]
Next, a silicate such as NSG, PSG, BSG, or BPSG is formed so as to cover the data line 6a or the like, for example, by a normal pressure or low pressure CVD method using TEOS gas or the like, preferably by a plasma CVD method capable of forming a low temperature film. A third interlayer insulating film 43 made of a glass film, a silicon nitride film, a silicon oxide film or the like is formed (step S13). The film thickness of the third interlayer insulating film 43 is, eg, about 500-3500 nm.
[0124]
Next, in step S14, as shown in FIG. 5, the third interlayer insulating film 43 is planarized using, for example, CMP.
[0125]
Next, in step S15, contact holes 803 and 804 are opened by dry etching such as reactive ion etching or reactive ion beam etching for the third interlayer insulating film 43. At this time, the contact hole 803 is formed so as to communicate with the shield layer relay layer 6a1, and the contact hole 804 is formed so as to communicate with the second relay layer 6a2.
[0126]
Next, in step S16, a metal film of the shield layer 400 is formed on the third interlayer insulating film 43 by sputtering or plasma CVD.
Here, first, a lower layer film is formed directly on the third interlayer insulating film 43 by using a low resistance material such as aluminum, and then a pixel electrode 9a to be described later such as titanium nitride is formed on the lower layer film. An upper layer film is formed using a material that does not cause electric corrosion and ITO that constitutes, and finally, the lower layer film and the upper layer film are patterned together to form a shield layer 400 having a two-layer structure. At this time, the third relay electrode 402 is also formed together with the shield layer 400.
[0127]
Next, a fourth interlayer insulating film 44 made of a silicate glass film such as NSG, PSG, BSG, or BPSG, a silicon nitride film, a silicon oxide film, or the like is formed by, for example, atmospheric pressure or low pressure CVD using TEOS gas or the like. (Step S17). The film thickness of the fourth interlayer insulating film 44 is about 500 to 1500 nm, for example.
[0128]
Next, in step S18, as shown in FIG. 5, the fourth interlayer insulating film 44 is planarized using, for example, CMP. Next, a contact hole 89 is formed by dry etching such as reactive ion etching or reactive ion beam etching for the fourth interlayer insulating film 44 (step S19). At this time, the contact hole 89 is formed so as to communicate with the third relay electrode 402.
[0129]
Next, a transparent conductive film such as an ITO film is deposited on the fourth interlayer insulating film 44 to a thickness of about 50 to 200 nm by sputtering or the like. Then, the pixel electrode 9a is formed by photolithography and etching (step S20). When the electro-optical device is used as a reflection type, the pixel electrode 9a may be formed of an opaque material having a high reflectance such as AL. Next, in step S21, a polyimide alignment film coating solution is applied onto the pixel electrode 9a. Next, the alignment film 16 is formed by performing a rubbing process in a predetermined direction so as to have a predetermined pretilt angle.
[0130]
In the present embodiment, the protrusion 111 is formed in the next step S22. That is, a film of a predetermined material is formed on the alignment film 16. Next, the protrusion 111 is obtained by removing the other part of the film by photolithography and etching, leaving a region adjacent to one corner of the pixel electrode 9a where the stripe unevenness due to the influence of the lateral electric field is likely to occur. .
[0131]
In the description of FIG. 5, the example in which the protrusion 111 is formed after the rubbing process on the alignment film 16 is described. However, the rubbing process may be performed after the protrusion 111 is formed on the alignment film 16. . Further, as described above, the protrusion 111 is formed on the fourth interlayer insulating film 44 before the alignment film 16 is formed, and the alignment film 16 is formed on the pixel electrode 9a, the fourth interlayer insulating film 44, and the protrusion 111. However, it is preferable that the protrusion 111 is formed after the alignment film 16 is formed.
[0132]
On the other hand, for the counter substrate 20, a glass substrate or the like is first prepared, and a light shielding film 53 as a frame is formed through sputtering and photolithography and etching, for example. These light shielding films 53 do not have to be conductive, and may be formed of a material such as resin black in which carbon or Ti is dispersed in a photoresist in addition to a metal material such as Cr, Ni, or AL.
[0133]
Next, a counter electrode 21 is formed by depositing a transparent conductive film such as ITO to a thickness of about 50 to 200 nm by sputtering or the like on the entire surface of the counter substrate 20. Further, after the polyimide-based alignment film coating solution is applied to the entire surface of the counter electrode 21, the alignment film 22 is formed by performing a rubbing process in a predetermined direction so as to have a predetermined pretilt angle.
[0134]
Finally, as shown in FIGS. 2 and 3, the TFT substrate 10 and the counter substrate 20 on which the respective layers are formed, for example, form a seal material 52 along the four sides of the counter substrate 20, and The upper and lower conductive materials 106 are formed at the four corners, and the alignment films 16 and 22 are bonded together by the sealing material 52 so as to face each other. Thereby, the vertical conduction member 106 contacts the vertical conduction terminal 107 of the TFT substrate 10 at the lower end, and contacts the common electrode 21 of the counter substrate 20 at the upper end.
[0135]
It should be noted that even when a protrusion is formed on the counter substrate 20 side adjacent to one corner of the pixel electrode 9a where the unevenness due to the horizontal electric field is likely to occur and opposed to the region where the unevenness due to the horizontal electric field is likely to occur, FIG. The same process as step S22 is performed. For example, the protrusion 112 (see FIG. 7) is formed by forming the metal film for the black matrix formed on the counter substrate 20 side sufficiently thick at a position facing a region where stripe unevenness due to the influence of the lateral electric field is likely to occur. Can be formed.
[0136]
Then, a liquid crystal layer 50 having a predetermined thickness is formed by sucking, for example, liquid crystal formed by mixing a plurality of types of nematic liquid crystals into the space between both substrates by vacuum suction or the like.
[0137]
The sealing material 52 is made of, for example, an ultraviolet curable resin, a thermosetting resin, or the like, and is cured by ultraviolet rays, heating, or the like in order to bond the two substrates together. In addition, if the liquid crystal device according to the present embodiment is applied to a liquid crystal device in which the liquid crystal device is small and performs enlarged display like a projector, the distance between the substrates (inter-substrate gap) ) Is set to a predetermined value, and a glass fiber or a cap material (spacer) such as glass beads is dispersed. Alternatively, such a gap material may be included in the liquid crystal layer 50 if the liquid crystal device is applied to a large-sized liquid crystal device such as a liquid crystal display or a liquid crystal television that displays the same size. When the liquid crystal device is used, an FPC copper foil pattern is connected to the external connection terminal.
[0138]
Needless to say, if the delay of the scanning signal supplied to the scanning line 11a and the gate electrode 3a is not a problem, the scanning line driving circuit 104 may be only on one side. The data line driving circuit 101 may be arranged on both sides along the side of the image display area 10a.
[0139]
On the TFT substrate 10, in addition to the data line driving circuit 101, the scanning line driving circuit 104 and the like, a sampling circuit for applying an image signal to the plurality of data lines 6a at a predetermined timing, and a plurality of data lines 6a. In addition, a precharge circuit for supplying a precharge signal of a predetermined voltage level in advance of an image signal, an inspection circuit for inspecting quality, defects, etc. of the electro-optical device during manufacturing or at the time of shipment may be formed. Good.
[0140]
In the above-described embodiment, instead of providing the data line driving circuit 101 and the scanning line driving circuit 104 on the TFT substrate 10, for example, a driving LSI mounted on a TAB (Tape Automated Bonding) substrate is mounted on the TFT substrate. You may make it connect electrically and mechanically through the anisotropic conductive film provided in the 10 peripheral part. Further, on the side on which the projection light of the counter substrate 20 enters and on the side on which the emission light of the TFT substrate 10 exits, respectively, for example, TN (Twisted Nematic) mode, VA (Vertical Aligned) mode, PDLC (Polymer Dispersed Liquid Crystal). A polarizing film, a retardation film, a polarizing plate, and the like are arranged in a predetermined direction according to an operation mode such as a mode, or a normally white mode or a normally black mode.
[0141]
As described above, in the present embodiment, the protrusion 111 is formed in the non-opening region adjacent to the corner of the pixel electrode 9a in the band-shaped region in which the stripe unevenness easily occurs due to the influence of the horizontal electric field in the line inversion driving method. ing. This protrusion prevents the occurrence of continuous alignment failure of the liquid crystal molecules, thereby preventing streaking.
[0142]
In the above embodiment, an example in which the alignment film is applied to a liquid crystal device has been described. However, it is obvious that the present invention can be applied to a liquid crystal device in which the alignment film is not flattened. is there.
[0143]
(Electronics)
Next, an overall configuration, particularly an optical configuration, of an embodiment of a projection color display device as an example of an electronic apparatus using the electro-optical device described in detail as a light valve will be described. FIG. 11 is an explanatory diagram of a projection type color display device.
[0144]
In FIG. 11, a liquid crystal projector 1100, which is an example of a projection type color display device according to the present embodiment, prepares three liquid crystal modules including a liquid crystal device having a drive circuit mounted on a TFT array substrate, and each has RGB light bulbs 100R. , 100G and 100B. In the liquid crystal projector 1100, when projection light is emitted from a lamp unit 1102 of a white light source such as a metal halide lamp, light components R, G, and R corresponding to the three primary colors of RGB are obtained by three mirrors 1106 and two dichroic mirrors 1108. Divided into B, the light valves are guided to the light valves 100R, 100G and 100B corresponding to the respective colors. At this time, in particular, the B light is guided through a relay lens system 1121 including an incident lens 1122, a relay lens 1123, and an exit lens 1124 in order to prevent light loss due to a long optical path. The light components corresponding to the three primary colors modulated by the light valves 100R, 100G, and 100B are synthesized again by the dichroic prism 1112 and then projected as a color image on the screen 1120 via the projection lens 1114.
[0145]
The present invention is not limited to the above-described embodiment, and can be appropriately changed without departing from the spirit or idea of the invention that can be read from the claims and the entire specification.
[Brief description of the drawings]
FIG. 1 is a schematic plan view showing an electro-optical device according to an embodiment of the invention.
FIG. 2 is a plan view of a liquid crystal device, which is an electro-optical device according to the present embodiment, viewed from the counter substrate side together with the components formed thereon.
3 is a cross-sectional view of the liquid crystal device after being assembled at the end of the assembling process in which a TFT substrate, which is an active matrix substrate, and a counter substrate are bonded together to enclose liquid crystal, and cut along the line HH ′ in FIG.
FIG. 4 is an equivalent circuit diagram of various elements, wirings, and the like in a plurality of pixels constituting a pixel region of the liquid crystal device that is the electro-optical device of the present embodiment.
FIG. 5 is a cross-sectional view showing in detail a pixel structure of the liquid crystal device of FIGS. 1 to 4;
FIG. 6 is an explanatory diagram schematically showing a cross section of a liquid crystal device in this embodiment.
FIG. 7 is an explanatory diagram for explaining an example in which protrusions are formed on the counter substrate side.
FIG. 8 is an explanatory diagram showing an example in which a pole-shaped protrusion is adopted as the protrusion.
FIG. 9 is an explanatory view showing an example in which a belt-like member is adopted as a protrusion.
FIG. 10 is a flowchart showing a method for manufacturing a liquid crystal device which is an electro-optical device.
FIG. 11 is an explanatory diagram showing a projection type color display device.
FIG. 12 is an explanatory diagram schematically showing a pretilt of liquid crystal molecules when no voltage is applied.
FIG. 13 is an explanatory diagram schematically showing a planar shape of a liquid crystal device.
[Explanation of symbols]
6a ... data line, 9a ... pixel electrode, 11a ... scanning line, 111 ... projection.

Claims (11)

First and second substrates disposed opposite to each other;
A plurality of pixel electrodes disposed in a matrix on the first substrate, to which drive voltages having opposite polarities are applied to adjacent lines;
A common electrode provided on the second substrate;
An electro-optic material sandwiched between the first and second substrates;
The electro-optical material is affected by the electric field generated between the adjacent pixel electrodes by the drive voltage having the reverse polarity, and is at least one of the first regions in the band-like region along the inner side of one edge of the pixel electrode. An electro-optical device comprising a protrusion formed on the substrate. First and second substrates disposed opposite to each other;
A plurality of pixel electrodes disposed in a matrix on the first substrate, to which drive voltages having opposite polarities are applied to adjacent lines;
A common electrode provided on the second substrate;
An electro-optic material sandwiched between the first and second substrates;
The electro-optical material is affected by the electric field generated between the adjacent pixel electrodes by the drive voltage having the reverse polarity, and is at least one of the second regions in the band-like region along the inner side of one edge of the pixel electrode. An electro-optical device comprising a protrusion formed on the substrate. The electro-optical device according to claim 1, wherein the protrusion is formed in a non-opening region between the plurality of pixel electrodes. The electro-optical device according to claim 1, wherein the protrusion is formed over at least the entire width of the belt-shaped region. The electro-optical device according to claim 1, wherein the protrusion is formed in a pole shape. 3. The projection according to claim 1, wherein the protrusion is a non-opening region between the plurality of pixel electrodes and is formed in a stripe shape in a direction perpendicular to a longitudinal direction of the belt-like region. The electro-optical device according to 1. 3. The electro-optical device according to claim 1, wherein an upper end of the protrusion is in contact with the second substrate. 3. The electricity according to claim 1, wherein the protrusion is formed below an alignment film formed on the first and second substrates in contact with the electro-optic material. Optical device. 3. The electricity according to claim 1, wherein the protrusion is formed above an alignment film formed on the first and second substrates in contact with the electro-optical material. Optical device. The electro-optical device according to claim 8, wherein the insulating layer below the alignment film is a planarized insulating film. An electronic apparatus comprising the electro-optical device according to claim 1.

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