JP2005012937A - Phase synchronization detection circuit in generator - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a phase synchronization detection circuit in the synchronous closing unit of a generator strong against zero-cross noise by employing a hybrid circuit of analog circuit and digital circuit. <P>SOLUTION: The phase synchronization detection circuit comprises a phase shift means for delaying the phase of the output from a voltage input circuit in a generator by a quarter of wavelength, a means for multiplying the output from the phase shift means and the output from the voltage input circuit of a bus, a comparison means outputting the signal at a position where the plus and minus are equalized in the envelope of the output waveform from the multiplying means, and a means for removing the signal at a position of 180 ° phase shift between the bus and generator voltages from the output of the comparison means. Since a larger difference can be taken by multiplying the voltages of the bus and the generator as compared with simple addition or subtraction, a synchronization point can be detected with high precision. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a phase-synchronization detection circuit for use in a synchronous input device for supplying a generator such as a diesel generator or a micro gas turbine generator in synchronization with a commercial power source or a generator that is already operating, The present invention relates to a phase synchronization detection circuit that detects phase synchronization by hybridizing an analog circuit and a digital circuit.
[0002]
[Prior art]
When adding generator power to a bus that is supplied with power from a commercial power source or another generator, the voltage difference and frequency difference between the bus and the newly added generator are within the allowable values, and the phase Must match within a predetermined range. For this reason, various phase synchronization detection circuits have been proposed for detecting a point in which the phase of the generator and the newly introduced generator are synchronized. For example, since the beat waveform is output when the bus voltage and generator voltage are subtracted with an analog subtractor, and the voltage, frequency, and phase of both approaches, the timing at which the envelope of this beat waveform is minimized Is used as a synchronous timing, and a generator is turned on. However, this method has a problem that the calculation for synchronization estimation is complicated and difficult because the beat waveform includes an AC voltage on the bus or a ripple having the same frequency as the output voltage of the generator. Therefore, a method of removing ripples using a filter with a large time constant is conceivable, but there is a problem that the synchronization timing is delayed because the beat waveform is delayed.
[0003]
Therefore, in Patent Document 1, a rectangular wave synchronized with each phase of the three-phase AC generator and a rectangular wave V synchronized with a specific phase of the three-phase AC voltage of the bus are generated. The method of determining the level of other rectangular waves and estimating the synchronization timing when the combination of the levels of the rectangular waves changes in a predetermined manner is shown. Patent Document 2 discloses that the voltage of the bus and the generator voltage is converted from analog to digital for the unmanned and improved reliability of the power plant, and the beat voltage is calculated by adding them together, and the synchronization is digital. The detection method is shown in FIG.
[0004]
[Patent Document 1]
JP 2000-139029 A [Patent Document 2]
Japanese Patent Application Laid-Open No. 6-311656
[Problems to be solved by the invention]
However, although the device described in Patent Document 1 is simple, it can only be used in the case of three-phase alternating current, and the device described in Patent Document 2 simply adds the bus voltage and the generator voltage and adds them together. Because there is a beat calculation, if there is a normal 0V during digital sampling and 0V due to pulse noise that causes zero crossing, it is not possible to simply determine which is the normal synchronization point, so there is a possibility of malfunction. is there.
[0006]
Therefore, an object of the present invention is to provide a phase synchronization detection circuit that is hybrid with an analog and digital circuit and that is resistant to zero-cross noise and the like in the generator synchronization input device.
[0007]
[Means for Solving the Problems]
In order to solve the above problems, in the present invention,
A phase synchronization detection circuit in a generator that detects a phase synchronization point for synchronizing the voltage of the generator and the bus to which power from a commercial power source or another generator is supplied,
Phase shift means for delaying the phase of the voltage input signal of the generator by ¼ wavelength, multiplication means for multiplying the output of the phase shift means and the voltage input signal of the bus, and a plus in the envelope of the output waveform of the multiplication means , And a means for outputting a signal at a position where minus is equal, and a means for excluding a signal at a position where the phase of the bus and the generator voltage is shifted by a half wavelength from the output of the comparing means.
[0008]
In this way, by delaying the phase of the voltage input signal of the generator by a quarter wavelength and multiplying it by the voltage input signal of the bus, a difference can be taken larger than when simply adding or subtracting. Can be detected with high accuracy and the phase of the generator output is not delayed by a quarter wavelength, the phase synchronization point appears at the peak position at the output of the multiplication means, so that the phase synchronization point cannot be detected with high accuracy. On the other hand, in the present invention, since the phase of the generator output is multiplied with a delay of ¼ wavelength, the phase synchronization point is at the position where the plus and minus of the envelope in the multiplication means output are equal (zero cross point). Therefore, highly accurate synchronization point detection can be performed without being affected by zero cross noise.
[0009]
The comparison means for outputting a signal at a position where the plus and minus in the envelope of the multiplication means output waveform are equal is given in advance a signal at a position where the plus and minus in the envelope of the multiplication means output waveform are equal. By configuring so that the phase difference between the bus and the generator becomes a predetermined value or less, it is possible to output an optimum synchronization point for applying the generator voltage to the bus.
[0010]
The means for excluding the signal at the position where the phase of the bus and the generator voltage is shifted by a half wavelength from the output of the comparison means includes a phase shift means for delaying the phase of the voltage input signal of the generator by ¼ wavelength, and the phase shift means. By comparing the phase of the phase means output and the phase of the voltage input signal of the bus, and detecting a phase shift of approximately 90 degrees to 270 degrees, both phases are approximately 90 degrees to 270. Since the phase of the generator voltage is originally shifted by a half wavelength and compared, this phase discriminator can be detected as a deviation of about 180 to 360 degrees and can be easily detected. And thereby easily removing a signal that is generated when the phase of the generator voltage and the bus appearing at the position where the plus and minus in the envelope of the multiplication means output waveform are equal to each other is shifted by a half wavelength. It can be.
[0011]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention will be exemplarily described in detail with reference to the drawings. However, the dimensions, materials, shapes, relative arrangements, and the like of the components described in this embodiment are not intended to limit the scope of the present invention only to those unless otherwise specified. This is just an example.
[0012]
FIG. 1 is a schematic block diagram showing an embodiment of a phase synchronization detection circuit in a generator of the present invention, FIG. 2 is an input waveform and an output waveform of a multiplier in the phase synchronization detection circuit in the generator of the present invention, and FIG. FIG. 4 is an output waveform when the phase of the generator voltage input to the multiplier is not shifted, and FIG. 5 is a specific circuit example of the comparator 17. FIG. 6 is an operation time chart thereof.
[0013]
In the figure, 1 is a phase synchronization detection circuit of the present invention, 2 is a bus voltage to which power from a commercial power source or another generator is supplied, 3 is a voltage of a generator (this machine) that detects phase synchronization, 4 and 5 are transformers (PT), and 6 and 7 have a voltage within a certain range by a gain switching signal 9 from the CPU arithmetic circuit 8 and have an analog / digital conversion function for analog / digital conversion of this voltage. The input amplifier circuits 10 and 11 are signal lines for sending the bus voltage and frequency and the generator voltage and frequency to the CPU arithmetic circuit 8, and 12 is a phase shift of the generator voltage by 90 degrees by -90 degrees (1/4 wavelength) shift. The phase shifter 13 includes a bus voltage 2 that is set to a certain range by the input amplifier 6 and a voltage that is also set to a certain range by the input amplifier 7 and has a phase delayed by 90 degrees by the -90 degree phase shifter 12. Multiply A multiplier, 14 is an automatic gain adjustment circuit (AGC) for setting the output of the multiplier 13 within a certain range, 15 is a filter circuit for removing noise, 16 is an amplifier (AMP), 17 is an amplifier (AMP) 16 A comparator (comparator) that outputs a phase difference output 19 when the signal from the CPU arithmetic circuit 8 falls within the range of the phase difference setting signal 18 from the CPU arithmetic circuit 8, and 18 shows the phase difference output 19 as the bus voltage 2 and the generator voltage 3. The phase difference setting signal sent from the CPU arithmetic circuit 8 is output when the phase becomes less than the predetermined range, and 20 is the phase for the synchronous tester on the liquid crystal panel 26 amplified by the amplifier (AMP) 16. Signal. 21 is a phase discriminator for discriminating that the phase difference between the bus voltage 2 and the generator voltage 3 is changed from 90 degrees to 270 degrees. When the phase difference is 90 degrees to 270 degrees, the H signal is output and the phase difference is 270 degrees. When the angle is 90 degrees, the L signal is output. 22 is a synchronization input discriminator, 23 is a phase polarity signal output from the 90 to 270 degree phase discriminator 21 of the bus voltage 2 and the generator voltage 4, and 24 is when the frequency difference and the voltage difference are within the set values. , 25 is a signal for enabling synchronization, and 26 is a synchronization tester on the liquid crystal panel.
[0014]
In FIG. 5, 18 is a phase difference setting signal from the CPU arithmetic circuit 8, and when the phase of the bus voltage 2 and the generator voltage 4 are matched within ± 10 degrees, an “H” signal is output. However, when a phase matching signal is output when they match within ± 5 degrees, an “L” signal is sent. 50 and 51 are comparators for detecting that the phases of the bus voltage 2 and the generator voltage 4 are within ± 10 degrees, and 52 and 53 are also the phases of the bus voltage 2 and the generator voltage 4 are within ± 5 degrees. , 54, 55 and 58 are knot circuits, 56 and 57 are NAND circuits, 59 and 60 are NOR circuits, and 61 is an AND circuit.
[0015]
First, the present invention will be briefly described with reference to FIGS. 2 and 3. In the present invention, the phase of the input voltage 2 from the bus and the input voltage 3 from the generator is set to 90 degrees by the −90 degree phase shifter 12. The delayed voltage is multiplied by the multiplier 13 (1/4 wavelength), and the phase synchronization point between the bus and the generator voltage is detected from the result. That is, now the bus voltage 2 is in the state of FIG. 2A, and the generator voltage 3 is assumed to be synchronized in phase with the voltage difference and frequency difference between the bus and the generator within an allowable range. If the state of B) is assumed, the result of multiplying the voltage of FIG. 2C obtained by delaying the phase of the generator voltage 3 by 90 degrees by the -90 degree phase shifter 12 and the voltage of FIG. 15 exit) is as shown in FIG. In FIG. 2, the horizontal axis represents the phase angle at the bus voltage 2. For example, when the generator voltage 3 is delayed in phase by 45 degrees from the bus voltage 2 in FIG. 2A, the result of multiplying the bus voltage 2 and the generator voltage 3 is negative as shown in FIG. An output biased to the side is obtained. Further, when the generator voltage 3 is delayed in phase by 90 degrees from the bus voltage 2 in FIG. 2 (A), the result of multiplying the bus voltage 2 and the generator voltage 3 is minus as shown in FIG. 2 (F). Similarly, the results of 135 degree delay, 180 degree delay, 225 degree delay, 270 degree delay, and 315 degree delay are respectively shown in FIGS. 2 (G), (H), (J), (K), ( L).
[0016]
The generator voltage 3 shown in FIG. 2 is assumed to be in a state where the voltage difference and the frequency difference between the bus 2 and the generator 3 are within an allowable range and the phase is synchronized as described above. When there is a deviation, the phase difference changes with time. That is, even if the bus 2 and the generator voltage 3 are initially synchronized as shown in FIG. 2B, that is, the output of the multiplier 13 is the state shown in FIG. 2 is slightly smaller than the frequency of the bus 2, the phase difference between them is (E), (F), (G), (H), (J), (K), (L ), And the state is synchronized every certain time determined by the frequency difference.
[0017]
Therefore, as apparent from FIG. 2, the output of the multiplier 13 is shifted from the synchronized state of FIG. 2D to the minus side as shown in FIG. ), When it is delayed by 180 degrees, it changes to a state where a plus / minus balance is achieved, and after passing through a state biased toward the plus side as shown in FIG. 2 (J), the synchronization is changed as shown in FIG. 2 (D). Return to the state where it was removed. Therefore, when the phase state of the bus voltage 2 and the generator voltage 3 is represented by the beat waveform FIG. 3 (G), the output of the multiplier 13 is as shown in FIG. 3 (A). That is, in FIG. 3 (A), 0 degrees is a synchronized state as shown in FIG. 2 (D), and 180 degrees is the generator voltage 3 is the bus voltage 2 as shown in FIG. 2 (H). It is in a state of being shifted by 180 degrees (half wavelength). In this way, at the position where the bus voltage 2 and the generator voltage 3 are synchronized with the position where the phase is shifted by 180 degrees (half wavelength), the plus and minus of the envelope at the output of the multiplier 13 are equal. Therefore, if the signal at a position shifted by 180 degrees (half wavelength) is discarded and only the synchronized position is taken out, the position where the plus and minus of the envelope are equal intersects the point of voltage 0 with a certain angle. Can be detected.
[0018]
On the other hand, for example, when the phase of the input voltage 3 from the generator is multiplied without delay as shown in FIG. 4, the synchronization point appears at the peak position of the envelope, and the synchronization point cannot be detected with high accuracy. That is, in FIG. 4, the horizontal axis represents the phase angle at the bus voltage 2, the bus voltage 2 is in the state of FIG. 4A, and the generator voltage 3 is the voltage difference and frequency between the bus and the generator as in FIG. If the difference is within the allowable range and the phase is synchronized as shown in FIG. 4B, the generator voltage shown in FIG. 4B is multiplied by the bus voltage shown in FIG. In the state, an output only on the plus side can be obtained as shown in FIG. When the generator voltage 3 is delayed in phase by 45 degrees from the bus voltage 2 in FIG. 4 (A), the result of multiplying the bus voltage 2 and the generator voltage 3 is positive as shown in FIG. 4 (D). The output is biased. Further, when the generator voltage 3 is delayed in phase by 90 degrees from the bus voltage 2 in FIG. 4 (A), the result of multiplying the bus voltage 2 and the generator voltage 3 is positive as shown in FIG. Similarly, minus results are equal, and the results of 135 degree delay, 180 degree delay, 225 degree delay, 270 degree delay, and 315 degree delay are respectively shown in FIGS. 4 (F), (G), (H), (J), It becomes like (K). That is, as shown in FIG. 3, when the horizontal axis is expressed by the phase shift angle between the bus voltage 2 and the generator voltage 3, the synchronized 0 degree and 180 degree positions are the plus side and the minus side of the envelope. It becomes difficult to detect the synchronization point with high accuracy because the position of the peak becomes substantially horizontal.
[0019]
The present invention configures a phase synchronization detection circuit in a generator according to such a concept, and the present invention will be described in detail with reference to FIG. In FIG. 1, the voltage input to the input terminal 2 of the bus that is supplied with power from a commercial power source or another generator, and the input terminal 3 of the power from the generator (this machine) that detects phase synchronization is The voltage is stepped down by the transformers 4 and 5 and is adjusted to an optimum voltage for input to the multiplier 13 by the gain switching signal 9 from the CPU arithmetic circuit 8 sent to the input amplifiers 6 and 7 to be analog / Digitally converted. The converted voltage is sent to the CPU arithmetic circuit 8 as the bus voltage 10 and the generator voltage 11 to be the gain switching signal 9, and the voltage 3 from the generator (this machine) is further The phase is delayed by 90 degrees (1/4 wavelength) by the -90 degree phase shifter 12 and sent to the multiplier 13 and the 90 to 270 degree phase discriminator 21 together with the bus voltage of the input amplifier 6. The 90 to 270 degree phase discriminator 21 is for excluding a signal outputted at 180 degrees (half wavelength) from a phase difference output 19 outputted from a comparator 17 described later. FIG. As shown in FIG. 2, “0” (L) is output when the phase difference between the bus voltage 2 and the generator voltage 3 is 270 to 90 degrees, and “1” (H) is output when the phase difference is 90 to 270 degrees.
[0020]
As described with reference to FIG. 2, the multiplier 13 multiplies the voltage sent from the bus 2 and the voltage obtained by delaying the phase of the generator 3 by 90 degrees to obtain a voltage as shown in FIG. Is output. Then, the automatic gain adjustment circuit (AGC) 14 extracts the envelope of the voltage waveform of FIG. 3A from the voltage, and the noise is removed by the filter 15 and sent to the amplifier 16. The amplifier 16 amplifies the transmitted voltage to a predetermined voltage, and the phase difference between the voltage from the bus 2 and the voltage of the generator 3 is a signal of a specified value on the + side from 0 V as shown in FIG. This is sent to the CPU arithmetic circuit 8 as the phase signal 20. The amplified signal of FIG. 3B is also sent to the comparator 17, and compared with the phase difference setting signal 18 from the CPU arithmetic circuit 8 sent to the comparator 17. When the phase of the voltage and the voltage of the generator 3 coincide with each other within a certain range (when synchronized), a phase difference output signal 19 as shown in FIG.
[0021]
The operation of the comparator 17 will be described in detail with reference to FIGS. 5 and 6. The + side of the comparators 50, 51, 52, and 53 shown in FIG. 5 is a position where the phase of the voltage waveform in FIG. Before and after (0 degree), voltages corresponding to positions of −10 degrees (comparator 50), −5 degrees (comparator 52), +5 degrees (comparator 53), and +10 degrees (comparator 51) are applied. 53 outputs “L” before the phase difference between the bus voltage 2 and the generator voltage 4 becomes +10 degrees and +5 degrees. Therefore, the signal is inverted by the knot circuits 54 and 55, and the "H" signal is sent to the NAND circuits 56 and 57 as shown in FIG. However, the comparators 50 and 52 output “L” as shown in FIG. 6 when the phase difference between the bus voltage 2 and the generator voltage 4 does not reach −10 degrees and −5 degrees. The NAND circuits 56 and 57 are closed, and the “H” output is sent to the NOR circuits 59 and 60.
[0022]
On the other hand, when the CPU arithmetic circuit 8 detects that the phase of the bus voltage 2 and the generator voltage 4 coincide with each other within ± 10 degrees as the phase difference setting signal 18, the signal of “H” is within ± 5 degrees. When detecting the coincidence at, the signal of “L” is sent. Therefore, when detecting that the phase of the bus voltage 2 and the generator voltage 4 coincide within ± 10 degrees, set the phase difference. The “H” signal of the signal 18 is sent to the NOR circuit 60, the “L” signal inverted by the NOT circuit 58 is sent to the NOR circuit 59, and the “L” signal is sent from the NOR circuits 59, 60 to the OR circuit 61. Since it is sent, the phase difference output 19 is “L”.
[0023]
When the phase difference between the bus voltage 2 and the generator voltage 4 becomes -10 degrees as shown in FIG. 6, the comparator 50 detects this and outputs an “H” signal, so that the NAND circuit 56 opens and outputs. Becomes “L”, both inputs of the NOR circuit 59 become “L”, an “H” signal is sent to the OR circuit 61, and the phase difference output 19 becomes “H”. Then, when the phase difference between the bus voltage 2 and the generator voltage 4 becomes -5 degrees as shown in FIG. 6, the comparator 52 detects this and outputs an “H” signal, so that the NAND circuit 57 is opened. The output becomes “L” and comes to the NOR circuit 60. Since the “H” signal of the phase difference setting signal 18 is sent from the CPU to the NOR circuit 60, the output remains “L” and does not change. .
[0024]
Then, when the phase difference between the bus voltage 2 and the generator voltage 4 becomes +5 degrees as shown in FIG. 6, the comparator 53 detects this and outputs an “H” signal so that it is inverted by the knot circuit 55. The “L” signal is sent to the NAND circuit 57, which is closed and the output becomes “H”. However, the output of the NOR circuit 60 is “L”, and there is no change. Further, when the phase difference between the bus voltage 2 and the generator voltage 4 becomes +10 degrees as shown in FIG. 6, the comparator 51 detects this and the output becomes “H”. Inverted, the "L" signal is sent to the NAND circuit 56, and the "H" signal is sent to the NOR circuit 59. Therefore, the output of the NOR circuit 59 becomes "L", and the phase difference output 19 of the OR circuit 61 is shown in FIG. As shown in “19. Phase difference output (± 10 °)”, “L”.
[0025]
When a signal “L” is output from the CPU arithmetic circuit 8 as a phase difference setting signal 18 that outputs a phase coincidence signal when they coincide within ± 5 degrees, the NOR circuit 59 is passed through the knot circuit 58. Since the “H” signal is applied, the NOR circuit 59 always outputs the “L” signal, and the NOR circuit 60 outputs the voltage of −5 degrees and +5 degrees detected by the comparators 52 and 53 in FIG. A signal as shown in “19. Phase difference output (± 5 °)” is output.
[0026]
Thus, when the phase difference becomes ± 10 ° or ± 5 ° by the ± 10 ° or ± 5 ° signal of the phase difference setting signal 18 sent from the CPU arithmetic circuit 8 from the comparator 17. A signal indicating that the phase is synchronized is output to the synchronization input discriminating circuit 22, but this phase difference output 19 is output around the point where the center voltage of the output of the multiplier 13 intersects the position of the voltage 0. As can be seen from the filter output (15) in FIG. 3B, the phase difference between the voltage from the bus 2 and the voltage of the generator 3 is 0 degree (synchronization point) and 180 degrees (synchronization is shifted). Are output in both).
[0027]
For this reason, the synchronization input discriminating circuit 22 receives the phase difference between the bus voltage 2 and the generator voltage 3 from the 90 ° to 270 ° phase discriminator 21 from 90 ° to 270 ° as shown in FIG. ) And the signal 24 of FIG. 3E when the voltage difference and frequency difference between the bus voltage 2 and the generator voltage 3 are within the set range are sent from the CPU arithmetic circuit 8. The AND of these signals and the phase difference output signal 19 of FIG. 3C from the comparator 17 is taken so that the phase difference in the phase difference output signal 19 is 180 degrees (out of synchronization). The output is removed and the synchronous input signal 25 shown in FIG. 3 (F) is sent to the CPU arithmetic circuit 8. For this reason, the CPU arithmetic circuit 8 displays on the synchronous tester 26 that the angle at which synchronization can be made is reached, turns on a circuit breaker (CB) of a generator (not shown), and puts the generator into the bus.
[0028]
The above is the operation of the phase synchronization detection circuit in the generator according to the present invention. By configuring the synchronization detection circuit in the generator in this way, the phase synchronization detection circuit is hybridized by analog and digital circuits, and as a result, zero cross It is possible to provide a phase synchronization point detection circuit that is strong against noise and capable of detecting a phase synchronization point with high accuracy.
[0029]
【The invention's effect】
As described above, according to the present invention, the synchronization detection circuit is configured by using the phase shift means for delaying the phase of the generator output by ¼ wavelength and the multiplying means for multiplying the phase shift means output by the bus output. As a result, the difference can be made larger than the case of simply adding or subtracting by multiplying the voltage of the bus and the generator, and the synchronization point can be detected with high accuracy. In addition, when the phase of the generator output is not delayed by ¼ wavelength, the phase synchronization point appears at the peak position in the multiplier output, so that the phase synchronization point cannot be detected with high precision. Since the phase is multiplied with a delay of ¼ wavelength, the phase synchronization point is a position where the plus and minus of the envelope in the multiplier output are equal (zero cross point). Therefore, when the synchronous inspection detection is performed in the filter and comparator circuit by receiving the output, the zero cross noise generated in the bus and the generator voltage input due to noise is normally removed by the configuration of this circuit, so that it is not affected by the zero cross noise. High-precision synchronization point detection can be performed.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram showing an embodiment of a phase synchronization detection circuit in a generator of the present invention.
FIG. 2 is an input waveform of a phase synchronization detection circuit and an output waveform of a multiplier in the generator of the present invention.
FIG. 3 is an output waveform of each block of the phase synchronization detection circuit in the generator of the present invention.
FIG. 4 is an output waveform when the phase of the generator voltage input to the multiplier is not shifted.
FIG. 5 is a specific circuit example of a comparator 17 constituting a phase synchronization detection circuit in the generator of the present invention.
FIG. 6 is an operation time chart of a comparator 17 constituting a phase synchronization detection circuit in the generator of the present invention.
[Explanation of symbols]
1 Phase synchronization detection circuit 2 Input terminal from bus 3 Input terminal 4 from generator (this machine) 5 Transformer (PT)
6, 7 Input amplifier 8 CPU arithmetic circuit 9 Switching signal 10, 11 Signal line for sending bus voltage and generator voltage 12-90 degree phase shifter 13 Multiplier 14 Automatic gain adjustment circuit (AGC)
15 Filter circuit 16 Amplifier (AMP)
17 Comparator 18 Phase difference setting signal 19 Phase difference output 20 Phase signal 21 90 to 270 degree phase discriminator 22 Synchronizing on discriminator 23 Phase polarity signal 24 of bus voltage and generator voltage Frequency difference and voltage difference are within set values When the signal becomes 25, the synchronization input possible signal 26 is synchronized

Claims (3)

A phase synchronization detection circuit in a generator that detects a phase synchronization point for synchronizing the voltage of the generator and the bus to which power from a commercial power source or another generator is supplied,
Phase shift means for delaying the phase of the voltage input signal of the generator by ¼ wavelength, multiplication means for multiplying the output of the phase shift means and the voltage input signal of the bus, and a plus in the envelope of the output waveform of the multiplication means And a means for outputting a signal at a position where minus is equal, and a means for excluding a signal at a position where the phase of the bus voltage and the generator voltage is shifted by a half wavelength from the output of the comparing means. Phase synchronization detection circuit in the machine. The comparison means outputs a signal at a position where the plus and minus in the envelope of the multiplication means output waveform are equal when the phase difference between the predetermined bus and the generator is equal to or less than a predetermined value. The phase synchronization detection circuit in the generator according to claim 1, wherein the phase synchronization detection circuit is a generator. The means for excluding the signal at the position where the phase of the bus bar and the generator voltage is shifted by a half wavelength from the output of the comparison means comprises: phase shifting means for delaying the phase of the voltage input signal of the generator by 1/4 wavelength; and the phase shifting means 2. The generator according to claim 1, wherein the generator is a phase discriminator that compares the phases of the output and the voltage input signal of the bus and detects that the phases of the two are shifted by approximately 90 to 270 degrees. Phase synchronization detection circuit.

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