JP2005012363A - Clock phase adjusting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a clock phase adjusting circuit using a PLL without phase compensation so as to compensate a phase of an output clock with respect to an input clock within a permissible error. <P>SOLUTION: An input clock iCLK to an LSI chip 20 acts like an operation reference on a board. A PLL circuit 21 generates an internal operating clock opCLK whose frequency is a multiple of 1 to 16 of the frequency of the input clock iCLK depending on setting. The opCLK is used for an operating clock for an edge detection section 23, an initial value setting section 24, and a frequency divider 25. The edge detection section 23 detects the leading edge, the trailing edge or both the edges of the iCLK to provide an output of one pulse. The frequency divider 25 comprises a 16-bit shift register and loads an initial value of the initial value setting section 24 by an output of the edge detection section 23 to carry out 16-bit shift operations. A synchronizing circuit 26 is operated by a clock generated by the frequency divider 25 and its output signal becomes an output clock CLK of the LSI 20. Since the CLK is an output of the synchronizing circuit 26, a phase error between the CLK and the iCLK can be kept within the permissible error. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

の場合である。
【００１９】
同期回路２６は分周器２５で生成されたクロックで動作し、その出力信号がＬＳＩチップ２０の出力クロックＣＬＫとなる。
【００２０】
出力クロックＣＬＫは同期回路２６の出力信号なので、入力クロックｉＣＬＫとの位相誤差をａ以内とすることができる。このため、ＰＬＬ回路２１の逓倍率と分周器２５の分周率を変えることで基板上の入力クロックｉＣＬＫとＬＳＩチップ２０の出力クロックＣＬＫの位相誤差を調節することが可能となる。そのため、システムの必要とする位相誤差に合わせて適度にＰＬＬ回路２１の逓倍率を設定することが可能となる。
【００２１】
本実施形態によれば、位相補償の無いＰＬＬ回路を使用した場合であっても、スキャナが備える基板上のクロックとＬＳＩチップが出力する多相クロックとの位相誤差を必要最小限の範囲で調節することができるため、クロックによる放射ノイズの影響がなく、ＣＣＤからＡ／Ｄ変換部へ供給されるアナログ画像信号が不安定となったり、出力画像データのＳ／Ｎが低下したりするといった弊害がない。
【００２２】
なお、分周器２５の分周数ｎをより大きなビット数とすれば、より高精度の位相調節を行なうことができ、ｎビットカウンタを用いて分周することも好ましい。
【００２３】
（実施形態２）
図４は本発明に係るクロック位相調節回路の実施形態２を実施したＬＳＩチップ内部の要部構成を示すブロック図であり、分周器の構成を詳細に示している。本実施形態は位相調節を任意のタイミングで行うものである。このＬＳＩチップを使用したスキャナ全体の基本構成は実施形態１と同じであるが、ＬＳＩチップ内部の分周器の構成が異なる。
【００２４】
図４において、シフトレジスタ４８はリング構造の１６ビットシフトレジスタで、分周クロックの波形パターンが初期値により設定される。初期値の設定は調節フラグ４６により制御される。アンドゲート４７には、エッジ検出部２３からの検出出力と調節フラグ４６が入力され、調節フラグ４６が１の場合はシフトレジスタ４８がエッジ検出毎に初期化される。この場合はシステムの電源ＯＮ時に調節フラグ４６を１にして位相調節を実行し、その後、調節フラグ４６は０の状態で、次に指定されるまで位相調節は行わない。
【００２５】
シフトレジスタ４９は８ビットのシフトレジスタで、シフトレジスタ４８の出力ビットを受けて８ビット分シフト動作した後出力する。ただし、シフトレジスタ４８がリセットされると同時に、シフトレジスタ４９の最終ビットの値でシフトレジスタ４９の全ビットがリセットされる。
【００２６】
シフトレジスタ４９の役割は、分周器４５がリセットされた時に、ＰＬＬ回路２１の逓倍されたクロック幅のパルス（ハザード）を出力しないことであり、シフトレジスタ４９のビット長を調節することで位相調節時に発生するハザードの最少パルス幅を補償することが可能となる。本実施形態ではシフトレジスタ４９を８ビットとしたため、最少パルス幅は、ＰＬＬ回路２１により逓倍されたクロック周期の８倍となる。
【００２７】
本実施形態によれば、例えばシステムの電源ＯＮ時等の任意のタイミングで調節フラグ４６を１にして位相調節を実行することで、実施形態１と同様の位相補償効果を得ることができる。
【００２８】
本発明の実施態様の例を以下に列挙する。
〔実施態様１〕 入力クロックを逓倍するＰＬＬ手段からの逓倍されたクロックを基に動作して、集積回路外部への出力クロックと前記入力クロックとの位相関係を調節するクロック位相調節回路であって、
前記逓倍されたクロックの周期に応じた分解能で前記入力クロックのエッジを検出する検出手段と、
該エッジ検出のタイミングで任意の位相と分周比の設定を行なって分周クロックを生成する分周クロック生成手段とを備え、
前記逓倍されたクロックが前記分周クロック生成手段による前記分周クロックに同期することで、前記入力クロックとの位相関係を調節することを特徴とするクロック位相調節回路。
【００２９】
〔実施態様２〕 実施態様１に記載のクロック位相調節回路において、
前記エッジ検出手段は、前記入力クロックの立ち上がりエッジまたは立下りエッジの一方を検出することを特徴とするクロック位相調節回路。
【００３０】
〔実施態様３〕 実施態様１に記載のクロック位相調節回路において、
前記分周クロック生成手段はｎビットカウンタにより構成されることを特徴とするクロック位相調節回路。
【００３１】
〔実施態様４〕 実施態様１に記載のクロック位相調節回路において、
前記分周クロック生成手段はｎビットのシフトレジスタにより構成され、ｎビット分のシフト動作により前記分周クロックが出力される周期でリセットされることを特徴とするクロック位相調節回路。
【００３２】
〔実施態様５〕 実施態様４に記載のクロック位相調節回路において、
前記分周クロック生成手段はｎビットのリング状シフトレジスタを含んで構成され、さらに、
前記リング状シフトレジスタを任意のタイミングでリセットする手段を備えることを特徴とするクロック位相調節回路。
【００３３】
〔実施態様６〕 実施態様５に記載のクロック位相調節回路において、
前期分周クロック生成手段からの前記分周クロックがｍビットのシフトレジスタを通して出力され、さらに、
前記ｍビットのシフトレジスタはリセット時に、最終段ビットのリセット直前の値がセットされることを特徴とするクロック位相調節回路。
【００３４】
〔実施態様７〕 実施態様１乃至６のいずれかに記載のクロック位相調節回路と、
前記クロック位相調節回路により位相調節された前記出力クロックを基に動作する画像読取り手段と、
前記クロック位相調節回路により位相調節された前記出力クロックを基に動作し、前記画像読取り手段からの画像信号に所定の画像処理を施す画像処理手段とを備えたことを特徴とするスキャナ装置。
【００３５】
【発明の効果】
本発明に係るクロック位相調節回路によれば、基板上の入力クロックと、ＬＳＩチップ出力信号、例えばＣＣＤ等の基板上のデバイスを制御するための多相クロック等の出力クロックの位相関係を必要最小限で許容範囲内に調節できるため、アナログデバイスの安定動作、放射ノイズの抑制を実現することができる。
【図面の簡単な説明】
【図１】本発明に係るクロック位相調節回路の実施形態１を使用したスキャナを示す概略的なブロック図である。
【図２】実施形態１に係るクロック位相調節回路を含んだＬＳＩチップの内部構成を示すブロック図である。
【図３】実施形態１における動作を示すタイミングチャートである。
【図４】本発明に係るクロック位相調節回路の実施形態２を実施したＬＳＩチップ内部の要部構成を示すブロック図である。
【符号の説明】
１０ クロックジェネレータ
２０ ＬＳＩチップ
２１ ＰＬＬ回路
２２ クロック位相調節部
２３ エッジ検出部
２４ 初期値設定部
２５，４５ 分周器
２６ 同期回路
３０ ＣＣＤ
４０ Ａ／Ｄ変換部
４６ 調節フラグ
４７ アンドゲート
４８，４９ シフトレジスタ
５０ 画像処理部
１００ スキャナ[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a clock phase adjustment circuit, and more particularly to a clock phase adjustment circuit that performs phase control between a clock on an electric circuit board and an operation clock inside an LSI chip on the electric circuit board.
[0002]
[Prior art]
Conventionally, an internal clock of an LSI chip used in a scanner or the like is often operated at a relatively high speed (high frequency) with respect to a clock on a substrate on which the LSI chip is mounted in order to improve performance. Therefore, the clock multiplied by mounting the PLL inside the LSI chip is used as the operation clock (internal clock). At this time, in the normal PLL, the phase of the output clock multiplied by the phase of the input clock is not compensated. If phase compensation is required, a clock with substantially the same phase can be obtained by using a PLL with a phase compensation function.
[0003]
[Problems to be solved by the invention]
However, when a PLL without phase compensation is used inside the LSI, the phase relationship between the clock on the board and the clock or data signal output from the LSI changes every time the board is powered on. For this reason, radiation noise from the substrate, crosstalk noise, and the like are not uniform, and a countermeasure over a wide band is required. Furthermore, it adversely affects the operation of other devices on the substrate, particularly analog devices (A / D, D / A, CCD, etc.). Such an adverse effect can be eliminated by using a PLL with a phase compensation function, but this leads to an increase in LSI cost.
[0004]
In the scanner, the phase relationship of the clocks to the CCD, A / D converter, and image processor is not constant, and therefore, from the CCD to the A due to the influence of radiation noise from the external clock operating with the input clock. The analog image signal input to the / D conversion unit becomes unstable, and the S / N of the image may be reduced.
[0005]
An object of the present invention is to provide a clock phase adjustment circuit that solves the above problems.
[0006]
[Means for Solving the Problems]
If a PLL with phase compensation is used, phase compensation can be performed with high accuracy. However, in an actual circuit, if the adjustment can be made with a certain degree of error, the above-mentioned problem will be eliminated, so that a PLL without phase compensation is allowed. Phase compensation within the error.
[0007]
That is, the clock multiplied by the PLL inside the LSI chip is further divided, and the generated clock is used as the operation clock. Using the clock multiplied by the PLL as an operation clock inside the LSI, the frequency dividing means (shift register or counter for generating the divided clock) is operated, the rising edge of the input clock is detected, and the divided clock is generated. The counter of the output is reset to adjust the phase of the output clock.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
(Embodiment 1)
FIG. 1 is a schematic block diagram showing a scanner using the clock phase adjusting circuit according to the first embodiment of the present invention, and FIG. 2 is a block diagram showing an internal configuration of the LSI chip in FIG.
[0009]
The scanner 100 shown in FIG. 1 includes a clock generator 10, an LSI chip 20, a CCD 30, an A / D conversion unit 40, and an image processing unit 50. The clock generator 10 generates the clock CLK1 and inputs it to the PLL circuit 21 without phase compensation and the clock phase adjustment unit 22 inside the LSI chip 20 mounted on an electric circuit board (not shown).
[0010]
The PLL circuit 21 multiplies the clock CLK1 by 8 to generate the clock CLK2. The phases (change points) of the clocks CLK1 and CLK2 are different each time the substrate is turned on. The clock phase adjustment unit 22 operates using the clock CLK2 as an operation clock, and generates clocks CLK3, CLK4, and CLK5 whose phases are adjusted as described later from the clocks CLK1 and CLK2. The clocks CLK3, CLK4, and CLK5 are adjusted to maintain an allowable phase error within a certain range with respect to the phase of the clock CLK1.
[0011]
The CCD 30 is for image reading, and may be either a format in which the CCD 30 moves and scans a fixed document, or a format in which the CCD 30 is fixed and feeds and scans. The CCD 30 may be a color filter or a monochrome type. The CCD 30 forms an image of an original on an imaging surface using an optical lens, and takes in charges corresponding to the original image. Then, in synchronization with a drive signal from a driver (not shown) and the clock CLK3, these charges are sequentially supplied to the A / D converter 40 as an analog image signal through a CDS circuit (not shown).
[0012]
The A / D converter 40 converts the analog image signal obtained from the CCD 30 into digital data. This A / D conversion is performed in synchronization with the control signal and CLK4. At this time, the phase of CLK4 is adjusted so that CLK4 rises when the analog image signal obtained from the CCD 30 is at a stable and constant level.
[0013]
The image processing unit 50 performs various image processing such as black offset correction and shading correction on the output digital data from the A / D conversion unit 40 and outputs the processed data to the outside. At this time, the phase of CLK5 is adjusted so that the image processing unit 50 can receive the output digital data from the A / D conversion unit 40.
[0014]
Hereinafter, the configuration and operation of the clock phase adjusting unit 22 which is a main part of the present invention for performing the phase adjustment will be described in detail.
In FIG. 2, the LSI chip 20 is mounted on an electric circuit board (not shown) of the scanner 100. The clock phase adjustment unit 22 is configured by elements other than the LSI chip 20.
[0015]
The input clock iCLK (= CLK1) is a clock that serves as an operation reference on the substrate, and is supplied from the clock generator 10 to the LSI chip 20. At the same time, the input signal and output signal to the LSI chip 20 are synchronized with the input clock iCLK. A PLL circuit 21 is provided inside the LSI chip 20, and the PLL circuit 21 can generate a clock having a frequency obtained by multiplying the input clock iCLK by 1 to 16 by an arbitrary setting.
[0016]
In the timing chart of FIG. 3, the internal operation clock opCLK (= CLK2) of (b) which is the PLL output generated by the PLL circuit 21 is output at a frequency obtained by multiplying the input clock iCLK of (a) by 8. It is an example. Here, when the internal operation clock opCLK is used as a reference, the input clock iCLK may have a phase error equal to or smaller than the amount indicated by a in FIG. 3 (one cycle of the internal operation clock opCLK).
[0017]
The internal operation clock opCLK is an operation clock for the edge detection unit 23, the initial value setting unit 24, and the frequency divider 25. Since the internal operation clock opCLK is multiplied by 8 by the PLL circuit 21, it is usually several hundred MHz. The edge detection unit 23 detects the rising edge, falling edge, or both edges of the input clock iCLK and outputs one pulse. FIG. 3C shows an example of a rising edge detection waveform. The frequency divider 25 is composed of an n (n = 16) bit shift register, loads the initial value of the initial value setting unit 24 by the output pulse of the edge detection unit 23, and performs a 16-bit shift operation.
[0018]
Each of the divided CLKs in FIGS. 3D to 3K has an initial value of the initial value setting unit 24,

This is the case.
[0019]
The synchronization circuit 26 operates with the clock generated by the frequency divider 25, and its output signal becomes the output clock CLK of the LSI chip 20.
[0020]
Since the output clock CLK is an output signal of the synchronization circuit 26, the phase error from the input clock iCLK can be within a. For this reason, it is possible to adjust the phase error between the input clock iCLK on the substrate and the output clock CLK of the LSI chip 20 by changing the multiplication factor of the PLL circuit 21 and the frequency division ratio of the frequency divider 25. Therefore, the multiplication factor of the PLL circuit 21 can be set appropriately according to the phase error required by the system.
[0021]
According to the present embodiment, even when a PLL circuit without phase compensation is used, the phase error between the clock on the substrate provided in the scanner and the multiphase clock output from the LSI chip is adjusted within a necessary minimum range. Therefore, there is no influence of the radiation noise due to the clock, the analog image signal supplied from the CCD to the A / D converter becomes unstable, or the S / N of the output image data is lowered. There is no.
[0022]
Note that if the frequency division number n of the frequency divider 25 is set to a larger number of bits, more accurate phase adjustment can be performed, and it is also preferable to perform frequency division using an n-bit counter.
[0023]
(Embodiment 2)
FIG. 4 is a block diagram showing the configuration of the main part inside the LSI chip in which the second embodiment of the clock phase adjusting circuit according to the present invention is implemented, and shows the configuration of the frequency divider in detail. In the present embodiment, phase adjustment is performed at an arbitrary timing. The basic configuration of the entire scanner using the LSI chip is the same as that of the first embodiment, but the configuration of the frequency divider in the LSI chip is different.
[0024]
In FIG. 4, a shift register 48 is a ring structure 16-bit shift register, and a waveform pattern of a divided clock is set by an initial value. Setting of the initial value is controlled by the adjustment flag 46. The detection output from the edge detector 23 and the adjustment flag 46 are input to the AND gate 47. When the adjustment flag 46 is 1, the shift register 48 is initialized every time the edge is detected. In this case, the adjustment flag 46 is set to 1 when the system power is turned on, and the phase adjustment is executed. Thereafter, the adjustment flag 46 is 0 and the phase adjustment is not performed until the next designation.
[0025]
The shift register 49 is an 8-bit shift register, receives the output bit of the shift register 48, shifts the output by 8 bits, and outputs it. However, at the same time as the shift register 48 is reset, all bits of the shift register 49 are reset with the value of the last bit of the shift register 49.
[0026]
The role of the shift register 49 is not to output a pulse (hazard) having a multiplied clock width of the PLL circuit 21 when the frequency divider 45 is reset, and the phase by adjusting the bit length of the shift register 49. It is possible to compensate for the minimum pulse width of the hazard that occurs during adjustment. In this embodiment, since the shift register 49 is 8 bits, the minimum pulse width is 8 times the clock cycle multiplied by the PLL circuit 21.
[0027]
According to the present embodiment, the phase compensation effect similar to that of the first embodiment can be obtained by executing the phase adjustment by setting the adjustment flag 46 to 1 at an arbitrary timing such as when the system is turned on.
[0028]
Examples of embodiments of the present invention are listed below.
[Embodiment 1] A clock phase adjustment circuit that operates based on a multiplied clock from a PLL means that multiplies an input clock and adjusts the phase relationship between an output clock to the outside of an integrated circuit and the input clock. ,
Detecting means for detecting an edge of the input clock with a resolution corresponding to a cycle of the multiplied clock;
Frequency division clock generating means for generating a divided clock by setting an arbitrary phase and frequency division ratio at the edge detection timing;
The clock phase adjustment circuit, wherein the multiplied clock is synchronized with the divided clock generated by the divided clock generation means to adjust a phase relationship with the input clock.
[0029]
[Embodiment 2] In the clock phase adjustment circuit according to Embodiment 1,
The clock phase adjustment circuit, wherein the edge detection means detects one of a rising edge and a falling edge of the input clock.
[0030]
[Embodiment 3] In the clock phase adjustment circuit according to Embodiment 1,
The clock phase adjusting circuit, wherein the frequency-divided clock generating means comprises an n-bit counter.
[0031]
[Embodiment 4] In the clock phase adjustment circuit according to Embodiment 1,
2. The clock phase adjusting circuit according to claim 1, wherein the frequency-divided clock generating means is constituted by an n-bit shift register and is reset at a cycle in which the frequency-divided clock is output by an n-bit shift operation.
[0032]
[Embodiment 5] In the clock phase adjustment circuit according to Embodiment 4,
The frequency-divided clock generating means includes an n-bit ring-shaped shift register, and
A clock phase adjustment circuit comprising means for resetting the ring-shaped shift register at an arbitrary timing.
[0033]
[Embodiment 6] In the clock phase adjustment circuit according to Embodiment 5,
The frequency-divided clock from the previous frequency-divided clock generation means is output through an m-bit shift register, and
A clock phase adjustment circuit, wherein the m-bit shift register is set to a value immediately before the last bit is reset at the time of reset.
[0034]
[Embodiment 7] The clock phase adjusting circuit according to any one of Embodiments 1 to 6,
Image reading means operating based on the output clock phase-adjusted by the clock phase adjustment circuit;
A scanner apparatus comprising: an image processing unit that operates based on the output clock phase-adjusted by the clock phase adjustment circuit and performs predetermined image processing on an image signal from the image reading unit.
[0035]
【The invention's effect】
According to the clock phase adjustment circuit of the present invention, the phase relationship between the input clock on the substrate and the output clock of the LSI chip output signal, for example, a multiphase clock for controlling a device on the substrate such as a CCD, is the minimum Therefore, the analog device can be stably operated and radiation noise can be suppressed.
[Brief description of the drawings]
FIG. 1 is a schematic block diagram showing a scanner using a first embodiment of a clock phase adjustment circuit according to the present invention.
FIG. 2 is a block diagram showing an internal configuration of an LSI chip including a clock phase adjustment circuit according to the first embodiment.
FIG. 3 is a timing chart showing an operation in the first embodiment.
FIG. 4 is a block diagram showing a configuration of main parts inside an LSI chip in which a second embodiment of a clock phase adjustment circuit according to the present invention is implemented;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 10 Clock generator 20 LSI chip 21 PLL circuit 22 Clock phase adjustment part 23 Edge detection part 24 Initial value setting part 25, 45 Frequency divider 26 Synchronous circuit 30 CCD
40 A / D converter 46 Adjustment flag 47 AND gate 48, 49 Shift register 50 Image processor 100 Scanner

Claims (1)

A clock phase adjusting circuit which operates based on a multiplied clock from a PLL means for multiplying an input clock and adjusts a phase relationship between an output clock to the outside of the integrated circuit and the input clock;
Detecting means for detecting an edge of the input clock with a resolution corresponding to a cycle of the multiplied clock;
Frequency division clock generating means for generating a divided clock by setting an arbitrary phase and frequency division ratio at the edge detection timing;
The clock phase adjustment circuit, wherein the multiplied clock is synchronized with the divided clock generated by the divided clock generation means to adjust a phase relationship with the input clock.

Images