JP2005012284A - Bit length extending apparatus, data processing apparatus, bit length extending method, control program and readable recording medium - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To supplement data of low order (m-n) bit length with a less conversion error by an easy processing in extending digital data of n-bit length to data of m-bit length (m>n). <P>SOLUTION: In performing bit extension for input data Dn of a bit length n into output data Dm of a bit length larger than n, a bit length extending apparatus 10 assigns high order (m-n) bit of the input data Dn to low order (m-n) bits of the output data requiring supplement, thereby generating the of m-bit output data Dm without performing complicated processing. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a bit length extension device used when digital data is converted to a bit length according to the use environment, a data processing device using the same, a bit length extension method, a control program for causing a computer to execute the method, and The present invention also relates to a computer-readable readable recording medium on which this is recorded.
[0002]
[Prior art]
In recent years, various information and data have been converted into digital signals and processed. However, even for the same type of information / data, the so-called conditions such as the performance and processing capability of the data processing apparatus that processes the data, the required processing accuracy, specifications and provisions related to the operation of the data, etc. It is necessary to perform processing with a digital signal having a bit length suitable for each use environment. For this reason, even if the same information / data is transferred from one usage environment to a different usage environment, data processing can be performed with a bit length suitable for each usage environment. Need to convert the bit length.
[0003]
For example, when the bit length suitable for the usage environment N is n (n is a positive integer) bits and the bit length suitable for the usage environment M is m (m is a positive integer) bits, the same information and data Even so, when moving data from the usage environment N to the usage environment M, it is necessary to convert the bit length from n to m.
[0004]
Here, as shown in FIG. 6A, when n> m, the lower (n−m) bits of the n-bit data are discarded and the upper m bits are used, so that m bits Data can be generated.
[0005]
However, as shown in FIG. 6B, when n <m, it is necessary to compensate for the lower (mn) bits that are insufficient in the m-bit data by some method.
[0006]
As described above, when the n-bit data is expanded to the m-bit data, the easiest method for supplementing the lower order (mn) of the m-bit data is, for example, lack of (mn) bits. There is a method in which all the minutes are filled with “0” or “1”.
[0007]
Also, in the audio-related field and the like, many methods for generating lower bits have been proposed, as in Patent Documents 1 to 3, for example.
[0008]
For example, according to Permissible Document 1, lower M bits and sign bit S are extracted from N-bit audio data to generate (S + M) -bit data, and {N− (S + M)}-bit pseudo data L To generate (S + L + M) -bit data, add reverberation bit X to this to generate (S + L + M + X) -bit data, and replace (S + L + M) -bit data with N-bit data (N + X A bit length extending method is disclosed in which the bit length can be extended without generating a sense of incongruity by generating bit data.
[0009]
Further, Patent Document 2 extracts a difference between sampling data, detects a minute level portion where there is no change over several samples and changes only 1 LSB, and a gradual level change over several samples before and after 1 LSB change. There has been disclosed a bit extension apparatus that can obtain a smooth data change as a whole by generating and adding data below the LSB so as to be output.
[0010]
Further, Patent Document 3 calculates a difference data string between samples of input audio data, calculates a continuous point of no change point where the difference data is 0, and a change point where the difference data is 1 LB or more. Two difference rates are calculated using the difference data of the change points adjacent to the change continuous interval, and the lower bits of the data of the non-change continuous interval and the bit length are extended based on the two change rates. Discloses a digital audio reproduction apparatus capable of reproducing an audio signal close to the amplitude of an input analog audio signal from digital audio data.
[0011]
[Patent Document 1]
Japanese Patent Laid-Open No. 9-46179
[Patent Document 2]
JP-A-4-354208
[Patent Document 3]
Japanese Patent Laid-Open No. 10-242859
[0012]
[Problems to be solved by the invention]
However, when n-bit data is expanded to m-bit (m> n) data, the lower (mn) bits of m-bit data are all compensated by “0” or “1”. In the case of “0”, the error increases as it approaches the maximum value, and in the case of “1”, the error increases as it approaches the minimum value.
[0013]
For example, when data Dn having a bit length n handled in the usage environment N is converted to data Dm having a bit length m for use in the usage environment M, as shown by an arrow A1 in FIG. m−n) When all the shortage of bits is filled with “0”, Dm does not reach the maximum value even if Dn reaches the maximum value. Also, as shown by the arrow A2 in FIG. 7, when all the deficiencies of the lower (mn) bits are compensated with “1”, Dm does not become 0 even if Dn becomes the minimum value (0).
[0014]
In addition, the bit length extension methods disclosed in Patent Documents 1 to 3 require complicated processing, so that it is not easy to apply them to technical fields other than audio related fields.
[0015]
The present invention solves the above-described conventional problems. When the bit length is extended from n-bit digital data to m-bit length (m> n) data, complicated processing is not performed and the lower order (m -N) Bit length extension device that can compensate for bit length data with less error and can be applied in a wide range of technical fields, data processing device using the same, bit length extension method, and cause computer to execute this An object of the present invention is to provide a control program and a computer-readable readable recording medium on which the control program is recorded.
[0016]
[Means for Solving the Problems]
The bit length extension device of the present invention is a bit length extension device that extends digital data of n (n is a positive integer) bit length to digital data of m bits (m is an integer of m> n). Of the m-bit data, all n-bit data of the original data is assigned to the upper n bits, and the upper (mn) bit data of the original data is reassigned to the lower (mn) bits. A first bit length extending means for generating bit output data is provided, whereby the above object is achieved.
[0017]
The bit length extension device of the present invention converts digital data of n (n is a positive integer) bit length including sign information in the most significant bit into digital data of m bits (m is an integer of m> n) length. In the bit length extension device to be extended, among the m-bit data, all n-bit data of the original data is assigned to the upper n bits and the next most significant bit of the original data is assigned to the lower (mn) bits. The second bit length extension means for generating m-bit output data by allocating data from the second most significant bit to the upper (mn) bits, thereby achieving the above object. The
[0018]
Preferably, the first bit length extension means in the bit length extension device of the present invention uses the n-bit input data as the upper input data of bit length (mn) bits and the bit length (n− (m -N)) first data separation means for separating the lower-order input data, and among the m-bit data, the higher-order (mn) bits are assigned the higher-order input data, and the next (n- ( mn)) a first data composition for generating m-bit output data by allocating the lower input data to the bits and reassigning the upper input data to the next lower (mn) bits. Means.
[0019]
Further preferably, the second bit length extending means in the bit length extending apparatus of the present invention is configured to convert the n-bit input data into the most significant input data of the most significant bit, the second most significant bit next to the most significant bit. Second data separating means for separating the upper input data from bit to bit length (mn) bits and the lower input data of bit length (n- (mn) -1), and the m-bit data The most significant bit is assigned the most significant input data, the second most significant bit next to the most significant bit is assigned the upper (mn) bits, and the next ( m-bit output data is generated by allocating the lower input data to n- (mn) -1) bits and reassigning the upper input data to the next lower (mn) bits. Second data composition And a stage.
[0020]
Further preferably, the first bit length extension means or the second bit length extension means in the bit length extension device of the present invention bit-shifts the n-bit input data in one direction (mn) times. First variable generating means for generating a first variable; second variable generating means for generating a second variable obtained by bit-shifting the n-bit input data in the other direction (n- (mn)) times; First logic synthesizing means for generating m-bit output data from the logical sum of the first variable and the second variable;
[0021]
Further preferably, the second bit length extension means in the bit length extension device of the present invention obtains (n−1) -bit data from the second most significant bit next to the most significant bit of the n-bit input data. Third variable generation means for generating a third variable bit-shifted (mn) times in one direction, and the (n-1) -bit data in the other direction (n- (mn) -1) A fourth variable generating means for generating a fourth variable that has been bit-shifted times, and m-1 bit data is generated from the logical sum of the third variable and the fourth variable, And second logic synthesis means for generating m-bit output data by adding the most significant bit input data as the most significant bit data.
[0022]
The data processing apparatus according to the present invention performs data processing on at least one of the input data and the output data of the bit length extension apparatus according to any one of claims 1 to 6, thereby achieving the above object.
[0023]
The bit length extension method of the present invention is a bit length extension method for extending digital data of n (n is a positive integer) bit length to digital data of m bits (m is an integer of m> n). Of the m-bit data, all n-bit data of the original data is assigned to the upper n bits, and the upper (mn) bit data of the original data is reassigned to the lower (mn) bits. There is a first bit length extension step for generating bit data, whereby the above object is achieved.
[0024]
According to the bit length extension method of the present invention, digital data of n (n is a positive integer) bit length in which sign information is included in the most significant bit is converted to digital data of m bits (m is an integer of m> n) length. In the extended bit length method, all n bits of the original data are assigned to the upper n bits of the m bits of data, and the next most significant bit of the original data is assigned to the lower (mn) bits. A second bit length extension step for generating m-bit data by allocating data from the second most significant bit to the upper (mn) bits, thereby achieving the above object. .
[0025]
Preferably, in the bit length extension method of the present invention, in the first bit length extension step or the first bit length extension step, the n-bit input data is bit-shifted in one direction (mn) times. A first variable generating step for generating a first variable; a second variable generating step for generating a second variable obtained by bit-shifting the n-bit input data in the other direction (n- (mn)) times; A first logic synthesis step of generating m-bit data from the logical sum of the first variable and the second variable.
[0026]
Furthermore, it is preferable that the second bit length extension step in the bit length extension method of the present invention includes data from the second most significant bit to the (n−1) bits after the most significant bit of the n-bit input data. A third variable generating step for generating a third variable obtained by bit-shifting (mn) times in one direction, and (n- (mn) -1 in the other direction. ) A fourth variable generating step for generating a fourth variable bit-shifted times, and m-1 bit data is generated from the logical sum of the third variable and the fourth variable, and the most significant of the m-1 bit And a second logic synthesis step for generating m-bit data by adding the input data of the most significant bit as the most significant bit data.
[0027]
The control program of the present invention is for causing a computer to execute the steps of the bit length extension method according to any one of claims 8 to 11, thereby achieving the above object.
[0028]
The readable recording medium of the present invention is readable by a computer in which the control program according to claim 12 is recorded, whereby the above object is achieved.
[0029]
The operation of the present invention will be described below with the above configuration.
[0030]
In the present invention, as shown in FIG. 2, when data Dn having a bit length n is extended to data Dm having a bit length m larger than n, compensation is required (mn). ) By assigning the upper (mn) bits of Dn to the lower bits of the bits, it is possible to generate m-bit data Dm without performing complicated processing as in the prior art. .
[0031]
Further, when Dn is the maximum value, Dm is also the maximum value, and when Dn is the minimum value, Dm is also the minimum value. Therefore, all of the shortage of (mn) bits is compensated with “1” or “0”. The error can be greatly reduced compared to the technology.
[0032]
When sign information is included in the most significant bit of the n-bit data, the lower (mn) bits that need to be compensated are changed from the second most significant bits except the most significant bit of the original data ( mn) bits can be allocated.
[0033]
DETAILED DESCRIPTION OF THE INVENTION
The case where the bit length extension device of the present invention is applied to a data processing device as Embodiments 1 to 3 will be described below with reference to the drawings.
[0034]
(Embodiment 1)
In the first embodiment, an example in which the present invention is realized by hardware (bit length extension circuit) as a bit length extension device will be described.
[0035]
FIG. 1 is a block diagram showing the main configuration of the data processing apparatus according to the first embodiment of the present invention.
[0036]
In FIG. 1, the data processing apparatus 100 has a first bit length that extends digital data of n (n is a positive integer) bit length to digital data of m bits (m is an integer of m> n) length. A bit length extension circuit 10 as extension means, and a data processing unit 5 that performs various data processing on the output data with the bit length extended from the bit length extension circuit 10 are provided. As the data processing apparatus 100 of the present invention, for example, in audio equipment, digital data of 10-bit gradation (in the present invention, n = 10) output from an old-style device is converted to the latest 16-bit gradation (m = And a data converter for inputting to a device corresponding to 16).
[0037]
The bit length extension circuit 10 includes an input circuit 1, a separation circuit 2 as first data separation means, a synthesis circuit 3 as first data synthesis means, and an output circuit 4 that outputs output data with bit length extended. Among the m-bit data, all n-bit data of the original data is assigned to the upper n bits, and the upper (mn) bits of the original data are assigned to the lower (mn) bits. The m-bit output data is generated by reassigning the data.
[0038]
The input circuit 1 receives input data Dn having a bit length n (n is a positive integer) from the outside and outputs it.
[0039]
The separation circuit 2 separates the input data Dn into upper input data Dn1 having a bit length (mn) and lower input data Dn2 having a bit length (n- (mn)). Here, m is a positive number with m> n.
[0040]
In the synthesis circuit 3, the upper input data Dn1 is assigned to the upper (mn) bits, the lower input data Dn2 is assigned to the next (n- (mn)) bits, and further as shown in FIG. The upper input data Dn1 is reassigned to the lower (mn) bits to generate output data Dm having a bit length m.
[0041]
The output unit 4 outputs data Dm extended from the synthesis circuit 3 to the bit length m (m is an integer of m> n).
[0042]
With the above configuration, the operation of the bit length extending apparatus 10 when the bit length of the input data Dn not including the code information is 8 and the bit length Dm of the output data is 15 will be described with reference to FIG. .
[0043]
As shown in FIG. 3A, first, the input data Dn having a bit length n = 8 is (mn) = 15−8 = higher input data having a bit length of 7 and a bit length (n− (mn)). ) = 8−7 = 1 is divided into low-order input data Dn2 of 1 bit length.
[0044]
Next, the upper input data Dn1 is assigned to the upper (mn) = 7 bits, the lower input data Dn2 is assigned to the next (n- (mn)) = 1 bit, and the upper input data Dn1 is reassigned to the lower order (mn) = 7 bits, and output data Dm having a bit length m = 15 is generated.
[0045]
As described above, according to the first embodiment, when the bit length n is extended to the data Dm having a bit length m larger than n, the (m−n) bits that need to be compensated are used. By assigning the upper (mn) bits of the data Dn to the lower bits, respectively, the m-bit data Dm can be easily generated without performing complicated processing as in the prior art. In this case, when the input data Dn is the maximum value, Dm is also the maximum value, and when the input data Dn is the minimum value, the Dm is also the minimum value. Therefore, all of the shortage of (mn) bits is “1” or “ The error can be greatly reduced as compared with the conventional technique which compensates for “0”.
[0046]
Further, when the bit length extension circuit 10 of the first embodiment is mounted on the data processing apparatus 100, if the sign information (information indicating positive or negative) is fixed to any one, the separation circuit 2 and the synthesis circuit It is possible to realize the operation 3 with only simple wiring.
[0047]
(Embodiment 2)
In the first embodiment, the case has been described where the sign information is not included in the most significant bit of the input data. However, in the present embodiment 2, the sign information (information indicating positive or negative) is included in the most significant bit of the input data. The case where is included will be described. 1 will be described in common.
[0048]
In FIG. 1, the data processing apparatus 100A has a second bit length that extends n (n is a positive integer) bit length digital data to m bit (m is an integer of m> n) length. A bit length extension circuit 10A as an extension means and a data processing unit 5 are provided.
[0049]
The bit length extension circuit 10A includes an input circuit 1, a separation circuit 2A as second data separation means, a synthesis circuit 3A as second data synthesis means, and an output circuit 4 that outputs output data with the bit length extended. Of the m-bit data, all n-bit data of the original data is assigned to the upper n bits, and the next (mn) bits are the next bits after the most significant bit of the original data. By assigning data from the 2nd bit to the upper (mn) bits, m-bit output data is generated.
[0050]
In the separation circuit 2A, the input data Dn having the bit length n is the most significant input data Dn0 composed of the most significant bits indicating the code information, and the bit length (mn) bits from the second most significant bits excluding the most significant bits. Are separated into the higher-order input data Dn1 and the lower-order input data Dn2 having a bit length (n− (mn) −1).
[0051]
In the combining circuit 3A, the most significant input data (code information) is assigned to the most significant bit, and the upper input data Dn1 is assigned from the second most significant bit to the most significant (mn) bits. The input data Dn2 is assigned to the next (n- (mn) -1) bits, and the upper input data Dn1 is reassigned to the lower (mn) bits, and the sign information is assigned to the most significant bits. Output data having a bit length m is generated.
[0052]
With reference to FIG. 3B, an example of the operation of the bit length extension circuit when the bit length of input data including code information is 8 and the bit length of output data is 15 will be described with reference to FIG.
[0053]
As shown in FIG. 3B, the input data Dn having the bit length n = 8 in which the sign information is included in the most significant bit is the most significant input data Dn0 composed of the most significant bit indicating the sign information s, the most significant bit. From the second bit excluding the bits, the bit length (mn) = 15-8 = 7 bits of high-order input data Dn1, and the bit length (n- (mn) -1) = 8-8 = 0 Separated into lower input data Dn2. In this example, the lower-order input data Dn2 is 0 bit and is not shown in FIG.
[0054]
The most significant input data (code information) is assigned to the most significant bit, the upper input data Dn1 is assigned from the second most significant bit excluding the most significant bit to the upper (mn) = 7 bits, and the lower input data Dn2 is The next (n− (mn) −1) = 0 bit is assigned, and the higher order input data Dn1 is further assigned to the next lower order (mn) = 7 bits. Output data Dm having a bit length m including code information s.
[0055]
As described above, according to the bit length extension device 10A of the second embodiment, when the most significant bit of n-bit data includes the sign information s, the lower (mn) bits that need to be compensated are Higher order (mn) bits can be assigned from the second most significant bits excluding the most significant bit of the original data. Also in this case, when the input data Dn is the maximum value, all the higher-order input data is “1”, so the output data Dm is also the maximum value. Further, when the input data Dn is the minimum value, all the higher-order input data is “0”, so the output data Dm is also the minimum value. Therefore, the conversion error can be reduced without performing complicated processing as in the prior art.
[0056]
In the first and second embodiments, the case where the bit length extension devices 10 and 10A of the present invention are realized by hardware (bit length extension circuit) has been described. However, the present invention is not limited to this, and software (control program) is used. Also, the functions of the first and second embodiments can be realized.
[0057]
Next, a third embodiment of the bit length extension device of the present invention by software will be described.
[0058]
(Embodiment 3)
FIG. 4 is a block diagram showing the main configuration of the data processing apparatus according to the third embodiment of the present invention.
[0059]
In FIG. 4, the data processing device 20 is constituted by a computer, and performs data processing on at least one of the bit length extending device for performing the bit length extending processing of the present invention and the input data and output data of the bit length extending device. It has a function with a data processing unit that applies
[0060]
The bit length extension device includes a ROM 21 and a RAM 22 as storage units for storing various data, and an input unit 23 that allows a user to input various operation commands and data (including received data in addition to operation input data). And an output unit 24 that displays various images, prints out data, and transmits data, and a control unit 25 that controls each unit and performs the bit length extension processing of the present invention.
[0061]
The ROM 21 stores a control program for bit length extension control processing and its data. The control program and its data can be downloaded from a readable recording medium such as a CD (optical disc) or DVD via an interface (not shown).
[0062]
The RAM 22 functions as a work memory when the control unit 25 operates.
[0063]
The control unit 25 is composed of a CPU (central processing unit) of a computer, and based on a control program for bit length extension control processing, input data Dn having a bit length n is converted to data having a bit length m larger than n. When the bit is extended to Dm, m bits of output data Dm are generated by assigning the upper (mn) bits of the input data Dn to the lower bits of the (mn) bits that need to be compensated. Control is made. The function of the data processing unit is also executed by the control unit 25.
[0064]
Specifically, the control unit 25 includes first variable generation means for generating a first variable obtained by bit-shifting n-bit input data in one direction (m−n) times, and n-bit input data in the other direction. Second variable generating means for generating a second variable bit-shifted (n− (m−n)) times and a first variable for generating m-bit output data from the logical sum of the first variable and the second variable. 1 logic synthesis means.
[0065]
The control program executed by the control unit 25 includes a first variable generation step for generating a first variable obtained by bit-shifting n-bit input data in one direction (m−n) times, and n-bit input data. A second variable generating step for generating a second variable bit-shifted (n− (m−n)) times in the direction, and a first variable for generating m-bit data from the logical sum of the first variable and the second variable. 1 logic synthesis step.
[0066]
Hereinafter, the operation of the above configuration will be described with reference to FIG.
[0067]
FIG. 5A is a diagram showing numerical values and variables as data used in the control unit 25 in FIG. 4, and FIG. 5B is a flowchart showing a bit length extension processing procedure executed by the control unit 25 in FIG. is there.
[0068]
A bit operation / arithmetic processing is performed on an input value Dn that does not include sign information s whose effective bit length n (n is a positive integer) is known in advance. By assigning n bits and reassigning the upper (mn) bits of the original data to the lower (mn) bits, the number of effective bits m (m is a positive integer with m> n) is revealed. A case where an output value (return value) Dm that does not include the encoded code information s is generated will be described. Variables A and B having a bit length sufficiently larger than the return value Dm are prepared in advance. In FIG. 5A, it is assumed that variables A and B having a bit length of 32 are prepared for n = 15 and m = 24.
[0069]
As shown in FIG. 5B, first, in step S1, a 15-bit input value Dn is assigned to variables A and B, respectively.
[0070]
Next, in step S2, a bit operation of left shift (shift in one direction) is performed (m−n) times for the variable A. In the example of FIG. 5A, the variable A is shifted left by (mn) = 24-15 = 9 bits.
[0071]
Similarly, in step S3, the bit operation of the right shift (shift in the other direction) is performed (n− (mn)) times for the variable B. At this time, the bits pushed out from the LSB are discarded. In this example, the variable B is right shifted by (n− (mn)) = 15− (24−15) = 6 bits, and the 6 bits pushed out from the LSB are discarded.
[0072]
Finally, in step S4, a logical sum of the variable A and the variable B is calculated. That is, by assigning the variable B to the variable A, a return value Dm as desired output data is generated. In this example, a 24-bit return value Dm is generated.
[0073]
Even if the input value Dn and the return value Dm include the sign information s, if the most significant bit is the sign information s, there is no change in the position. However, it may be performed as follows.
[0074]
That is, although detailed explanation is omitted here, before the input value Dn is substituted into the variables A and B in step S1, the most significant bit indicating the sign information is saved, and the most significant bit of the input value Dn is changed. The data from the second most significant bit to (n−1) bits is substituted into variables A and B.
[0075]
Next, in step S2, the left shift bit operation is performed (m−n) times for the variable A (third variable generation step; third variable generation means), and in step S3, the right shift bit is set for the variable B. The operation is performed (n- (mn) -1) times (fourth variable generation step; fourth variable generation means).
[0076]
Finally, in step S4, a logical sum of the variable A and the variable B is calculated (second logic synthesis step; second logic synthesis means). Also in this case, the return value Dm including the code information s at the highest order can be generated by assigning the variable B to the variable A and adding the saved most significant bit to the highest order.
[0077]
In the third embodiment, the case where the bit length extending apparatus of the present invention is realized by software (control program) has been described. However, the present invention is not limited to this, and the third embodiment is also implemented by hardware (bit length extending circuit). The function can be realized.
[0078]
As described above, according to the first to third embodiments, when the input data Dn having the bit length n is bit-extended to the output data Dm having the bit length m larger than n, the lower order of the output data Dm that needs to be compensated By assigning the upper (mn) bits of the input data Dn to the (mn) bits, m-bit output data Dm can be generated without performing complicated processing. If the most significant bit of the input data Dn includes the sign information s, the second (excluding the most significant bit) is excluded from the lower (mn) bits of the input data Dn that need to be compensated. Higher order (mn) bits can be assigned from the higher order data. In this way, when digital data with an n-bit length is expanded to data with an m-bit length (m> n), the lower (mn) bit-length data is reduced by an easy bit-length extension process. Can be compensated by conversion error.
[0079]
【The invention's effect】
As described above, according to the present invention, it is possible to generate data with a bit length suitable for each use environment by performing a bit length extension process of a digital signal with a minimum conversion error by a simple process. .
[Brief description of the drawings]
FIG. 1 is a block diagram showing a main configuration of Embodiments 1 and 2 of a data processing apparatus according to the present invention.
FIG. 2 is a diagram for explaining a basic principle of the present invention.
FIG. 3A is a diagram illustrating an example of data processing when code information is not included, and FIG. 3B is a diagram illustrating an example of data processing when code information is included.
FIG. 4 is a block diagram showing the main configuration of a data processing apparatus according to a third embodiment of the present invention.
5A is a diagram showing numerical values and variables used in the control unit of FIG. 4, and FIG. 5B is a flowchart showing a bit length extension processing procedure by the control unit of FIG. 4;
6A is a diagram for explaining a conventional processing example when the bit length is reduced, and FIG. 6B is a diagram for explaining a conventional processing example when the bit length is extended.
FIG. 7 is a diagram for explaining a problem of a conventional bit length extension method.
[Explanation of symbols]
1 Input circuit
2, 2A separation circuit
3, 3A synthesis circuit
4 Output circuit
10, 10A bit length expansion device
100, 100A, 200 Data processing device
21 ROM
22 RAM
23 Input section
24 Output unit
25 Control unit

Claims (13)

In a bit length extension device that extends digital data of n (n is a positive integer) bit length to digital data of m bits (m is an integer of m> n) length,
Of the m-bit data, all n-bit data of the original data is assigned to the upper n bits, and the upper (mn) bit data of the original data is reassigned to the lower (mn) bits. A bit length extension device comprising first bit length extension means for generating m-bit output data. In a bit length extension device that extends digital data of n (n is a positive integer) bit length including sign information in the most significant bit to digital data of m bits (m is an integer of m> n),
Among the m-bit data, all n-bit data of the original data is assigned to the upper n bits, and the lower (mn) bits are higher than the second most significant bit of the original data. A bit length extension method comprising second bit length extension means for generating m-bit output data by allocating data up to (mn) bits. The first bit length extension means includes
First data separation means for separating the n-bit input data into upper input data having a bit length (mn) bits and lower input data having a bit length (n- (mn));
Among the m-bit data, the upper input data is assigned to the upper (mn) bits, the lower input data is assigned to the next (n- (mn)) bits, and the next 2. The bit length extension device according to claim 1, further comprising: first data synthesis means for generating m-bit output data by reassigning the higher-order input data to the lower-order (mn) bits. The second bit length extension means includes
The n-bit input data includes the highest-order input data of the most significant bit, the higher-order input data from the second most significant bit to the bit length (mn) bits, and the bit length (n− (Mn) -1) second data separating means for separating the lower input data;
Of the m-bit data, the most significant input data is allocated to the most significant bit, and the most significant (mn) bits are allocated to the most significant (mn) bits after the second most significant bit. The lower input data is assigned to the next (n- (mn) -1) bits, and the upper input data is reassigned to the next lower (mn) bits. The bit length extension device according to claim 2, further comprising second data synthesis means for generating output data. The first bit length extending means or the second bit length extending means is:
First variable generating means for generating a first variable obtained by bit-shifting the n-bit input data in one direction (m−n) times;
Second variable generation means for generating a second variable obtained by bit-shifting the n-bit input data (n- (mn)) times in the other direction;
3. The bit length extending apparatus according to claim 1, further comprising: a first logic synthesis unit that generates m-bit output data from a logical sum of the first variable and the second variable. The second bit length extension means includes
A third variable for generating a third variable obtained by bit-shifting (n−1) -bit data in one direction (mn) times from the second-most bit next to the most significant bit of the n-bit input data Generating means;
Fourth variable generating means for generating a fourth variable obtained by bit-shifting the (n-1) -bit data in the other direction (n- (mn) -1) times;
M-1 bit data is generated from the logical sum of the third variable and the fourth variable, and the most significant bit input data is added to the most significant bit of the m-1 bit as the most significant bit data. 3. The bit length extending device according to claim 2, further comprising second logic synthesis means for generating bit output data. A data processing device that performs data processing on at least one of input data and output data of the bit length extension device according to claim 1. In a bit length extension method for extending n (n is a positive integer) bit length digital data to m bit (m is an integer of m> n) length,
Of the m-bit data, all n-bit data of the original data is assigned to the upper n bits, and the upper (mn) bit data of the original data is reassigned to the lower (mn) bits. A bit length extension method comprising a first bit length extension step for generating m-bit data. In a bit length extension method of extending n (n is a positive integer) bit length digital data including sign information in the most significant bit to m bit (m is an integer of m> n) length,
Among the m-bit data, all n-bit data of the original data is assigned to the upper n bits, and the lower (mn) bits are higher than the second most significant bit of the original data. A bit length extension method including a second bit length extension step of generating m bits of data by allocating data up to (mn) bits. The first bit length extension step or the first bit length extension step includes:
A first variable generating step for generating a first variable obtained by bit-shifting the n-bit input data in one direction (m−n) times;
A second variable generation step of generating a second variable obtained by bit-shifting the n-bit input data in the other direction (n- (mn)) times;
10. The bit length extension method according to claim 8, further comprising a first logic synthesis step of generating m-bit data from a logical sum of the first variable and the second variable. The second bit length extension step includes:
A third variable is generated by shifting data from the second most significant bit next to the most significant bit of the n-bit input data to (n−1) bits in one direction (mn) times. Variable generation step;
A fourth variable generation step of generating a fourth variable obtained by bit-shifting the (n-1) -bit data in the other direction (n- (mn) -1) times;
M-1 bit data is generated from the logical sum of the third variable and the fourth variable, and the most significant bit input data is added to the most significant bit of the m-1 bit as the most significant bit data. The bit length extending method according to claim 9, further comprising a second logic synthesis step of generating bit data. The control program for making a computer perform the step of the bit length expansion method in any one of Claims 8-11. A computer-readable readable recording medium on which the control program according to claim 12 is recorded.

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