JP2005012230A - Method of fabricating dielectric element - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method of manufacturing a dielectric element, prevented from the degradation of the reliability and yield, due to the deposition of conductive material onto a dielectric film and the sidewalls of a mask. <P>SOLUTION: The method includes steps of, while rotating a dielectric element 200 provided with an ferrodielectric capacitor made up of a lower electrode 12, a ferrodielectric film 13 and an upper electrode 14, irradiating the surface of the upper electrode 14 with ions i through a mask 19 in an oblique direction at an angle in the range 0°<α<90°, and patterning the upper electrode 14 and the ferrodielectric film 13 by means of etching. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method for manufacturing a dielectric element having a dielectric film.

  A memory in which a capacitor made of a ferroelectric film (hereinafter referred to as a ferroelectric capacitor) is provided at the gate portion of a field effect transistor (FET) is known as a non-volatile memory capable of nondestructive reading. The structure of such a ferroelectric memory includes an MFS (metal / ferroelectric / semiconductor) structure, an MFIS (metal / ferroelectric / insulator / semiconductor) structure, and an MFMIS (metal / ferroelectric / metal / insulator). Body / semiconductor) structures have been proposed.

  FIG. 14 is a schematic sectional view showing an example of a ferroelectric memory having an MFMIS structure. The ferroelectric memory shown in FIG. 14 is disclosed in, for example, Japanese Patent Laid-Open No. 5-327002.

14, the surface of the n ⁺ silicon substrate 31, a drain region 35 composed of the source region 34 and p ⁺ layer of a p ⁺ layer at a predetermined distance are formed. A region of the silicon substrate 31 between the source region 34 and the drain region 35 becomes a channel region 36. A gate insulating film 32 is formed on the channel region 36, and a gate electrode 33 is formed on the gate insulating film 32.

  An interlayer insulating film 37 is formed on the silicon substrate 31 and the gate electrode 33. A contact hole 39 is formed in the interlayer insulating film 37 on the gate electrode 33, and a wiring layer 40 is formed in the contact hole 39.

  Contact holes are provided in the interlayer insulating film 37 on the source region 34 and the drain region 35, and wiring layers 45 and 46 are formed in the contact holes, respectively. Further, a lower electrode 42 is formed on the wiring layer 40 connected to the gate electrode 33. A ferroelectric film 43 is formed on the lower electrode 42, and an upper electrode 44 is formed on the ferroelectric film 43. Also, ohmic electrodes 47 and 48 are formed on the wiring layers 45 and 46 connected to the source region 34 and the drain region 35, respectively.

In the ferroelectric memory of FIG. 14, the lower electrode 42, the ferroelectric film 43, and the upper electrode 44 constitute a ferroelectric capacitor.
JP-A-5-327062

  14, the upper electrode 44, the ferroelectric film 43, and the lower electrode 42 are formed in order to form a ferroelectric capacitor including the lower electrode 42, the ferroelectric film 43, and the upper electrode 44. It is necessary to process (pattern) by etching such as RIE (reactive ion etching).

  FIG. 15 is a schematic sectional view showing a conventional method of forming a ferroelectric capacitor. In the reactive ion etching apparatus 300 shown in FIG. 15, a conductive sample stage 302 is disposed by a conductive support member 303 at a lower portion in an etching chamber (chamber) 301. The etching chamber 301 and the support member 303 are insulated from each other by an insulating member 304. In the upper part of the etching chamber 301, an electrode 305 is disposed by a conductive support member 306 so as to face the sample stage 302. The etching chamber 301 and the support member 306 are insulated from each other by an insulating member 307.

  The etching chamber 301 is provided with a gas introduction port 308 and an exhaust port 309. The sample stage 302 and the support member 303 are connected to a high frequency power supply 310 via a capacitor 309. On the other hand, the electrode 305 and the support member 306 are grounded.

  On the sample stage 302, a dielectric element 400 having a ferroelectric capacitor to be processed is attached. In the dielectric element 400 of FIG. 15, a mask 45 made of a photoresist is formed on a ferroelectric capacitor made up of a lower electrode 42, a ferroelectric film 43 and an upper electrode 44.

  When processing the ferroelectric capacitor, a reactive gas is introduced from the gas introduction port 308 into the decompressed etching chamber 301, and high frequency power is supplied between the sample stage 302 and the electrode 305 by the high frequency power source 310. As a result, gas discharge occurs in the etching chamber 301, and the gas molecules g are ionized to generate plasma composed of ions i and electrons e.

  The ions i are accelerated toward the sample stage 302 by an electric field applied between the electrode 305 and the sample stage 302 and are irradiated perpendicularly to the surface of the dielectric element 400. The upper electrode 44, the ferroelectric film 43, and the lower electrode 42 are etched by the irradiation energy and reactivity of the ions i. Thereby, a patterned ferroelectric capacitor is formed.

  In the conventional method for forming a ferroelectric capacitor, when the upper electrode 44, the ferroelectric film 43 and the lower electrode 42 are processed by etching, Pt which is a material of the etched upper electrode 44 and lower electrode 42 is used. A conductive material such as (platinum) may be deposited on the sidewall of the ferroelectric film 43.

  In particular, when the upper electrode 44 and the lower electrode 42 are made of a material having low volatility such as Pt, the material removed by the etching is not exhausted from the exhaust port 309 and is deposited on the side wall of the ferroelectric film 43 as the deposit 50. Easy to reattach. In this case, the upper electrode 44 and the lower electrode 42 are electrically connected by the deposit 50 on the sidewall of the ferroelectric film 43. As a result, current leakage occurs between the upper electrode 44 and the lower electrode 42.

  In addition, when heat treatment is performed in order to recover and improve the characteristics of the ferroelectric film 43 in a later step, if the deposit 50 is present on the sidewall of the ferroelectric film 43, the characteristics of the ferroelectric film 43 are sufficiently recovered. And the problem of not improving arises.

  Even when the mask 45 is removed in an organic solvent or an aqueous solution, the deposit 50 on the sidewall of the ferroelectric film 43 is difficult to remove. When the deposit 50 also adheres to the side wall of the mask 45, it is difficult to remove the mask 45. Therefore, it is necessary to remove the deposit 50 on the side walls of the ferroelectric film 43 and the mask 45 with an organic solvent or the like. In this case, the deposit 50 removed from the side walls of the ferroelectric film 43 and the mask 45 becomes particles (fine particles) and reattaches to the surface of the dielectric element 400, which may adversely affect the next process.

  As described above, the deposit 50 on the side wall of the ferroelectric film 43 causes a problem that the performance of the device is lowered and the manufacturing yield is lowered.

  An object of the present invention is to provide a method of manufacturing a dielectric element in which a decrease in reliability and yield due to deposition of a conductive material on a dielectric film and a side wall of a mask is prevented.

(1) 1st invention The manufacturing method of the dielectric element which concerns on 1st invention forms the laminated structure through the process of forming the mask of a cross-sectional trapezoid shape on the laminated structure of a dielectric film and a conductive layer, and a mask And a step of processing the laminated structure by irradiating ions on the surface of the substrate, wherein the incident angle α of ions is 0 ° <α <90 ° with respect to the normal of the surface of the laminated structure. To do.

  In the method for manufacturing a dielectric element according to the present invention, ions are irradiated obliquely in a range of 0 ° <α <90 ° to the surface of the laminated structure along the inclined side surface of the trapezoidal mask. Therefore, the side walls of the conductive layer and the dielectric film are etched at a predetermined inclination angle. As a result, the conductive layer material is not deposited on the dielectric film and mask sidewalls, or even if the conductive layer material is deposited on the dielectric film and mask sidewalls, the deposit is removed by ions irradiated in an oblique direction. Is done. Therefore, a decrease in reliability and yield due to the deposition of the conductive material on the dielectric film and the side wall of the mask is prevented.

(2) Second Invention A method for manufacturing a dielectric element according to a second invention includes a step of sequentially forming a dielectric film and a second conductive layer on the first conductive layer, and a step on the second conductive layer. Forming a mask having a trapezoidal cross section on the surface, and processing at least the second conductive layer and the dielectric film by irradiating the surface of the second conductive layer through the mask with ions. The incident angle α is characterized in that 0 ° <α <90 ° with respect to the normal of the surface of the laminated structure.

  In the method of manufacturing a dielectric element according to the present invention, ions are inclined in the range of 0 ° <α <90 ° with respect to the surface of the second conductive layer along the inclined side surface of the trapezoidal mask. Since irradiation is performed, at least the second conductive layer and the sidewall of the dielectric film are formed at a predetermined inclination angle. As a result, the material of the second conductive layer is not deposited on the side walls of the dielectric film and the mask, or even when the material of the second conductive layer is deposited on the side walls of the dielectric film and the mask, the deposit is inclined. It is removed by the irradiated ions. Therefore, a decrease in reliability and yield due to the deposition of the conductive material on the dielectric film and the side wall of the mask is prevented.

(3) Third invention A method for manufacturing a dielectric element according to a third invention is the method for manufacturing a dielectric element according to the first or second invention, wherein the dielectric film is a ferroelectric film. Features. In this case, the reliability and yield of the dielectric element including the ferroelectric film are improved.

  ADVANTAGE OF THE INVENTION According to this invention, the manufacturing method of the dielectric element by which the reliability by the deposition of the electroconductive material to the dielectric film and the side wall of a mask and the fall of the yield was prevented can be provided.

  FIG. 1 is a schematic cross-sectional view showing a dielectric element manufacturing method according to the first embodiment of the present invention.

  In FIG. 1, an ion milling apparatus (ion beam etching apparatus) 100 has an ion irradiation chamber 101 and a plasma generation chamber 102. The ion irradiation chamber 101 and the plasma generation chamber 102 are insulated from each other by an insulating member 103.

  A sample stage 104 is rotatably provided in the ion irradiation chamber 101 by a rotating member 105. The rotation member 105 is rotationally driven around the rotation axis Z by a rotation drive mechanism (not shown). The sample stage 104 is tilted so that the normal of the surface thereof forms a predetermined angle α with respect to the rotation axis Z of the rotating member 105. On the sample stage 104, a dielectric element 200 having a ferroelectric capacitor to be processed, which will be described later, is attached.

  A magnet coil 106 for generating a magnetic field in the plasma generation chamber 102 is attached around the plasma generation chamber 102. A waveguide 107 for introducing a microwave into the plasma generation chamber 102 is attached to an end face outside the plasma generation chamber 102.

  Grids 108 and 109 are arranged perpendicular to the rotation axis Z of the rotating member 105 at the boundary between the ion irradiation chamber 101 and the plasma generation chamber 102. The ion irradiation chamber 101 is provided with an exhaust port 110, and the plasma generation chamber 102 is provided with a gas introduction port 111.

  In the dielectric element 200 of FIG. 1, an FET (not shown) is formed on a p-type single crystal silicon substrate 1, and a ferroelectric composed of a lower electrode 12, a ferroelectric film 13, and an upper electrode 14 on the FET. A body capacitor is formed. The lower electrode 12 of the ferroelectric capacitor is embedded in the interlayer insulating film 7. A mask 19 made of a photoresist is formed on the upper electrode 14.

  In the example of FIG. 1, in this state, the ferroelectric film 13 and the upper electrode 14 are patterned by etching as follows.

  A reactive gas is introduced into the plasma generation chamber 102 from the gas inlet 111, a magnetic field is generated by the magnet coil 106, and a microwave is generated by the waveguide 107. As a result, gas discharge occurs in the plasma generation chamber 102, and a plasma composed of ions i and electrons e is generated.

  When an acceleration voltage is applied between the grids 108 and 109, ions i are accelerated from the plasma generation chamber 102 toward the sample stage 104 in the ion irradiation chamber 101. By rotating the rotating member 105 around the rotation axis Z by a rotation driving mechanism (not shown), the ion i is in a state where the normal of the surface of the dielectric element 200 and the incident direction of the ion i form an angle α. Is irradiated in an oblique direction to the surface of the rotating dielectric element 200. Thereby, the upper electrode 14 and the ferroelectric film 13 are etched.

As the reaction gas, for example, a mixed gas of Ar and SF ₆ (10%) is used. The pressure in the ion irradiation chamber 101 is set to 2 × 10 ⁻⁴ Torr, for example. As plasma generation conditions, the frequency of the microwave is 2.45 GHz, the strength of the magnetic field is 875 G (Gauss), and the microwave output is 200 to 500 W. The acceleration voltage is set to 200 to 1000 V, for example. The incident angle α of the ions i to the surface of the dielectric element 200 is 10 to 80 °, and the rotation speed of the sample stage 104 is 4 ° / second.

Note that other gases such as Cl ₂ , CF ₄ , HBr, and BCl ₃ may be used as an etching gas, or a mixed gas thereof may be used.

  In the method of the present embodiment, ions i are irradiated on the surface of the rotating dielectric element 200 in an oblique direction, whereby the side walls of the upper electrode 14 and the ferroelectric film 13 are etched at a predetermined inclination angle α. . Thereby, even if the material of the upper electrode 14 is not deposited on the sidewalls of the ferroelectric film 13 and the mask 19, or the material of the upper electrode 14 is deposited on the sidewalls of the ferroelectric film 13 and the mask 19, the deposit is slanted. It is removed by ions irradiated in the direction.

  Therefore, no current leakage occurs between the upper electrode 14 and the lower electrode 12. Further, it becomes possible to sufficiently recover and improve the characteristics of the ferroelectric film 13 by a heat treatment in a later step. Further, the mask 19 can be easily removed, and the deposited particles are not reattached to the dielectric element 200. As a result, a decrease in reliability and yield due to the deposition of the conductive material on the side walls of the ferroelectric film 13 and the mask 19 is prevented.

  FIG. 2 is a schematic cross-sectional view showing a dielectric element manufacturing method according to the second embodiment of the present invention.

  In FIG. 2, an ion milling apparatus (ion beam etching apparatus) 100A has an ion irradiation chamber 101 and two plasma generation chambers 102a and 102b. The ion irradiation chamber 101 and the plasma generation chambers 102a and 102b are insulated from each other by insulating members 103a and 103b, respectively.

  A sample stage 104 is rotatably provided in the ion irradiation chamber 101 by a rotating member 105. The rotation member 105 is rotationally driven around the rotation axis Z by a rotation drive mechanism (not shown). The surface of the sample stage 104 is perpendicular to the rotation axis Z of the rotating member 105. On the sample stage 104, a dielectric element 200 having a ferroelectric capacitor similar to that of the first embodiment is attached.

  Magnet coils 106a and 106b for generating a magnetic field in the plasma generation chambers 102a and 102b are attached around the plasma generation chambers 102a and 102b, respectively. In addition, waveguides 107 for introducing microwaves into the plasma generation chambers 102a and 102b are attached to the outer peripheral portions of the plasma generation chambers 102a and 102b, respectively.

  Grids 108 a and 109 a are arranged at a boundary portion between the ion irradiation chamber 101 and the plasma generation chamber 102 a so as to form a predetermined angle α with respect to the surface of the sample stage 104. In addition, grids 108 b and 109 b are arranged at a boundary portion between the ion irradiation chamber 101 and the plasma generation chamber 102 b so as to form a predetermined angle α with respect to the surface of the sample stage 104. The ion irradiation chamber 101 is provided with an exhaust port 110, and the plasma generation chambers 102a and 102b are provided with gas introduction ports 111a and 111b, respectively.

  In the example of FIG. 2, the ferroelectric film 13 and the upper electrode 14 of the dielectric element 200 are patterned by etching as follows.

  A reactive gas is introduced into the plasma generation chambers 102a and 102b from the gas inlets 111a and 111b, respectively, a magnetic field is generated by the magnet coils 106a and 106b, and a microwave is generated by the waveguide 107. Thereby, gas discharge occurs in the plasma generation chambers 102a and 102b, and plasma composed of ions i and electrons e is generated.

  When an acceleration voltage is applied between the grids 108a and 109a and between the grids 108b and 109b, the ions i are accelerated from the plasma generation chambers 102a and 102b toward the sample stage 104 in the ion irradiation chamber 101, respectively. By rotating the rotating member 105 around the rotation axis Z by a rotation driving mechanism (not shown), the ion i is in a state where the normal of the surface of the dielectric element 200 and the incident direction of the ion i form an angle α. Is irradiated in an oblique direction to the surface of the rotating dielectric element 200. Thereby, the upper electrode 14 and the ferroelectric film 13 are etched.

  The reaction gas, the pressure in the ion irradiation chamber 101, the etching conditions, the acceleration voltage, the ion incident angle α on the surface of the dielectric element 200, and the rotation speed of the sample stage 104 are the same as in the first embodiment.

  In the method of this embodiment, the ions i are irradiated on the surface of the rotating dielectric element 200 in an oblique direction, whereby the side walls of the upper electrode 14 and the dielectric film 13 are etched at a predetermined inclination angle α. Thereby, even if the material of the upper electrode 14 is not deposited on the sidewalls of the ferroelectric film 13 and the mask 19, or the material of the upper electrode 14 is deposited on the sidewalls of the ferroelectric film 13 and the mask 19, the deposit is slanted. It is removed by ions irradiated in the direction.

  Therefore, no current leakage occurs between the upper electrode 14 and the lower electrode 12. Further, it becomes possible to sufficiently recover and improve the characteristics of the ferroelectric film 13 by a heat treatment in a later step. Further, the mask 19 can be easily removed, and the deposited particles are not reattached to the dielectric element 200. As a result, a decrease in reliability and yield due to the deposition of the conductive material on the side walls of the ferroelectric film 13 and the mask 19 is prevented.

  FIG. 3 is a schematic sectional view showing a method for manufacturing a dielectric element in the third embodiment of the present invention.

  In FIG. 3, an ion milling apparatus (ion beam etching apparatus) 100B includes an ion irradiation chamber 101 and a plasma generation chamber 102. The ion irradiation chamber 101 and the plasma generation chamber 102 are insulated from each other by an insulating member 103.

  Within the ion irradiation chamber 101, a sample stage 104 is disposed by a support member 105a. On the sample stage 104, a dielectric element 200 having a ferroelectric capacitor similar to that of the first embodiment is attached.

  A magnet coil 106 for generating a magnetic field in the plasma generation chamber 102 is attached around the plasma generation chamber 102. A waveguide 107 for introducing a microwave into the plasma generation chamber 102 is attached to an end face outside the plasma generation chamber 102.

  Grids 108 and 109 are arranged in parallel with the surface of the sample stage 104 at the boundary between the ion irradiation chamber 101 and the plasma generation chamber 102. The ion irradiation chamber 101 is provided with an exhaust port 110, and the plasma generation chamber 102 is provided with a gas introduction port 111.

  In the present embodiment, a mask 19a made of a photoresist having a trapezoidal cross section with a tapered side wall is formed on the upper electrode 14 of the dielectric element 200. In the example of FIG. 3, in this state, the ferroelectric film 13 and the upper electrode 14 are patterned by etching as follows.

  A reactive gas is introduced into the plasma generation chamber 102 from the gas inlet 111, a magnetic field is generated by the magnet coil 106, and a microwave is generated by the waveguide 107. As a result, gas discharge occurs in the plasma generation chamber 102, and a plasma composed of ions i and electrons e is generated.

  When an acceleration voltage is applied between the grids 108 and 109, ions i are accelerated from the plasma generation chamber 102 toward the sample stage 104 in the ion irradiation chamber 101. In this case, the ions i are irradiated on the surface of the dielectric element 200 along the inclined side wall of the mask 19a. Thereby, the upper electrode 14 and the ferroelectric film 13 are etched.

  The reaction gas, the pressure in the ion irradiation chamber 101, the plasma generation conditions, and the acceleration voltage are the same as in the first embodiment.

  In the method of this embodiment, ions i are irradiated obliquely onto the surface of the dielectric element 200 along the inclined side walls of the mask 19a, so that the side walls of the upper electrode 14 and the ferroelectric film 13 are predetermined. Etched at an angle of inclination. This inclination angle corresponds to the inclination angle in the first and second embodiments. Thereby, even if the material of the upper electrode 14 is not deposited on the sidewalls of the ferroelectric film 13 and the mask 19, or the material of the upper electrode 14 is deposited on the sidewalls of the ferroelectric film 13 and the mask 19, the deposit is slanted. It is removed by ions i irradiated in the direction.

  Therefore, no current leakage occurs between the upper electrode 14 and the lower electrode 12. Further, it becomes possible to sufficiently recover and improve the characteristics of the ferroelectric film 13 by a heat treatment in a later step. Further, the mask 19 can be easily removed, and the deposited particles are not reattached to the dielectric element 200. As a result, a decrease in reliability and yield due to the deposition of the conductive material on the side walls of the ferroelectric film 13 and the mask 19 is prevented.

Here, using the ion milling apparatus 100 of the first embodiment, the presence / absence of sidewall deposits according to the incident angle of ions was measured. In this measurement, a sample 500 shown in FIG. 4 was used. The sample 500 is obtained by sequentially forming a 3000 Å thick SiO ₂ film 502, a 500 Å thick Ti film 503, a 2000 Å thick Pt film 504, and a mask 505 made of a photoresist on a silicon substrate 501. The Ti film 503 is provided to improve the adhesion between the Pt film 504 and the SiO ₂ film 502.

The sample 500 is set on the sample stage 104, and the sample stage 104 is rotated at a rotation speed of 4 ° / second while irradiating the surface of the sample 500 with the incident angle α, and the presence or absence of deposit on the side wall of the mask 505 is checked. Observed. As a reaction gas, a mixed gas of 10% SF ₆ and Ar was used, the microwave output was 300 W, the acceleration voltage was 600 V, and the etching time was 8 minutes. The measurement results are shown in Table 1.

  As shown in Table 1, when the incident angle α is 0 °, Pt is deposited on the side wall of the mask 505 made of photoresist, whereas when the incident angle α is 25 ° or more, Pt is formed on the side wall of the mask 505. Not deposited.

  As described above, it was found that deposits on the side wall were not generated by irradiating the surface of the sample 500 with ions at an inclined angle. The incident angle of ions is set to an appropriate value within a range larger than 0 ° and smaller than 90 ° according to the reaction gas, etching conditions, and the like.

  FIG. 5 is a schematic cross-sectional view showing an example of a MFMIS structure ferroelectric memory having a ferroelectric capacitor formed by the method of the present invention.

5, the drain region 5 consisting of a source region 4 and the n ⁺ layer made of n ⁺ layer at a predetermined distance on the surface of the p-type single crystal silicon substrate 1 is formed. A region of the silicon substrate 1 between the source region 4 and the drain region 5 becomes a channel region 6.

The gate insulating film 2 made of SiO ₂ on the channel region 6 is formed. A gate electrode 3 made of polysilicon is formed on the gate insulating film 2. An interlayer insulating film 7 is formed on the silicon substrate 1 so as to cover the gate electrode 3 and the gate insulating film 2. A buffer layer 8 made of TiO ₂ (titanium oxide), CeO ₂ (cerium oxide) or the like is formed on the interlayer insulating film 7.

Contact holes 9 are formed in the interlayer insulating film 7 and the buffer layer 8 on the gate electrode 3. In the contact hole 9, a connection layer (plug) 10 made of a conductive material such as polysilicon or W (tungsten) is formed to a predetermined depth. A lower electrode 12 made of a conductive material such as Pt (platinum) or IrO ₂ (iridium oxide) is formed on the connection layer 10 in the contact hole 9.

A ferroelectric film 13 made of PZT (lead zirconate titanate) or SrBiTaO having a perovskite crystal structure is formed on the buffer layer 8 so as to be in contact with the upper surface of the lower electrode 12. An upper electrode 14 made of a conductive material such as Pt or IrO ₂ is formed on the ferroelectric film 13.

  Contact holes are respectively formed in the buffer layer 8 and the interlayer insulating film 7 on the source region 4 and the drain region 5, and the source electrode 15 and the drain electrode 16 made of a conductive material such as polysilicon are respectively formed in the contact holes. Is formed. On the source electrode 15 and the drain electrode 16, wiring layers 17 and 18 are formed, respectively.

  In the ferroelectric memory of FIG. 5, the lower electrode 12, the ferroelectric film 13, and the upper electrode 14 constitute a ferroelectric capacitor.

  In this embodiment, the lower electrode 12 corresponds to a lower electrode layer or a first conductive layer, and the upper electrode 14 corresponds to an upper electrode layer or a second conductive layer.

  6, FIG. 7, FIG. 8 and FIG. 9 are process sectional views showing a method of manufacturing the ferroelectric memory of FIG.

First, as shown in FIG. 6A, a gate insulating film 2 made of SiO _{2 having a} thickness of 100 mm is formed on a p-type silicon substrate 1 by a thermal oxidation method, and a CVD method (chemical process) is formed on the gate insulating film 2. The gate electrode 3 made of polysilicon having a film thickness of 2000 mm is formed by a chemical vapor deposition method.

Next, as shown in FIG. 6B, the gate electrode 3 and the gate insulating film 2 except for the gate formation region on the silicon substrate 1 are removed using a dry process such as reactive ion etching or ion milling. The gate part is formed. Then, using the gate electrode 3 as an ion implantation mask, an n-type impurity (n-type dopant) is ion-implanted into the surface of the silicon substrate 1 and heat treatment is performed. Thereby, a source region 4 and a drain region 5 made of an n-type impurity layer (n ⁺ layer) are formed in a self-aligned manner with respect to the gate insulating film 2 and the gate electrode 3 on the silicon substrate 1, respectively. A region of the silicon substrate 1 between the source region 4 and the drain region 5 becomes a channel region 6.

Thereafter, as shown in FIG. 6C, an interlayer insulating film 7 made of SiO ₂ or the like having a film thickness of about 6000 mm is formed on the silicon substrate 1 so as to cover the gate electrode 3 and the gate insulating film 2 by a CVD method or the like. To do.

Next, as shown in FIG. 7D, a buffer layer 8 made of TiO ₂ , CeO ₂ or the like and having a thickness of 500 mm is formed on the interlayer insulating film 7. Thereafter, as shown in FIG. 7E, a contact hole 9 is provided in the buffer layer 8 and the interlayer insulating film 7 on the gate electrode 3 by lithography.

  Then, as shown in FIG. 7F, a connection layer 10 made of a conductive material such as polysilicon or W is formed in the contact hole 9. In this case, the thickness of the connection layer 10 is set so that the distance from the upper end of the contact hole 9 to the upper surface of the connection layer 10 is 1500 mm. As a method for forming the connection layer 10, a conductive layer is formed inside the contact hole 9 and the entire surface of the buffer layer 8, and then the conductive layer on the buffer layer 8 is removed by etching the entire surface.

  Next, as shown in FIG. 8 (g), the TiN, the sputtering method or the like is used to prevent oxidation of the connection layer 10 and diffusion of impurities to the gate portion inside the contact hole 9 and the entire surface of the buffer layer 8. A diffusion barrier layer 11 made of a conductive material such as TaSiN is formed.

8H, the entire surface of the diffusion barrier layer 11 is etched to remove the diffusion barrier layer 11 on the buffer layer 8, and the upper surface of the diffusion barrier layer 11 in the contact hole 9 is The buffer layer 11 is etched back until it becomes lower than the upper surface of the buffer layer 8. In this case, a mixed gas of BCl ₃ and Cl ₂ is used as an etching gas, and the etching conditions are a high frequency output of 250 W and a pressure of 2 × 10 ⁻² Torr. Incidentally, the mixed gas of the Ar, may be mixed other gases such as N _2. In this way, the diffusion barrier layer 11 having a thickness of 300 mm is formed on the connection layer 10 in the contact hole 9. This diffusion barrier layer 11 becomes a part of the lower electrode 12 formed in the next step.

Next, as shown in FIG. 8I, a lower electrode 12 having a thickness of 3000 mm made of a conductive material such as Pt or IrO ₂ is formed on the buffer layer 8 and the diffusion barrier layer 11 in the contact hole 9. To do. As the material of the lower electrode 12, other materials may be used as long as the ferroelectric crystal is grown on the lower electrode 12. For example, RuO _x (ruthenium oxide) may be used.

Next, as shown in FIG. 9 (j), the lower electrode 12 is planarized by etch back or CMP (chemical mechanical polishing) or the like to leave the lower electrode 12 only in the contact hole 9 and contact. A lower electrode 12 having a thickness of 1200 mm is formed in the hole 9. In this case, Cl ₂ is used as the etching gas, and the etching conditions are a high frequency output of 300 W and a pressure of 3 × 10 ⁻³ Torr. Other gases such as Ar, HBr, and BCl ₃ may be used as an etching gas, or a mixed gas thereof may be used.

  Instead of etching back the diffusion barrier layer 11 in the step of FIG. 8 (h), after the diffusion barrier layer 11 and the lower electrode 12 are continuously formed, the lower electrode 12 and the diffusion barrier layer 11 are etched back simultaneously. Planarization by CMP may be performed.

  Next, as shown in FIG. 9K, a ferroelectric film 13 having a thickness of 2000 mm made of PZT, SrBiTaO or the like is formed on the lower electrode 12 and the buffer layer 8 by a sol-gel method, a sputtering method, a CVD method, or the like. To do.

Next, as shown in FIG. 9L, an upper electrode 14 made of a conductive material such as Pt or IrO _{2 having a} thickness of 1500 mm is formed on the ferroelectric film 13 by sputtering.

  Thereafter, as shown in FIG. 10 (m), a mask 19 made of a photoresist is formed on the upper electrode 44, and the mask 19 is formed by the method of the first embodiment, the second embodiment, or the third embodiment. By irradiating the surface of the upper electrode 14 with ions, the upper electrode 14 and the ferroelectric film 13 are patterned by etching. At the time of etching, the entire buffer layer 8 may be etched. The ferroelectric film 13 only needs to be in contact with the upper surface of the lower electrode 12, and does not necessarily have to straddle the buffer layer 8.

  Next, as shown in FIG. 5, contact holes are provided in the buffer layer 8 and the interlayer insulating film 7 on the source electrode 4 and the drain electrode 5, respectively, and the contact holes are made of a conductive material such as polysilicon. A source electrode 15 and a drain electrode 16 are formed. Finally, wiring layers 17 and 18 made of Al are formed on the source electrode 15 and the drain electrode 16. In this way, the ferroelectric memory of FIG. 5 is manufactured.

  In the above ferroelectric memory manufacturing method, since the method of the first, second or third embodiment is used for patterning the upper electrode 14 and the ferroelectric film 13, the material of the upper electrode 14 is used. Is not deposited on the side walls of the ferroelectric film 13 and the mask 19. Therefore, the reliability and yield of the ferroelectric memory due to the deposition of the conductive material on the side walls of the ferroelectric film 13 and the mask 19 are prevented.

  In addition, since the lower electrode 12 is provided in the contact hole 9 of the interlayer insulating film 7, when the upper electrode 14 and the ferroelectric film 13 are patterned by etching, the conductive material of the lower electrode 12 is the ferroelectric film 13. And it does not deposit on the side wall of the mask 19. Therefore, the reliability and yield of the ferroelectric memory due to the deposition of the conductive material on the side walls of the ferroelectric film 13 and the mask 19 are sufficiently prevented.

Further, since the ferroelectric film 13 is formed on the interlayer insulating film 7 via the buffer layer 8 in the step of FIG. 9K, the stress of the ferroelectric film 13 is relaxed by the buffer layer 8, The generation of cracks in the ferroelectric film 13 is prevented, and reaction of constituent elements (for example, reaction of Pb and SiO ₂ ) and mutual diffusion occur between the ferroelectric film 13 and the interlayer insulating film 7. Is prevented. As a result, the reliability and yield of the ferroelectric memory are further improved.

  Further, since the ferroelectric film 13 is formed on the lower electrode 12 made of a material having low reactivity such as Pt, and the interlayer insulating film 7 is provided between the ferroelectric film 13 and the silicon substrate 1. In addition, reaction of constituent elements and mutual diffusion between the ferroelectric film 13 and the silicon substrate 1 are sufficiently prevented.

  Here, the operation of the ferroelectric memory of FIG. 5 will be described. A positive voltage sufficient to reverse the polarization of the ferroelectric film 13 is applied to the upper electrode 14, and the voltage of the upper electrode 14 is set to 0 again. Thereby, the interface between the ferroelectric film 13 and the upper electrode 14 is negatively charged, and the interface with the lower electrode 12 is charged positively.

  In this case, the interface between the lower electrode 12 and the ferroelectric film 13 is negatively charged, and the interface between the gate electrode 3 and the gate insulating film 2 is positively charged. As a result, an inversion layer is formed in the channel region 6 between the source region 4 and the drain region 5, and the FET is turned on even though the voltage of the upper electrode 14 is zero.

  Conversely, a negative voltage sufficient to reverse the polarization of the ferroelectric film 13 is applied to the upper electrode 14, and the voltage of the upper electrode 14 is set to 0 again. As a result, the interface between the ferroelectric film 13 and the upper electrode 14 is positively charged, and the interface with the lower electrode 12 is negatively charged.

  In this case, the interface between the lower electrode 12 and the ferroelectric film 13 is positively charged, and the interface between the gate electrode 3 and the gate insulating film 2 is negatively charged. As a result, the inversion layer is not formed in the channel region 6 between the source region 4 and the drain region 5, and the FET is turned off.

  Thus, if the ferroelectric film 13 is sufficiently polarized, the FET can be selectively turned on or off even after the voltage applied to the upper electrode 14 is reduced to zero. Therefore, the data “1” and “0” stored in the ferroelectric memory can be determined by detecting the current between the source and the drain.

  The method for manufacturing a dielectric element according to the present invention is not limited to the ferroelectric memory of FIG. 5 but can be applied to various ferroelectric memories having ferroelectric capacitors.

  FIG. 11 is a schematic cross-sectional view showing another example of a ferroelectric memory having an MFMIS structure.

  In FIG. 11, a source region 22 made of an n + layer and a drain region 23 made of an n + layer are formed on the surface of a p-type silicon substrate 21 at a predetermined interval. A region of the silicon substrate 21 between the source region 22 and the drain region 23 becomes a channel region 24. On the channel region 24, a gate insulating film 25, a lower electrode 26, a ferroelectric film 27, and an upper electrode 28 are formed in this order.

  In the ferroelectric memory of FIG. 11, the lower electrode 26, the ferroelectric film 27, and the upper electrode 28 constitute a ferroelectric capacitor. In forming the ferroelectric capacitor, the method of the first embodiment, the second embodiment, or the third embodiment can be used.

  In this case, after the ferroelectric film 27 and the upper electrode 28 are formed in order on the lower electrode 26, a mask made of a photoresist is formed on the upper electrode 28, and the first and second embodiments are formed. Alternatively, the upper electrode 28, the ferroelectric film 27, and the lower electrode 26 are patterned by etching by the method of the third embodiment.

  FIG. 12 is a schematic sectional view showing an example of a ferroelectric memory having an MFIS structure.

12, the surface of the p-type silicon substrate 21, source region 22 and n ⁺ drain region 23 comprising a layer consisting of n ⁺ layer at a predetermined distance are formed. A region of the silicon substrate 21 between the source region 22 and the drain region 23 becomes a channel region 24. On the channel region 24, a gate insulating film 25, a ferroelectric film 27, and a gate electrode 28a are sequentially formed.

  In the ferroelectric memory of FIG. 12, the channel region 24, the gate insulating film 25, the ferroelectric film 27, and the gate electrode 28a of the p-type silicon substrate 21 constitute a ferroelectric capacitor. In forming the ferroelectric capacitor, the method of the first embodiment, the second embodiment, or the third embodiment can be used.

  In this case, after the gate insulating film 25, the ferroelectric film 27, and the gate electrode 28a are formed in this order on the p-type silicon substrate 21, a mask made of a photoresist is formed on the gate electrode 28a. The gate electrode 28a, the ferroelectric film 27, and the gate insulating film 25 are patterned by etching by the method of the example, the second example, or the third example.

  FIG. 13 is a schematic sectional view showing an example of a ferroelectric memory having an MFS structure.

13, the surface of the p-type silicon substrate 21, source region 22 and n ⁺ drain region 23 comprising a layer consisting of n ⁺ layer at a predetermined distance are formed. A region of the silicon substrate 21 between the source region 22 and the drain region 23 becomes a channel region 24. On the channel region 24, a ferroelectric film 27 and a gate electrode 28a are sequentially formed.

  In the ferroelectric memory of FIG. 13, the channel region 24, the ferroelectric film 27, and the gate electrode 28a of the p-type silicon substrate 21 constitute a ferroelectric capacitor. In forming the ferroelectric capacitor, the method of the first embodiment, the second embodiment, or the third embodiment can be used.

  In this case, after the ferroelectric film 27 and the gate electrode 28a are formed in order on the p-type silicon substrate 21, a mask made of a photoresist is formed on the gate electrode 28a. The gate electrode 28a and the ferroelectric film 27 are patterned by etching by the method of the embodiment or the third embodiment.

  The manufacturing method of the present invention can also be applied to a ferroelectric memory having the structure of FIG. In this case, after forming the lower electrode 42, the ferroelectric film 43 and the upper electrode 44 in this order on the interlayer insulating film 37, a mask made of photoresist is formed on the upper electrode 44, and the first embodiment, The upper electrode 44, the ferroelectric film 43, and the lower electrode 42 are processed by etching by the method of the second embodiment or the third embodiment.

  In addition, as the ferroelectric films 13, 27, 43, ferroelectrics made of the following materials may be used.

  (1) A bismuth-based layered ferroelectric material represented by the following general formula may be used.

(Bi ₂ O ₂ ) ²⁺ (A _n-1 B _n O _{3n + 1} ) ^2-
A is Sr, Ca, Ba, Pb, Bi, K, or Na, and B is Ti, Ta, Nb, W, or V.

When n = 1:
・ Bi ₂ WO ₆
・ Bi ₂ VO _5.5
For n = 2:
・ Bi ₂ O ₃ / SrTa ₂ O ₆
(SrBi ₂ Ta ₂ O ₉ ): SBT
Bi ₂ O ₃ / SrNb ₂ O ₆
(SrBi ₂ Nb ₂ O ₉ )
For n = 3:
_{· Bi 2 O 3 / SrTa 2} O 6 / BaTiO 3
_{· Bi 2 O 3 / SrTaO 6} / SrTiO 3
・ Bi ₂ O ₃ / Bi ₂ Ti ₃ O ₉
(Bi ₄ Ti ₃ O ₁₂ ): BIT
For n = 4:
_{· Bi 2 O 3 / Sr 3} Ti 4 O 12
(Sr ₃ Bi ₂ Ti ₄ O ₁₅ )
_{· Bi 2 O 3 / Bi 2} Ti 3 O 9 / SrTiO 3
(SrBi ₄ Ti ₄ O ₁₅ )
(2) A ferroelectric (isotropic material system) represented by the following general formula may be used.

_{· Pb (Zr X Ti 1-} X) O 3: PZT (PbZr 0.5 Ti 0.5) O 3
_{· (Pb 1-Y La Y} ) (Zr X Ti 1-X) O 3: PLZT
・ (Sr _1-X Ca _X ) TiO _{3
· (Sr 1-X Ba X} ) TiO 3: (Sr 0.4 Ba 0.6) TiO 3
・ (Sr _1-XY Ba _{X MY} ) Ti _1-Z N _Z O ₃
M is La, Bi, Sb or Y, and N is Nb, V, Ta, Mo or W.

・ Sr ₂ Nb ₂ O ₇
・ Sr ₂ Ta ₂ O ₇
・ Pb ₅ Ge ₃ O ₁₁
・ (Pb, Ca) TiO ₃
As a method of forming the ferroelectric films 13, 27, and 43, depending on the material of the ferroelectric films 13, 27, and 43, a molecular beam epitaxy method, a laser ablation method, a laser molecular beam epitaxy method, and a sputtering method ( RF type, DC type, or ion beam type), reactive vapor deposition, MOCVD (metal organic chemical vapor deposition), mist deposition, sol-gel, or the like can be used.

The material of the lower electrodes 12, 26, 42 and the upper electrodes 14, 28, 44 is not limited to Pt or IrO ₂ , but other noble metals (Au, Ag, Pt, Ru, Rh, Pb, Os, Ir, etc.), refractory metal (Co, W, Ti, etc.), a refractory metal compound (TiN, etc.), conductive oxides _{(RuO 2, RhO 2, OsO} 2, IrO 2, ReO 2, ReO 3, MoO 2, WO 2, _{SrRuO 3, Pb 2 Ru 2 O} 3-X, Bi 2 Ru 2 O 7-X , etc.), or an alloy may be used of each of these materials.

  Further, the lower electrodes 12, 26, 42 and the upper electrodes 14, 28, 44 may have a multilayer structure of the above materials, for example, a two-layer structure in which a Pt layer is formed on a Ti layer. .

  Further, the material of the gate electrode 3 and the connection layer 10 is not limited to polysilicon or W, and other conductive materials may be used.

  Further, in the above embodiment, the FET is formed on the silicon substrate 1, but the FET may be formed on another semiconductor substrate or semiconductor layer.

  In the above embodiment, the ferroelectric memory having the n-type channel has been described. However, the ferroelectric memory having the p-type channel can be realized by reversing the conductivity type of each layer.

  In the above embodiment, the case where the present invention is applied to the formation of a ferroelectric capacitor of a ferroelectric memory that operates as a nonvolatile memory has been described. However, the present invention relates to a ferroelectric memory that performs a volatile operation. The present invention can also be applied to the formation of ferroelectric capacitors.

  Furthermore, the present invention can also be applied to the formation of a dielectric capacitor having a structure in which a dielectric film is sandwiched between conductive layers, or another dielectric element having a laminated structure of a dielectric film and a conductive layer.

It is typical sectional drawing which shows the manufacturing method of the dielectric element in the 1st Example of this invention. It is typical sectional drawing which shows the manufacturing method of the dielectric element in the 2nd Example of this invention. It is typical sectional drawing which shows the manufacturing method of the dielectric element in the 2nd Example of this invention. It is typical sectional drawing which shows the measuring method for measuring the relationship between the incident angle of ion, and the presence or absence of a side wall deposit. It is a typical sectional view showing an example of a ferroelectric memory which has a ferroelectric capacitor formed by the manufacturing method of the present invention. FIG. 6 is a process cross-sectional view illustrating a method for manufacturing the ferroelectric memory of FIG. 5. FIG. 6 is a process cross-sectional view illustrating a method for manufacturing the ferroelectric memory of FIG. 5. FIG. 6 is a process cross-sectional view illustrating a method for manufacturing the ferroelectric memory of FIG. 5. FIG. 6 is a process cross-sectional view illustrating a method for manufacturing the ferroelectric memory of FIG. 5. FIG. 6 is a process cross-sectional view illustrating a method for manufacturing the ferroelectric memory of FIG. 5. It is a typical sectional view showing other examples of a ferroelectric memory which has a ferroelectric capacitor formed by the manufacturing method of the present invention. FIG. 10 is a schematic cross-sectional view showing still another example of a ferroelectric memory having a ferroelectric capacitor formed by the manufacturing method of the present invention. FIG. 10 is a schematic cross-sectional view showing still another example of a ferroelectric memory having a ferroelectric capacitor formed by the manufacturing method of the present invention. It is a typical sectional view showing an example of a ferroelectric memory which has a ferroelectric capacitor. It is typical sectional drawing which shows the formation method of the conventional ferroelectric capacitor.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Silicon substrate 2 Gate insulating film 3 Gate electrode 4 Source region 5 Drain region 6 Channel region 7 Interlayer insulating film 8 Buffer layer 9 Contact hole 10 Connection layer 11 Diffusion barrier layer 12, 26, 42 Lower electrode 13, 27, 43 Ferroelectricity Body membrane 14, 28, 44 Upper electrode

Claims (3)

Forming a mask having a trapezoidal cross section on the laminated structure of the dielectric film and the conductive layer;
Processing the laminated structure by irradiating the surface of the laminated structure with ions through the mask, and
The dielectric element manufacturing method, wherein an incident angle α of the ions is 0 ° <α <90 ° with respect to a normal line of the surface of the laminated structure. Forming a dielectric film and a second conductive layer in order on the first conductive layer;
Forming a trapezoidal mask on the second conductive layer;
Processing at least the second conductive layer and the dielectric film by irradiating the surface of the second conductive layer with ions through the mask,
The dielectric element manufacturing method, wherein an incident angle α of the ions is 0 ° <α <90 ° with respect to a normal line of the surface of the laminated structure. The method of manufacturing a dielectric element according to claim 1, wherein the dielectric film is a ferroelectric film.

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