JPH1168057A - Dielectric device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a dielectric device which is superior in polarization characteristic, enhanced in productivity, and reduced in manufacturing cost. SOLUTION: A source region 4 and a drain region 5 are formed on the surface of a silicon substrate 1, and a gate-insulating film 2 and a gate electrode are successively formed on a channel region between the source region 4 and the drain region 5. An interlayered insulating film 7 is formed on the silicon substrate 1, so as to cover the gate electrode 3 and the gate-insulating film 2, and a contact hole 9 is bored in the interlayered insulating film 7 on the gate electrode 3. A connecting layer 10 and a lower electrode 12 of Bi2 Sr2 CuO6 are formed inside the contact hole 9. A ferroelectric film 13 of SrBi2 Ta2 O9 and an upper electrode 14 of Bi2 Sr2 CuO6 are successively formed on the interlayered insulating film 7, coming into contact with the upside of the lower electrode 12.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a dielectric element having a dielectric film.

[0002]

2. Description of the Related Art A memory provided with a capacitor made of a ferroelectric film (hereinafter referred to as a ferroelectric capacitor) at a gate portion of a field effect transistor (FET) is known as a non-destructive readable nonvolatile memory. Have been. The structure of such a ferroelectric memory includes an MFS (metal / ferroelectric / semiconductor) structure, an MFIS (metal / ferroelectric / insulator / semiconductor) structure, and an MFMIS (metal / ferroelectric / metal / insulator) structure. Body / semiconductor) structure and the like have been proposed.

FIG. 12 is a schematic sectional view showing an example of a ferroelectric memory having an MFMIS structure. The ferroelectric memory of FIG. 12 is disclosed, for example, in Japanese Patent Application Laid-Open No. Hei 5-327062.

In FIG. 12, a source region 3 made of ap ⁺ layer is formed on a surface of an n ⁺ silicon substrate 31 at a predetermined interval.
4 and a drain region 35 composed of ap ⁺ layer is formed. A region of the silicon substrate 31 between the source region 34 and the drain region 35 becomes a channel region 36. A gate insulating film 32 is formed on the channel region 36, and a gate electrode 33 is formed on the gate insulating film 32.

On silicon substrate 31 and gate electrode 33
An interlayer insulating film 37 is formed thereon. Gate electrode 3
A contact hole 39 is formed in the interlayer insulating film 37 on the third layer 3, and a wiring layer 40 is formed in the contact hole 39.

On the source region 34 and the drain region 35
Contact holes are respectively provided in the upper interlayer insulating film 37, and the wiring layers 45 and 4 are respectively provided in the contact holes.
6 are formed. Further, a lower electrode 42 is formed on the wiring layer 40 connected to the gate electrode 33. A ferroelectric film 43 is formed on the lower electrode 42, and an upper electrode 44 is formed on the ferroelectric film 43. The wiring layer 4 connected to the source region 34 and the drain region 35
Ohmic electrodes 47 and 48 are formed on 5 and 46, respectively.

In this ferroelectric memory, the lower electrode 42, the ferroelectric film 43 and the upper electrode 44 constitute a ferroelectric capacitor.

[0008]

In the ferroelectric memory shown in FIG. 12, a lower electrode 42 and an upper electrode 44 are usually used.
Is formed of a metal having low reactivity such as Pt (platinum). As described above, the ferroelectric film 43 is formed on the lower electrode 42 made of a low-reactivity metal and the gate electrode 33 is formed.
Since the interlayer insulating film 37 is provided around the wiring layer 40 between the ferroelectric film 43 and the lower electrode 42, the reaction and mutual diffusion of constituent atoms between the ferroelectric film 43 and the silicon substrate 31 are sufficiently prevented. Have been.

However, in the above-described conventional ferroelectric memory, if the heat treatment is performed in a step after the formation of the ferroelectric capacitor, the lower electrode 42 and the upper electrode 44 are not heated.
A grain boundary composed of rod-like crystals is formed on Pt, which is a material of
Oxygen in the ferroelectric film 43 is easily diffused in Pt.
Thereby, an oxide layer is formed near the interface of the wiring layer 40 in contact with the ferroelectric film 43, and the resistance of the wiring layer 40 increases.

In addition, when the ferroelectric capacitor is placed in an atmosphere containing hydrogen during the formation of the insulating film in a later step, P
The desorption of oxygen from the ferroelectric film 43 is promoted by the catalytic action of t. Thus, a deteriorated layer is formed near the interface of the ferroelectric film 43 in contact with the upper electrode 44. As a result, the polarization characteristics of the ferroelectric film 43 deteriorate.

Further, Pt, which is a material of the lower electrode 42 and the upper electrode 44, has low reactivity and has difficult-to-etch characteristics, so that it takes a long time to process and the productivity is low. Further, Pt is expensive, resulting in high material costs and high manufacturing costs.

An object of the present invention is to have good polarization characteristics,
An object of the present invention is to provide a dielectric element capable of improving productivity and reducing cost.

[0013]

Means for Solving the Problems and Effects of the Invention

(1) First invention A dielectric element according to a first invention has a laminated structure of a first electrode layer and a dielectric film having crystal structures similar to each other.

In the dielectric element according to the present invention, the first
The electrode layers and the dielectric films have similar crystal structures.
Thereby, the lattice matching between the first electrode layer and the dielectric film is improved, so that the crystallinity of the dielectric film formed on the first electrode layer is improved, and The interface stability with the dielectric film is improved. Therefore, a dielectric element having good element characteristics is realized.

(2) Second Invention The dielectric element according to the second invention is the same as the dielectric element according to the first invention, except that the laminated structure is similar to the first electrode layer and the dielectric film. It has a second electrode layer having a crystal structure.

In the dielectric element according to the present invention, the first
The electrode layer, the dielectric film, and the second electrode layer have similar crystal structures. Thereby, the lattice matching between the first electrode layer and the dielectric film and the lattice matching between the dielectric film and the second electrode layer are improved, so that the dielectric material formed on the first electrode layer is improved. The crystallinity of the film is improved, and the interface stability between the first electrode layer and the dielectric film and the interface stability between the dielectric film and the second electrode layer are improved. Therefore, a dielectric element having good element characteristics is realized.

(3) Third invention A dielectric element according to a third invention is characterized in that, in the structure of the dielectric element according to the first or second invention, the electrode layer is made of a conductive oxide. I do.

In this case, the problem of desorption of constituent elements (for example, oxygen) of the dielectric film due to the catalytic action of the electrode layer does not occur.
Thereby, good polarization characteristics can be obtained in the dielectric film. Therefore, a dielectric device having better device characteristics is realized.

(4) Fourth Invention A dielectric element according to a fourth aspect of the present invention is the dielectric element according to any one of the first to third aspects, wherein the crystal structure of the electrode layer and the dielectric film is different. It has a perovskite structure.

In this case, both the electrode layer and the dielectric film have a perovskite structure, and have similar crystal structures. As a result, the lattice matching between the electrode layer and the dielectric film is improved, so that the crystallinity of the dielectric film formed on the electrode layer is improved, and the interface stability between the electrode layer and the dielectric film is improved. improves.

Further, the electrode layer having the perovskite structure is easy to process, and can be formed by a continuous process in the same manufacturing apparatus as the dielectric film having the perovskite structure. Further, the electrode layer having a perovskite structure can be formed at lower cost than a platinum group metal.

Therefore, a dielectric device having good device characteristics and capable of improving productivity and reducing costs is realized.

(5) Fifth Invention A dielectric element according to a fifth invention is characterized in that first and second impurity regions formed on a semiconductor substrate or a semiconductor layer at predetermined intervals, and the first and second impurity regions are formed. A gate insulating film formed on the region between the impurity regions, a gate electrode formed on the gate insulating film, and a contact hole formed on the semiconductor substrate or the semiconductor layer so as to cover the gate electrode and the gate insulating film. A lower electrode layer formed in a contact hole of the interlayer insulating film and electrically connected to the gate electrode, and formed on the interlayer insulating film so as to contact an upper surface of the lower electrode layer. A dielectric film, and an upper electrode layer formed on the dielectric film, wherein the lower electrode layer and the upper electrode layer are made of a conductive oxide having a perovskite structure, and the dielectric film is formed of a conductive oxide having a perovskite structure. It is made of an electric body.

In the dielectric element according to the present invention, the lower electrode layer, the upper electrode layer, and the dielectric film have a perovskite structure, and have similar crystal structures. Thereby, the lattice matching between the lower electrode layer and the dielectric film and the lattice matching between the dielectric film and the upper electrode layer are improved, so that the crystallinity of the dielectric film formed on the lower electrode layer is improved. And the interface stability between the lower electrode layer and the dielectric film and the interface stability between the dielectric film and the upper electrode layer are improved. Also,
There is no problem of desorption of constituent elements (for example, oxygen) of the dielectric film due to the catalytic action of the lower electrode layer and the upper electrode layer. Therefore, good polarization characteristics can be obtained in the dielectric film.

The conductive oxide having a perovskite structure can be easily processed, and can be formed by a continuous process in the same manufacturing apparatus as the dielectric film having a perovskite structure. Further, a conductive oxide having a perovskite structure can be formed at lower cost than a platinum group metal.

In particular, since the lower electrode layer in contact with the lower surface of the dielectric film is provided in the contact hole of the interlayer insulating film, when the upper electrode layer and the dielectric film are patterned, the material of the lower electrode layer is dielectric. Does not adhere or accumulate on sidewalls of body membrane. Even if the material of the upper electrode layer adheres to or deposits on the side wall of the dielectric film, the lower electrode layer is provided in the contact hole of the interlayer insulating film, so that a gap between the upper electrode layer and the lower electrode layer is formed. Current does not leak. Therefore, a decrease in reliability and yield due to adhesion or deposition of the conductive material on the side wall of the dielectric film is prevented.

Therefore, a dielectric memory having good element characteristics and capable of improving productivity and reducing costs is realized.

(6) Sixth Invention A dielectric element according to a sixth aspect of the present invention is the dielectric element according to the fifth aspect, wherein the dielectric element is formed below the lower electrode layer in the contact hole. The semiconductor device further includes a connection layer electrically connected to the gate electrode.

In this case, a connection layer and a lower electrode layer are provided in the contact hole of the interlayer insulating film, and the lower electrode layer in the contact hole is electrically connected to the gate electrode by the connection layer.

(7) Seventh invention A dielectric element according to a seventh invention is the dielectric element according to any one of the first to sixth inventions, wherein the electrode layer is made of a layered conductive oxide. And the dielectric film is made of a layered dielectric.

In this case, since both the electrode layer and the dielectric film have a layered structure, the lattice matching between the electrode layer and the dielectric film is further improved. Thereby, the crystallinity of the dielectric film formed on the electrode layer is further improved, and the interface stability between the electrode layer and the dielectric film is further improved. Therefore, better polarization characteristics can be obtained in the dielectric film.

(8) Eighth Invention The dielectric element according to the eighth invention is the dielectric element according to any one of the first to seventh inventions, wherein the electrode layer is a bismuth-based layered conductive oxide. Wherein the dielectric film is made of a layered dielectric containing bismuth.

In this case, since both the electrode layer and the dielectric film have a layered structure and contain bismuth, the electrode layer and the dielectric film have similar crystal structures and similar constituent elements. Therefore, the lattice matching between the electrode layer and the dielectric film is further improved, and a deterioration layer is not formed between the electrode layer and the dielectric film due to mutual diffusion of constituent elements.
Thereby, the crystallinity of the dielectric film formed on the electrode layer is further improved, and the interface stability between the electrode layer and the dielectric film is further improved. Therefore, better polarization characteristics can be obtained in the dielectric film.

(9) Ninth Invention A dielectric element according to a ninth invention is the dielectric element according to any one of the first to eighth inventions, wherein the dielectric film is made of a ferroelectric material. It is characterized by. In this case, a ferroelectric element having good element characteristics and capable of improving productivity and reducing cost is realized.

(10) Tenth invention A dielectric element according to a tenth aspect of the present invention is the dielectric element according to any one of the first to ninth aspects, wherein the electrode layer is made of bismuth, strontium, copper and oxygen. , And the dielectric film is made of a layered ferroelectric containing strontium, bismuth, tantalum, and oxygen.

In this case, since both the electrode layer and the dielectric film have a layered structure and contain bismuth, strontium and oxygen, the electrode layer and the dielectric film have similar crystal structures and similar constituent elements. . Therefore, the lattice matching between the electrode layer and the dielectric film is further improved, and a deteriorated layer is not formed between the electrode layer and the dielectric film due to mutual diffusion of constituent elements. Thereby, the crystallinity of the dielectric film formed on the electrode layer is further improved, and the interface stability between the electrode layer and the dielectric film is further improved. Therefore, a ferroelectric element having better element characteristics and capable of improving productivity and reducing cost is realized.

[0037]

BEST MODE FOR CARRYING OUT THE INVENTION

(1) First Embodiment FIG. 1 is a schematic sectional view showing the structure of a ferroelectric memory according to a first embodiment of the present invention.

In FIG. 1, a p-type single crystal silicon substrate 1
Source region 4 composed of an n ⁺ layer at a predetermined interval on the surface of
And a drain region 5 composed of an n ⁺ layer. A region of the silicon substrate 1 between the source region 4 and the drain region 5 becomes a channel region 6.

The gate insulating film 2 made of SiO ₂ on the channel region 6 is formed. On the gate insulating film 2,
A gate electrode 3 made of polysilicon is formed.
Interlayer insulating film 7 is formed on silicon substrate 1 so as to cover gate electrode 3 and gate insulating film 2. On the interlayer insulating film 7, a buffer layer 8 made of TiO ₂ (titanium oxide), CeO ₂ (cerium oxide) or the like is formed.

A contact hole 9 is formed in the interlayer insulating film 7 and the buffer layer 8 on the gate electrode 3. In the contact hole 9, a connection layer (plug) 10 made of a conductive material such as polysilicon or W (tungsten) is formed to a predetermined depth.

On the connection layer 10 in the contact hole 9, T
A diffusion barrier layer 11 made of a conductive material such as iN or TaSiN is formed, and a Pt layer 12a is formed on the diffusion barrier layer 11.

On the Pt layer 12a in the contact hole 9,
Bi ₂ Sr ₂ C, a Bi (bismuth) -based conductive oxide
A lower electrode 12 made of uO ₆ (BSCO) is formed. A ferroelectric film 13 made of SrBi ₂ Ta ₂ O ₉ (SBT), which is a layered ferroelectric having a perovskite crystal structure, is formed on the buffer layer 8 so as to be in contact with the upper surface of the lower electrode 12. On the ferroelectric film 13,
An upper electrode 14 made of Bi ₂ Sr ₂ CuO ₆ which is a Bi-based conductive oxide is formed.

Contact holes are formed in the buffer layer 8 and the interlayer insulating film 7 on the source region 4 and the drain region 5, respectively. The source electrode 15 and the drain electrode made of a conductive material such as polysilicon are formed in the contact holes. 16 are formed respectively. Wiring layers 17 and 18 are formed on the source electrode 15 and the drain electrode 16, respectively.

In the ferroelectric memory shown in FIG.
2. The ferroelectric film 13 and the upper electrode 14 constitute a ferroelectric capacitor.

In this embodiment, the lower electrode 12 corresponds to a lower electrode layer or a first conductive layer, and the upper electrode 14 corresponds to an upper electrode layer or a second conductive layer.

FIG. 2 shows the lower electrode 1 of the ferroelectric memory shown in FIG.
2 and Bi ₂ Sr ₂ CuO as a material of the upper electrode 14
FIG. ₆ is a schematic view showing a crystal structure of No. ₆ . FIG. 3 shows SrBi which is a material of the ferroelectric film 13 of the ferroelectric memory of FIG.
It is a schematic view showing the crystal structure of ₂ Ta ₂ O _9.

As shown in FIG._TwoSr_TwoCuO₆
Is a layered conductive oxide having a perovskite crystal structure
Things. This Bi_TwoSr_TwoCuO₆Is about 600 ° C
It can be formed at low temperature, shows superconductivity at low temperature, and
Resistance is 10^-FourIt is about Ωcm. On the other hand, as shown in FIG.
And SrBi_TwoTa_TwoO₉Is a perovskite crystal structure
Is a layered ferroelectric material having Bi_TwoSr_TwoCuO₆You
And SrBi_TwoTa_TwoO₉The in-plane lattice constants of both are 0.3
9 nm. Thus, Bi of FIG._TwoSr _TwoCuO
₆And SrBi of FIG._TwoTa_TwoO₉Is similar in crystal structure
Has the property.

Therefore, the lower electrode 12 and the ferroelectric film 1
3 and the ferroelectric film 13 and the upper electrode 14
And the lattice matching with is improved. Further, the crystallinity of the ferroelectric film 13 formed on the lower electrode 12 is improved.

As shown in FIG. 2, Bi ₂ Sr ₂ C
The constituent elements of uO ₆ are Sr, Bi, Cu and O.
On the other hand, as shown in FIG. 3, the constituent elements of SrBi ₂ Ta ₂ O ₉ are Sr, Bi, Ta and O. in this way,
Bi ₂ Sr ₂ CuO ₆ of FIG. ₂ and SrBi ₂ T of FIG.
a ₂ O ₉ has similarity of constituent elements.

Therefore, the lower electrode 12 and the ferroelectric film 1
3 and near the interface between the ferroelectric film 13 and the upper electrode 14 are less affected by mutual diffusion of constituent elements. That is, C in the lower electrode 12 and the upper electrode 14
When u and Ta in the ferroelectric film 13 interdiffuse, SrBi ₂ Ta ₂ O _9, which is the material of the ferroelectric film 13, is partially formed near the interface between the lower electrode 12 and the upper electrode 14. In the vicinity of the interface in the ferroelectric film 13, Bi ₂ Sr ₂ C which is a material of the lower electrode 12 and the upper electrode 14 is partially formed.
uO ₆ is formed. In this case, the interface between the lower electrode 12 and the ferroelectric film 13 and the ferroelectric film 13 and the upper electrode 14
Interface is slightly disturbed, and no deteriorated layer is formed at these interfaces.

Further, since the ferroelectric capacitor composed of the lower electrode 12, the ferroelectric film 13 and the upper electrode 14 has an all-oxide type laminated structure, the interface stability is improved.
The problem of oxygen desorption due to the catalytic action of Pt is avoided.
Further, even if the ferroelectric film 13 deteriorates such as oxygen deficiency, the properties of the lower electrode 12, the ferroelectric film 13 and the upper electrode 14 can be recovered by performing a heat treatment for supplementing oxygen. . As a result, a ferroelectric capacitor having excellent polarization fatigue characteristics is formed.

Further, since the lower electrode 12, the ferroelectric film 13 and the upper electrode 14 can be formed by a continuous process in the same manufacturing apparatus, the productivity is improved. Further, for example, when the lower electrode 12 and the upper electrode 14 are formed using a 6-inch sputter target made of Bi ₂ Sr ₂ CuO ₆ , compared with the case where they are formed using a 6-inch sputter target made of Pt, Material costs are reduced by a factor of ten. As a result, the cost of the ferroelectric memory is reduced.

Further, the lower electrode 12 and the upper electrode 14
Bi ₂ Sr ₂ CuO _6, which is a material having high reactivity, has good workability and can be easily etched by chemical etching. Further, by introducing Cl ₂ or HBr into the etching reaction system, it is possible to perform etching utilizing reactivity. As a result, the etching rate can be increased. Further, the lower electrode 1
2. The ferroelectric film 13 and the upper electrode 14 can be simultaneously etched. As a result, productivity is improved.

4 to 8 are process sectional views showing a method for manufacturing the ferroelectric memory of FIG. First, as shown in FIG. 4A, a gate insulating film 2 made of SiO _{2 having a} thickness of 100 ° is formed on a p-type silicon substrate 1 by a thermal oxidation method.
A gate electrode 3 made of polysilicon having a thickness of 2000 .ANG. On the gate insulating film 2 by CVD (chemical vapor deposition).
To form

Next, as shown in FIG. 4B, the gate electrode 3 and the gate insulating film 2 except for the gate forming region on the silicon substrate 1 are formed by using a dry process such as reactive ion etching or ion milling. Is removed to form a gate portion. Then, using the gate electrode 3 as a mask for ion implantation, an n-type impurity (n-type dopant) is ion-implanted into the surface of the silicon substrate 1 and heat treatment is performed. Thereby, n-type impurity layer (n ⁺ layer) is self-aligned with gate insulating film 2 and gate electrode 3 on silicon substrate 1.
A source region 4 and a drain region 5 are formed. The region of the silicon substrate 1 between the source region 4 and the drain region 5 becomes a channel region 6.

Thereafter, as shown in FIG. 4C, a SiO 2 film having a thickness of about 6000 ° is formed on the silicon substrate 1 so as to cover the gate electrode 3 and the gate insulating film 2 by a CVD method or the like.
_An interlayer insulating film 7 made of ₂ or the like is formed.

Next, as shown in FIG. 5D, a film 500 of TiO ₂ , CeO ₂ or the like is formed on the interlayer insulating film 7.
The buffer layer 8 of Å is formed. Thereafter, as shown in FIG. 5E, a contact hole 9 is provided in the buffer layer 8 and the interlayer insulating film 7 on the gate electrode 3 by a lithography technique.

Then, as shown in FIG. 5F, a connection layer 10 made of a conductive material such as polysilicon or W is formed in the contact hole 9. In this case, the thickness of connection layer 10 is set such that the distance from the upper end of contact hole 9 to the upper surface of connection layer 10 is 1500 °. As a method for forming the connection layer 10, a conductive layer is formed inside the contact hole 9 and the entire surface of the buffer layer 8, and then the conductive layer on the buffer layer 8 is removed by etching the entire surface.

Next, as shown in FIG. 6G, the connection layer 10 is formed inside the contact hole 9 and over the entire surface of the buffer layer 8.
A diffusion barrier layer 11 made of a conductive material such as TiN or TaSiN is formed by a sputtering method or the like in order to prevent oxidation of the semiconductor and diffusion of impurities into the gate portion.

As shown in FIG. 6H, the diffusion barrier layer 11 on the buffer layer 8 is removed by etching the entire surface of the diffusion barrier layer 11, and the diffusion barrier layer 11 in the contact hole 9 is removed. The upper surface of the buffer layer 8
The buffer layer 11 is etched back until the buffer layer 11 becomes lower than the upper surface. In this case, a mixed gas of BCl ₃ and Cl ₂ is used as an etching gas, and the etching conditions are as follows.
High frequency output is 250W and pressure is 2 × 10 ^-2 Torr
And Note that another gas such as Ar or N ₂ may be mixed with the above mixed gas. Thus, the contact hole 9
A diffusion barrier layer 11 having a thickness of 300 ° is formed on the connection layer 10 in the inside.

Next, as shown in FIG. 6 (i), the crystallinity of Bi ₂ Sr ₂ CuO ₆ formed on the buffer layer 8 and the diffusion barrier layer 11 in the contact hole 9 is improved. For this purpose, a Pt film 12a is formed.

Thereafter, as shown in FIG. 7 (j), the Pt layer 12a on the buffer layer 8 is removed by etching the entire surface of the Pt layer 12a, and the upper surface of the Pt layer 12a in the contact hole 9 is removed. The Pt layer 12a is etched back until it becomes lower than the upper surface of the buffer layer 8. In this case, Ar was used as an etching gas, the high frequency output was set to 300 W, and the pressure was set to 3 × 1.
0 ^-3 Torr. The etching is Cl ₂ , H
Other gases such as Br and BCl ₃ may be used, or a mixed gas thereof may be used. Thus, the Pt layer 1 having a thickness of 200 ° is formed on the diffusion barrier layer 11 in the contact hole 9.
2a is formed.

Next, as shown in FIG. 7K, on the buffer layer 8 and the Pt layer 12a in the contact hole 9,
The lower electrode 12 made of Bi ₂ Sr ₂ CuO ₆ is formed by a sputtering method or the like.

Thereafter, as shown in FIG. 7 (l), the lower electrode 12 is flattened by etch back or CMP (chemical mechanical polishing) to leave the lower electrode 12 only in the contact hole 9. Film thickness 1 in the contact hole 9
A lower electrode 12 of 000 ° is formed. In this case, Ar, HBr, or the like is used as an etching gas, and the etching conditions are a high frequency output of 200 to 400 W and a pressure of about 1 × 10 ⁻³ Torr.

Note that, instead of etching back the diffusion barrier layer 11 and the Pt layer 12a in the steps of FIGS. 6H and 7J, respectively, the diffusion barrier layer 11 and the Pt layer 12 are not etched back.
After the formation of the lower electrode 12 and the lower electrode 12, the lower electrode 12, the Pt layer 12a, and the diffusion barrier layer 11 may be simultaneously etched back or planarized by the CMP method.

Next, as shown in FIG. 8 (m), a ferroelectric film 13 of SrBi ₂ Ta ₂ O ₉ having a thickness of 2000 ° is formed on the lower electrode 12 and the buffer layer 8 by a sputtering method or the like. . Further, as shown in FIG. 8 (n), an upper electrode 14 made of Bi ₂ Sr ₂ CuO _{6 having a} thickness of 1500 ° is formed on the ferroelectric film 13 by a sputtering method or the like.

Thereafter, as shown in FIG. 8 (o), the upper electrode 14 and the ferroelectric film 13 are patterned by etching. In this case, Ar, H is used as an etching gas.
Using Br or the like, the etching conditions are high-frequency output 2
The pressure is set to about 1 × 10 ⁻³ Torr.

At the time of etching, the entire buffer layer 8 may be etched. The ferroelectric film 13 is a lower electrode 12
And it does not necessarily have to straddle on the buffer layer 8.

Next, as shown in FIG.
A contact hole is provided in each of the buffer layer 8 and the interlayer insulating film 7 on the drain electrode 5 and a source electrode 15 and a drain electrode 16 made of a conductive material such as polysilicon are formed in the contact holes. Finally, Al is formed on the source electrode 15 and the drain electrode 16.
Are formed. Thus, the ferroelectric memory of FIG. 1 is manufactured.

In the ferroelectric memory of this embodiment, since the lower electrode 12 is provided in the contact hole 9 of the interlayer insulating film 7, the lower electrode 12 is patterned when the upper electrode 14 and the ferroelectric film 13 are patterned by etching. The 12 conductive materials do not deposit on the side walls of the ferroelectric film 13. Therefore, the reliability and the yield of the ferroelectric memory due to the deposition of the conductive material on the side wall of the ferroelectric film 13 are sufficiently prevented from being lowered.

In the step of FIG. 8 (m), the ferroelectric film 1
Since 3 is formed on interlayer insulating film 7 with buffer layer 8 interposed therebetween, stress of ferroelectric film 13 is alleviated by buffer layer 8, and cracks in ferroelectric film 13 are prevented from occurring. At the same time, reaction of constituent elements and mutual diffusion between the ferroelectric film 13 and the interlayer insulating film 7 are prevented. As a result, the reliability and yield of the ferroelectric memory are further improved.

Further, the ferroelectric film 13 and the silicon substrate 1
Since the interlayer insulating film 7 is provided around the conductive layer 10 between them, the reaction and mutual diffusion of the constituent elements between the ferroelectric film 13 and the silicon substrate 1 are sufficiently prevented.

Here, the operation principle of the ferroelectric memory of FIG. 1 will be described. A positive voltage sufficient to invert the polarization of the ferroelectric film 13 is applied to the upper electrode 14, and the upper electrode 14
Is set to 0. Thus, the interface of the ferroelectric film 13 with the upper electrode 14 is negatively charged, and the interface with the lower electrode 12 is positively charged.

In this case, the ferroelectric film 13 of the lower electrode 12
Is negatively charged, and the gate insulating film 2 of the gate electrode 3
Interface is positively charged. As a result, an inversion layer is formed in the channel region 6 between the source region 4 and the drain region 5, and the FET is turned on even though the voltage of the upper electrode 14 is zero.

Conversely, a negative voltage sufficient to invert the polarization of the ferroelectric film 13 is applied to the upper electrode 14, and the voltage of the upper electrode 14 is set to 0 again. Thereby, the ferroelectric film 13
The interface with the upper electrode 14 is positively charged, and the interface with the lower electrode 12 is negatively charged.

In this case, the ferroelectric film 13 of the lower electrode 12
Is positively charged, and the gate insulating film 2 of the gate electrode 3
Interface is negatively charged. As a result, no inversion layer is formed in the channel region 6 between the source region 4 and the drain region 5, and the FET is turned off.

As described above, if the ferroelectric film 13 is sufficiently polarized, the FET can be selectively turned on or off even after the voltage applied to the upper electrode 14 is set to zero. it can. Therefore, it is possible to determine the data “1” and “0” stored in the ferroelectric memory by detecting the current between the source and the drain.

(2) Second Embodiment FIG. 9 is a schematic sectional view showing a structure of a ferroelectric memory having an MFMIS structure according to a second embodiment of the present invention.

Referring to FIG. 9, a source region 22 composed of an n ⁺ layer is formed on a surface of a p-type silicon substrate 21 at a predetermined interval.
And a drain region 23 formed of an n ⁺ layer. The region of the silicon substrate 21 between the source region 22 and the drain region 23 becomes the channel region 24. On the channel region 24, a gate insulating film 25, a lower electrode 26, a ferroelectric film 27, and an upper electrode 28 are sequentially formed.

In the ferroelectric memory of FIG. 9, the lower electrode 26, the ferroelectric film 27 and the upper electrode 28 constitute a ferroelectric capacitor. Lower electrode 26 and upper electrode 2
8 is made of Bi ₂ Sr ₂ CuO ₆ , and the ferroelectric film 27 is made of SrBi ₂ Ta ₂ O ₉ .

The ferroelectric memory according to the present embodiment also has excellent polarization degradation resistance, as in the ferroelectric memory according to the first embodiment, so that it is possible to improve the productivity and reduce the cost. .

(3) Third Embodiment FIG. 10 is a schematic sectional view showing the structure of a ferroelectric memory having an MFIS structure according to a third embodiment of the present invention.

Referring to FIG. 10, a source region 2 made of an n ⁺ layer is formed on the surface of p-type silicon substrate 21 at a predetermined interval.
A drain region 23 composed of 2 and n ⁺ layers is formed. The region of the silicon substrate 21 between the source region 22 and the drain region 23 becomes the channel region 24. On the channel region 24, a gate insulating film 25, a ferroelectric film 27
And a gate electrode 28a are sequentially formed.

In the ferroelectric memory of FIG. 10, the channel region 24 of the p-type silicon substrate 21 and the gate insulating film 2
5. The ferroelectric film 27 and the gate electrode 28a constitute a ferroelectric capacitor. The ferroelectric film 27 is made of SrBi ₂ T
a ₂ O ₉ , and the gate electrode 28a is made of Bi ₂ Sr ₂ C
It consists of uO ₆ .

In the ferroelectric memory of this embodiment, like the ferroelectric memory of the first embodiment, it has excellent resistance to polarization degradation, and it is possible to improve the productivity and reduce the cost. .

(4) Fourth Embodiment FIG. 11 is a schematic sectional view showing a structure of a ferroelectric memory having an MFS structure according to a fourth embodiment of the present invention.

In FIG. 11, a source region 2 made of an n ⁺ layer is formed on the surface of p-type silicon substrate 21 at a predetermined interval.
A drain region 23 composed of 2 and n ⁺ layers is formed. The region of the silicon substrate 21 between the source region 22 and the drain region 23 becomes the channel region 24. On the channel region 24, the ferroelectric film 27 and the gate electrode 2
8a are sequentially formed.

In the ferroelectric memory of FIG. 11, the channel region 24 of the p-type silicon substrate 21 and the ferroelectric film 27
And gate electrode 28a constitute a ferroelectric capacitor. The ferroelectric film 27 is made of SrBi ₂ Ta ₂ O ₉ ,
The gate electrode 28a is made of Bi ₂ Sr ₂ CuO ₆ .

The ferroelectric memory according to the present embodiment also has excellent polarization degradation resistance, as in the ferroelectric memory according to the first embodiment, so that it is possible to improve productivity and reduce costs. .

(5) Other Application Examples The present invention can be applied to a ferroelectric memory having the structure shown in FIG. In this case, the lower electrode 42 and the upper electrode 44 are formed of Bi ₂ Sr ₂ CuO ₆ , and the ferroelectric film 43 is formed of SrBi ₂ Ta ₂ O ₉ .

(6) Other electrode materials Lower electrodes 12, 26, 42 and upper electrodes 14, 28, 44
As a material of the gate electrode 28a, a conductive oxide made of the following materials can be used.

Perovskite type material: A ₂ B ₂ C _n M _{n + 1} O _{2n + 6} n = 0,1,2,3,4,5 A is Tl (thallium), Bi, Mg or Cu, B is Ba, C is C
a and M are Cu.

(Sr, La) MO _3. (Sr, La) ₂ MO ₄ M is Ti, V, Cr, Mn, Fe, Co, Ni, Cu,
Ru or Ir.

• CaMO ₃ M is V, Cr, Fe or Ru.

[0095] _{· LuNiO 3 · Ba (Pb,} Bi) is _{O 3 · LnBa 2 Cu n O} n + 4-a n = 3,4. Ln is Y, La, Pr, Nd, S
m, Eu, Gd, Td, Dy, Ho, Er, Tm, Yb
Or Lu.

(Ba, A) BiO ₃ A is K or Rb.

[0097] _{· Sr 1 + n Cu n O} 2n + 1 n = 1,2,3, it is ∞.

[0098] It is preferable to use the above perovskite-type materials, in particular, it is more preferable to use a perovskite material represented by _{A 2 B 2 C n M n} + 1 O 2n + 6.

Further, as the material of the lower electrodes 12, 26, 42, the upper electrodes 14, 28, 44 and the gate electrode 28a, conductive oxides of the following materials can be used.

ReO ₃ type material • ReO ₃ M _x WO ₃ type material M is H, alkali metal, alkaline earth metal, Cu, A
g, In, Tl, Sn or Pb.

Lower electrode 12, 26, 42, upper electrode 1
4, 28, 44 and the gate electrode 28a may have a multilayer structure of each of the above materials.

(7) Other Ferroelectric Materials As the ferroelectric films 13, 27 and 43, ferroelectrics made of the following materials may be used.

Bismuth-based layered ferroelectric substance (Bi ₂ O ₂ ) ²⁺ (A _n-1 B _n O _{3n + 1} ) ^{2- represented by} the following general formula, where A is Sr, Ca, Ba, Pb, Bi, K or N
a and B is Ti, Ta, Nb, W or V.

When n = 1: Bi ₂ WO ₆ Bi ₂ VO _{5.5 When} n = 2: Bi ₂ O ₃ / SrTa ₂ O ₆ (SrBi ₂ Ta ₂ O ₉ ): SBT Bi ₂ O ₃ / SrNb ₂ O ₆ (SrBi ₂ Nb ₂ O ₉ ) When n = 3: Bi ₂ O ₃ / SrTa ₂ O ₆ / BaTiO ₃ .Bi ₂ O ₃ / SrTaO ₆ / SrTiO ₃ .Bi ₂ O ₃ / Bi ₂ Ti ₃ O ₉ (Bi ₄ Ti ₃ O ₁₂ ): When BIT n = 4: Bi ₂ O ₃ / Sr ₃ Ti ₄ O ₁₂ (Sr ₃ Bi ₂ Ti ₄ O ₁₅ ) Bi ₂ O ₃ / Bi ₂ Ti ₃ O ₉ / SrTiO ₃ (SrBi ₄ Ti ₄ O ₁₅ ) As the material of the ferroelectric films 13, 27 and 43, it is preferable to use the above-mentioned bismuth-based layered ferroelectrics. Another ferroelectric material can be used.

Ferroelectric substance (isotropic material system) represented by the following general formula: Pb (Zr _x Ti _1-x ) O ₃ : PZT (PbZr _{0.5
Ti 0.5) O 3 · (Pb} 1-Y La Y) (Zr X Ti 1-X) O 3: PLZ
_{T · (Sr 1-X Ca} X) TiO 3 · (Sr 1-X Ba X) TiO 3: (Sr 0.4 Ba 0.6)
_{TiO 3 · (Sr 1-XY} Ba X M Y) Ti 1-Z N Z O 3 should be noted, M is La, Bi, Sb or Y, N is N
b, V, Ta, Mo or W.

Sr ₂ Nb ₂ O ₇ .Sr ₂ Ta ₂ O ₇ .Pb ₅ Ge ₃ O _11. (Pb, Ca) TiO ₃ (8) Method of forming ferroelectric film Ferroelectric films 13, 27, As a method for forming 43, a molecular beam epitaxy method (MBE method), a laser ablation method, a laser molecular beam epitaxy method, a sputtering method (RF type, DC type or ion beam type), a reactive evaporation method, an MOCVD method (organic metal Chemical vapor deposition method), mist deposition method, sol-gel method and the like can be used.

(9) Other Modifications The materials of the gate electrode 3 and the connection layer 10 are not limited to polysilicon and W, and other conductive materials may be used.

Further, in the above embodiment, the FET is formed on the silicon substrates 1 and 21, but the FET may be formed on another semiconductor substrate or semiconductor layer.

In the above embodiment, a ferroelectric memory having an n-type channel has been described. However, a ferroelectric memory having a p-type channel can be realized by reversing the conductivity type of each layer.

Further, the present invention is not limited to the ferroelectric memory of the above embodiment, but can be applied to various ferroelectric memories having a ferroelectric capacitor.

In the above embodiment, the case where the present invention is applied to a ferroelectric capacitor of a ferroelectric memory operating as a non-volatile memory has been described. The present invention is also applicable to a ferroelectric capacitor of a memory.

Furthermore, the present invention can be applied to the formation of a dielectric capacitor having a structure in which a dielectric film is sandwiched between conductive layers, or another dielectric element having a laminated structure of a dielectric film and a conductive layer. It is.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing a structure of a ferroelectric memory according to a first embodiment of the present invention.

2 is a schematic diagram showing a crystal structure of Bi ₂ Sr ₂ CuO ₆ which is a material of a lower electrode and an upper electrode of the ferroelectric memory of FIG.

3 is a schematic diagram showing a crystal structure of SrBi ₂ Ta ₂ O ₉ which is a material of a ferroelectric film of the ferroelectric memory of FIG.

FIG. 4 is a process sectional view illustrating the method of manufacturing the ferroelectric memory in FIG.

5 is a process sectional view illustrating the method of manufacturing the ferroelectric memory in FIG.

FIG. 6 is a process sectional view illustrating the method of manufacturing the ferroelectric memory in FIG.

7 is a process sectional view illustrating the method of manufacturing the ferroelectric memory in FIG.

8 is a process sectional view illustrating the method of manufacturing the ferroelectric memory in FIG.

FIG. 9 is a schematic sectional view showing the structure of a ferroelectric memory according to a second embodiment of the present invention.

FIG. 10 is a schematic sectional view showing the structure of a ferroelectric memory according to a third embodiment of the present invention.

FIG. 11 is a schematic sectional view showing the structure of a ferroelectric memory according to a fourth embodiment of the present invention.

FIG. 12 is a schematic sectional view showing an example of a conventional ferroelectric memory.

[Explanation of symbols]

 1,21 silicon substrate 2,25 gate insulating film 3,28a gate electrode 4,22 source region 5,23 drain region 6,24 channel region 7 interlayer insulating film 8 buffer layer 9 contact hole 10 connection layer 11 diffusion barrier layer 12, 26 lower electrode 13,27 ferroelectric film 14,28 upper electrode

──────────────────────────────────────────────────続 き Continued on front page (51) Int.Cl. ⁶ Identification code FI H01L 29/792

Claims (10)

[Claims] 1. A dielectric element having a stacked structure of a first electrode layer and a dielectric film having crystal structures similar to each other. 2. The dielectric device according to claim 1, wherein the laminated structure further includes a second electrode layer having a crystal structure similar to the first electrode layer and the dielectric film. 3. The dielectric element according to claim 1, wherein said electrode layer is made of a conductive oxide. 4. The crystal structure of the electrode layer and the dielectric film is a perovskite type structure.
4. The dielectric element according to any one of claims 1 to 3. 5. A semiconductor device according to claim 1, wherein said first and second impurity regions are formed on said semiconductor substrate or said semiconductor layer at a predetermined interval, and said gate insulating film is formed on said first and second impurity regions. A gate electrode formed on the gate insulating film; an interlayer insulating film having a contact hole formed on the semiconductor substrate or the semiconductor layer so as to cover the gate electrode and the gate insulating film; A lower electrode layer formed in the contact hole and electrically connected to the gate electrode; a dielectric film formed on the interlayer insulating film so as to contact an upper surface of the lower electrode; An upper electrode layer formed on a body film, wherein the lower electrode layer and the upper electrode layer are made of a conductive oxide having a perovskite structure, and the dielectric film is a perovskite type The dielectric element characterized by comprising a dielectric having a granulation. 6. The dielectric according to claim 5, further comprising a connection layer formed under the lower electrode layer in the contact hole and electrically connecting the lower electrode layer to the gate electrode. Body element. 7. The dielectric element according to claim 1, wherein said electrode layer is made of a layered conductive oxide, and said dielectric film is made of a layered dielectric. 8. The dielectric according to claim 1, wherein said electrode layer is made of a bismuth-based layered conductive oxide, and said dielectric film is made of a layered dielectric containing bismuth. element. 9. The dielectric device according to claim 1, wherein said dielectric film is made of a ferroelectric material. 10. The electrode layer is made of a layered conductive oxide containing bismuth, strontium, copper and oxygen, and the dielectric film is made of a layered ferroelectric containing strontium, bismuth, tantalum and oxygen. The dielectric element according to any one of claims 1 to 9, wherein