JP2005012052A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device that is high in performance and operation speed and can prevent an increase in chip area in a semiconductor system. <P>SOLUTION: The semiconductor device is provided with test means 13a-13d that are not used in a normal mode and are used in a test mode for easing testing of a device; a signal wiring 11 to be used as a signal line in a normal mode; test wirings 12a and 12b that are arranged adjacent to the signal wiring 11 with an insulation film in between and of which at least a part is formed nearly parallel to the signal wiring 11, and that are not used as a signal line in a normal mode; first switching devices 14a-14d that become conductive when the test wirings 12a and 12b are used as a signal line in a test mode; and second switching devices 16a and 16b that get into nonconductive state when the test wirings 12a and 12b are used as a signal line in a tets mode. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a test circuit. In particular, the present invention relates to a semiconductor device applied to an SOC (system on chip) in which a high-speed and multifunctional semiconductor system is mounted on one chip.
[0002]
[Prior art]
In a conventional semiconductor device having a complicated function, an operation test, a function test, and the like are performed as a development test in order to detect a circuit bug caused by a design error during development. Further, in order to guarantee the operation of the semiconductor device to the user, a reliability test and the like are performed as a pre-shipment test in addition to an operation test and a function test before shipping to the market.
[0003]
In particular, with the rapid miniaturization of semiconductor processes in recent years, SOC (system on chip) in which an entire system of several tens of mega-gates is mounted on one chip has appeared, and test technology has become increasingly important.
[0004]
For such a large-scale SOC, various test circuits are installed in the semiconductor device for the purpose of shortening the test time and improving the efficiency of the tester equipment, and the development test and shipment of a highly functional and highly reliable semiconductor device Pre-test is done efficiently.
[0005]
However, the scale of test circuits required with the increasing complexity and scale of the system has dramatically increased. Especially, the number of dedicated test wirings has increased remarkably, and it is not uncommon for the percentage of the total wiring to reach several percent. .
[0006]
For this reason, in order to reduce the number of test circuit wires, a method has been proposed in which test command data is parallel-serial converted and supplied to the test circuit as serial data (see Patent Document 1). However, this method can reduce the number of specific wirings that can be converted from parallel to serial, such as command data and addresses, but cannot reduce inter-circuit signal wirings that occupy most of the test dedicated wirings.
[0007]
By the way, due to the recent demand for higher system speed, the signal frequency propagating through the signal wiring in the semiconductor device often exceeds GHz in a high-speed signal line called a so-called critical path.
[0008]
On the other hand, with the miniaturization of the semiconductor process, the signal wiring width tends to narrow and the wiring interval tends to narrow. For this reason, it is necessary to take measures such as attaching shield wiring to necessary signal wiring in consideration of crosstalk between signal wirings when designing a semiconductor device.
[0009]
Such shield wiring, like the dedicated wiring of the test circuit described above, has a ratio of several percent to the entire wiring, and the increase in the chip area due to these has become non-negligible.
[0010]
[Patent Document 1]
Japanese Patent Laid-Open No. 2002-93197
[Problems to be solved by the invention]
As described above, the conventional semiconductor device has a chip area due to a dramatic increase in test circuits and shield wiring necessary for guaranteeing its operation and ensuring reliability as the system becomes more complex, larger, and faster. There was a problem that the increase cannot be ignored.
[0012]
The present invention has been made to solve the above-described problems, and provides a semiconductor device that suppresses an increase in chip area despite being a high-function, high-speed and high-reliability system. For the purpose.
[0013]
[Means for Solving the Problems]
In order to achieve the above object, a semiconductor device according to the present invention is arranged with at least one signal wiring used as a signal line and an insulating film in the vicinity of the signal wiring, at least a part of which is the signal wiring. First and second test wirings formed substantially in parallel with the first and second test wirings, connected to the first and second test wirings and set to a predetermined power supply potential, and the first and second wirings First and second test means connected to two test wirings, and a first connection for connecting the first and second test means and the first and second test wirings in a test mode And second connection means for connecting the signal wiring and the power supply wiring with the first connection means being non-conductive in the normal mode, the first and second test wirings being shield wirings, and Having And it features.
[0014]
According to the present invention, test wiring used for development testing and pre-shipment testing can be used as a shield wiring for signal wiring that becomes a critical path during normal operation, and is highly functional, high speed, and high reliability. In spite of the semiconductor system having the above, it is possible to realize a semiconductor device in which an increase in the chip area is suppressed.
[0015]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, embodiments of the present invention (hereinafter referred to as embodiments) will be described with reference to the drawings.
[0016]
(First embodiment)
FIG. 1 is an image diagram showing a wiring layout in the semiconductor device according to the first embodiment of the present invention. Here, the signal wiring 11 to be shielded, the test wirings 12a and 12b that also serve as the shield wiring, and the portion related to the control are shown.
[0017]
The semiconductor device according to the first embodiment of the present invention includes a signal wiring 11 to be shielded, test wirings 12a and 12b that use both a test signal line and a shield wiring, and test circuits 13a to 13d used in a test mode. The switch elements 14a to 14d connecting the test wirings 12a and 12b and the test circuits 13a to 13d, the power supply wirings 15a and 15b for supplying the reference potential (Vss), and the test wirings 12a and 12b and the power supply wirings 15a and 15b. It has switch elements 16a and 16b to be connected.
[0018]
The signal wiring 11 and the test wirings 12a and 12b are arranged adjacent to each other via an insulating film, and the test wirings 12a and 12b are arranged almost in parallel on both sides of the signal wiring 11 therebetween.
[0019]
The switch elements 14a to 14d and the switch elements 16a and 16b are configured by, for example, n-type MOS-FETs (hereinafter referred to as nMOS), and a control signal TEST indicating a test mode is not shown on the gate electrodes of the switch elements 14a to 14d. A control signal / TEST indicating a normal mode (“/” means an inverted signal of the control signal TEST) is input to the gate electrodes of the switch elements 16a and 16b. .
[0020]
One end of a test wiring 12a is connected to the drain electrode of the switch element 14a, and a test circuit 13a is connected to the source electrode.
[0021]
One end of a test wiring 12b is connected to the drain electrode of the switch element 14b, and a test circuit 13b is connected to the source electrode.
[0022]
The other end of the test wiring 12a is connected to the drain electrode of the switch element 14c, and the test circuit 13c is connected to the source electrode.
[0023]
The other end of the test wiring 12b is connected to the drain electrode of the switch element 14d, and the test circuit 13d is connected to the source electrode.
[0024]
A test wiring 12a is connected to the drain electrode of the switch element 16a, and a power supply wiring 15a is connected to the source electrode.
[0025]
A test wiring 12b is connected to the drain electrode of the switch element 16b, and a power supply wiring 15b is connected to the source electrode.
[0026]
In the normal mode, the signal wiring 11 is a so-called critical path used for transmitting a high-speed signal, and a shield wiring is required to reduce crosstalk between adjacent wirings. The normal mode here is an operation mode used by a general user for the purpose of using the function of the semiconductor device, and means an operation mode set by inputting a command having a specification disclosed to the general user.
[0027]
The test wirings 12a and 12b are formed in the same wiring layer as the signal wiring 11, and are used as signal lines for transmitting signals between the test circuits 13a to 13d in the test mode. Further, the test wirings 12a and 12b are not used as signal lines in the normal mode, but are used as shield lines fixed to the reference potential (Vss).
[0028]
The test mode here refers to an operation mode in which the operation state of the semiconductor device is different from the normal mode described above and is in an exclusive relationship with the normal mode, and includes a test mode with specifications open to general users. Absent. In other words, this test mode is used for operation tests, function tests as development tests at the time of development, and operation tests, function tests, reliability tests as pre-shipment tests performed before shipment to the market. It is.
[0029]
The control signal TEST input to the gate electrodes of the switch elements 14a to 14d is a signal that is "H" in the test mode and "L" in the normal mode, and the "H" level is the signal of the switch elements 14a to 14d. Boosted to a higher boot level by the threshold. This is to prevent the “H” level of a signal propagating therethrough from dropping a so-called threshold when the test wirings 12a and 12b are used as signal lines in the test mode.
[0030]
The control signal / TEST input to the gate electrodes of the switch elements 16a and 16b is “L” in the test mode and “H” in the normal mode. Similarly to the above-described TEST, the “H” level is boosted to the boot level.
[0031]
The test circuits 13a to 13d are logic circuits used in the test mode, and a plurality of test circuits 13a to 13d are arranged at necessary places in the semiconductor device. Further, the test circuits 13a to 13d are not used in the normal mode, and their operations are stopped.
[0032]
Next, the operation of the semiconductor device having the above-described configuration will be described.
[0033]
First, in the test mode of the development test and the pre-shipment test, the control signal TEST is set to “H”, the switch elements 14a to 14d are turned on, the control signal / TEST is set to “L”, and the switch elements 16a and 16b are turned off. The test wiring 12a is set as a signal line between the test circuits 13a and 13c, and the test wiring 12b is set as a signal line between the test circuits 13b and 13d.
[0034]
In this case, since the signal wiring 11 is not shielded, the signal wiring 11 cannot be used as a high-speed signal line, and therefore a high-speed operation test in which the signal wiring 11 is used as a high-speed signal line cannot be performed. However, the ratio of the high-speed operation test to the entire test executed in the test mode is small, and the test circuits 13a to 13d used in the high-speed operation test and the number of wirings between them are the same as the entire test circuits 13a to 13d. Since the number of wirings between circuits is very small, there is no problem if the combination of the test wirings 12a and 12b and the signal wiring 11 is taken into consideration at the time of design.
[0035]
That is, the inter-circuit signals of the test circuits 13a to 13d used in the high-speed operation test are not allocated to the test wirings 12a and 12b, but are allocated to another test dedicated wiring. When a high-speed operation test is performed, the control signal TEST is set to “L”, the control signal / TEST is set to “H”, and the test wirings 12a and 12b are temporarily shielded from the signal lines in the test mode. Switch to wiring and use.
[0036]
The interval between the signal wiring 11 and the test wirings 12a and 12b is determined by a simulation of an allowable crosstalk amount of the signal wiring 11 as in the case of laying out the wiring dedicated to the shield.
[0037]
In the normal mode, the control signal TEST is set to “L” to make the switch elements 14a to 14d non-conductive, and the control signal / TEST is set to “H” to make the switch elements 16a and 16b conductive. As a result, the test wirings 12a and 12b are switched from the signal line in the test mode to the shield wiring of the signal wiring 11 for use.
[0038]
According to the first embodiment, the test wirings 12a and 12b used for the development test and the pre-shipment test can be used as the shield wiring of the signal wiring 11 that becomes a critical path in the normal mode. The number of shield wires can be greatly reduced, and an increase in chip area can be suppressed despite the high-function, high-speed and high-reliability semiconductor system.
[0039]
In the first embodiment described above, the control signal TEST and the control signal / TEST are boosted to the boot level in consideration of the threshold values of the switch elements 14a to 14d and the switch elements 16a and 16b. The power supply voltage (Vdd) may be used as the “H” level. This is because, in general, signals used in the test circuits 13a to 13d are low-speed, and even if the “H” level of the test wirings 12a and 12b drops, the circuit operation is hardly hindered.
[0040]
Further, although the test wirings 12a and 12b are arranged in parallel on both sides of the signal wiring 11, the present invention is not limited to this. For example, if the effect can be confirmed by the simulation of the crosstalk amount, the signal wiring 11 may be arranged only on one side or may be arranged only on a part of the signal wiring 11.
[0041]
Further, although the test circuits 13a to 13d are arranged in a distributed manner, the present invention is not limited to this, and the test wirings 12a and 12b may be wirings between different signal terminals of the same circuit.
[0042]
Further, the power supply wirings 15a and 15b are Vss. In FIG. 1, the power supply wirings 15a and 15b are shown separately for each of the test wirings 12a and 12b. However, the present invention is not limited to this, and Vdd may be used. Both test wirings 12a and 12b may be electrically connected to 15a or 15b.
[0043]
Furthermore, in the above-described first embodiment, the test wirings 12a and 12b are signal lines between the test circuits 13a to 13d, but the present invention is not limited to this. For example, as shown in FIG. 2, it can also be applied to input / output wirings connecting test pads 17a and 17b and signal terminals of test circuits 13a and 13b.
[0044]
In this case, the switch elements 18a and 18b for connecting the test pads 17a and 17b and the test wirings 12a and 12b may be omitted.
[0045]
(Second Embodiment)
FIG. 3 is an image diagram showing a wiring layout in the semiconductor device according to the second embodiment of the present invention. Here, mainly the signal wiring 41 to be shielded, the test wirings 42a and 42b which are used as the test signal line and the shield wiring, and the part related to the control are shown.
[0046]
The semiconductor device according to the second embodiment of the present invention includes a signal wiring 41 to be shielded, test wirings 42a and 42b that use both the test signal line and the shield wiring, and test circuits 43a to 43d used in the test mode. Switch elements 44a to 44d for connecting the test lines 42a and 42b and the test circuits 43a to 43d, a power supply line 45 for supplying a reference potential (Vss), a switch element 46 for connecting the test line 42b and the power supply line 45, and A switch element 47 is provided for connecting the test wirings 42a and 42b.
[0047]
The signal wiring 41 and the test wirings 42a and 42b are arranged substantially in parallel as in the first embodiment.
[0048]
The switch elements 44a to 44d and the switch element 46 are, for example, nMOS, and are connected to the test wirings 42a and 42b in substantially the same manner as in the first embodiment.
[0049]
The difference from the first embodiment is that the test wiring 42a is not directly connected to the reference potential (Vss) via the switch element, and a switch element 47 is provided between the test wiring 42b and the test wiring 42b instead. That is. That is, the control signal / TEST indicating the normal mode is input to the gate electrode of the switch element 47, the test wiring 42a is connected to the drain electrode, and the test wiring 42b is connected to the source electrode.
[0050]
The functions and operations of the signal wiring 41, the test wirings 42a and 42b, the switch elements 44a to 44d, the switch element 46, the test circuits 43a to 43d, and the power supply wiring 45 are the same as those in the first embodiment, and thus description thereof is omitted. . The voltage levels of the control signals TEST and / TEST and the control logic are the same as those in the first embodiment.
[0051]
Further, the operation of the control signal / TEST input to the gate electrode of the switch element 47 is the same as that in the first embodiment.
[0052]
Next, the operation of the semiconductor device having the above-described configuration will be described.
[0053]
First, in the test mode of the development test and the pre-shipment test, the control signal TEST is set to “H” to make the switch elements 44a to 44d conductive, the control signal / TEST is set to “L”, and the switch element 46 and The switch element 47 is turned off, and the test wirings 42a and 42b are set as signal lines between the test circuits 43a to 43d as in the first embodiment.
[0054]
When performing a high-speed operation test, the control signals TEST and / TEST are temporarily inverted, and the test wirings 42a and 42b are switched from the signal line in the test mode to the shield wiring of the signal wiring 41 for use. Is the same as that of the first embodiment.
[0055]
Further, the interval between the signal wiring 41 and the test wirings 42a and 42b is also determined by simulation, as in the first embodiment.
[0056]
Furthermore, in the normal mode, the control signal TEST is set to “L” to turn off the switch elements 14a to 14d, and the control signal / TEST is set to “H” to turn on the switch elements 16a and 16b. Thus, the test wirings 12a and 12b are used by switching from the signal line in the test mode to the shield wiring of the signal wiring 11.
[0057]
According to the second embodiment, as in the first embodiment, the number of shield wirings can be greatly reduced, so that an increase in the chip area can be suppressed.
[0058]
In the second embodiment described above, as in the first embodiment, the control signal TEST and the control signal / TEST are boosted to the boot level, but the present invention is not limited to this.
[0059]
Further, although the test wirings 42a and 42b are arranged in parallel on both sides of the signal wiring 41, the present invention is not limited to this as in the first embodiment.
[0060]
Further, as in the first embodiment, the test wirings 42a and 42b may be wirings between different signal terminals of the same circuit.
[0061]
Furthermore, although the power supply wiring 45 is Vss, it may be Vdd as in the first embodiment.
[0062]
Further, similarly to the first embodiment, the second embodiment can be applied to input / output wirings of the test circuits 43a to 43d.
[0063]
(Third embodiment)
FIG. 4 is an image diagram showing a wiring layout in a semiconductor device according to the third embodiment of the present invention. Here, mainly the signal wiring 61 to be shielded, the test wirings 62a and 62b that are used as both the test signal line and the shield wiring, and the portions related to the control are shown. Further, in order to show a plurality of wiring layers, unlike FIG. 1, the signal wiring 61 and the test wirings 62a and 62b are shown in the perspective view in the middle. However, the power supply wiring having the reference potential (Vss) formed in the uppermost layer of the wiring layer is omitted.
[0064]
The semiconductor device according to the third embodiment of the present invention includes a signal wiring 61 to be shielded, test wirings 62a and 62b that use both the test signal line and the shield wiring, and test circuits 63a and 63b used in the test mode. , Switch elements 64a and 64b connecting the test wirings 62a and 62b and the test circuits 63a and 63b, and switch elements 66a and 66b connecting the test wirings 62a and 62b and a reference potential (Vss) of a power supply wiring (not shown). ing.
[0065]
The signal wiring 61 and the test wirings 62a and 62b are arranged adjacent to each other in the vertical direction with an insulating film interposed therebetween, and the test wirings 62a and 62b are arranged almost in parallel with the signal wiring 61 therebetween. The signal wiring 61 and the test wirings 62a and 62b are formed in different wiring layers.
[0066]
The switch elements 64a and 64b and the switch elements 66a and 66b are, for example, nMOS, and are connected to the test wirings 62a and 62b in substantially the same manner as in the first embodiment.
[0067]
The difference from the first embodiment is that the test wirings 62a and 62b to be connected are arranged above and below the signal wiring 61 and formed in different wiring layers.
[0068]
Since the functions and operations of the signal wiring 61, the test wirings 62a and 62b, the switch elements 64a and 64b, the switch elements 66a and 66b, and the test circuits 63a and 63b are the same as those in the first embodiment, the description thereof is omitted. The voltage levels of the control signals TEST and / TEST and the control logic are the same as those in the first embodiment.
[0069]
Furthermore, since the operation of the semiconductor device having the above-described configuration is the same as that of the first embodiment, description thereof is omitted.
[0070]
According to the third embodiment, not only the same effect as that of the first embodiment can be expected, but also a high shielding effect can be exhibited in the vertical direction of the signal wiring 61, while suppressing an increase in the chip area. A semiconductor system with higher speed and higher reliability can be realized.
[0071]
In the third embodiment described above, the control signal TEST and the control signal / TEST are boosted to the boot level as in the first embodiment, but the present invention is not limited to this.
[0072]
Further, although the test wirings 62a and 62b are arranged parallel to the top and bottom of the signal wiring 61, the present invention is not limited to this as in the first embodiment.
[0073]
Further, as in the first embodiment, the test wirings 62a and 62b may be wirings between different signal terminals of the same circuit.
[0074]
Furthermore, although the power supply wiring is Vss, it may be Vdd as in the first embodiment.
[0075]
Furthermore, as in the first embodiment, the third embodiment can be applied to the input / output wirings of the test circuits 63a and 63b.
[0076]
Further, similarly to the second embodiment, the test wirings 62a and 62b can be connected via the switch element.
[0077]
In the first to third embodiments described above, the switch element is an nMOS. However, the present invention is not limited to this. For example, an nMOS and a p-type MOS-FET (hereinafter referred to as a pMOS). It is also possible to connect the drain electrode and the source electrode, input the control signal TEST to the gate electrode of the nMOS, and input the control signal / TEST to the gate electrode of the pMOS.
[0078]
Similarly, the switch element is not limited to the nMOS, and may be connected to Vdd that supplies the power supply potential using, for example, a pMOS. In this case, it goes without saying that the control signal / TEST input to the gate electrode is inverted.
[0079]
Further, similarly, the switch element is not limited to the nMOS.
[0080]
Furthermore, in the above-described first to third embodiments, the high-speed operation test is performed by temporarily setting the test wiring as the shield wiring, but the present invention is not limited to this. In the test mode, unlike the normal mode, the test circuit that operates according to the type of test to be executed and the signals used in it can be specified at the design stage. For example, the signal that needs to be shielded according to the type of high-speed operation test It is also possible to design so that only the test wiring corresponding to the wiring is set as the shield wiring.
[0081]
【The invention's effect】
As described above, according to the present invention, the test wirings 12a and 12b used for the development test and the pre-shipment test can be used as the shield wiring of the signal wiring that becomes a critical path in the normal mode. Despite the high-speed and high-reliability semiconductor system, an increase in the chip area can be suppressed.
[Brief description of the drawings]
FIG. 1 is an image diagram showing a wiring layout in a semiconductor device according to a first embodiment of the present invention.
FIG. 2 is an image view showing another wiring layout in the semiconductor device according to the first embodiment of the present invention.
FIG. 3 is an image diagram showing a wiring layout in a semiconductor device according to a second embodiment of the present invention.
FIG. 4 is an image diagram showing a wiring layout in a semiconductor device according to a third embodiment of the present invention.
[Explanation of symbols]
11, 41, 61 Signal lines 12a, 12b, 42a, 42b, 62a, 62b Test lines 13a-13d, 43a-43d, 63a, 63b Test circuits 14a-14d, 16a, 16b, 18a, 18b, 44a-44d, 46, 47, 64a, 64b, 66a, 66b Switch elements 15a, 15b, 45 Power supply wirings 17a, 17b Test pads

Claims (9)

At least one signal wiring used as a signal line;
A test wiring that is disposed in the vicinity of the signal wiring with an insulating film interposed therebetween, and at least a part of the wiring is formed substantially parallel to the signal wiring;
A power supply wiring connected to the test wiring and set to a predetermined power supply potential;
Test means connected to the test wiring;
First connection means for connecting the test means and the test wiring in a test mode;
2. A semiconductor device comprising: a second connection means for connecting the test wiring and the power supply wiring in a normal mode, making the first connection means non-conductive and using the test wiring as a shield wiring . The semiconductor device according to claim 1, wherein a plurality of the test wirings are arranged with respect to the signal wiring. The semiconductor device according to claim 1, wherein a plurality of the power supply wirings are arranged with respect to the signal wirings. The semiconductor device according to claim 1, wherein the test unit is connected to both ends of the test wiring. 2. The semiconductor device according to claim 1, wherein the test means is connected to one end of the test wiring, and the other end is connected to a test terminal. The semiconductor device according to claim 2, wherein the test wiring is disposed at a position facing each other across the signal wiring. The first connection means is constituted by a first switch element provided between the test means and the test wiring,
The second connection means includes a second switch element provided between the test wiring and the power supply wiring,
2. The semiconductor device according to claim 1, wherein a control signal is applied to a gate of the first switch element, and an inverted signal of the control signal is applied to a gate of the second switch element. The semiconductor device according to claim 1, wherein the test wiring is formed in the same wiring layer as the signal wiring. The semiconductor device according to claim 1, wherein the test wiring is formed in a wiring layer different from the signal line.

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