JP2005010424A - Method of driving plasma display panel - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To achieve high luminance display by means of an AC type plasma display panel having a structure with which the discharge interference between cells hardly occurs. <P>SOLUTION: The cells constituting a screen are divided to a plurality of sets each one of which consists of two cells adjacent to each other in a column direction, and matrix display having the set of the two cells as a light emission unit is realized by sequentially performing partial addressing, transfer preparation and transfer. The partial addressing refers to the addressing to be performed with only one of the cells in the set as a target. The transfer preparation refers to an operation to generate discharge between display electrodes only in the cells to be lighted among the targets of the partial addressing. The transfer refers to an operation to generate the discharge between the display electrodes in the cells to be lighted among the addressed cells and the cells to be combined with these cells as the set. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a method for driving a plasma display panel (PDP) and a display device that displays an image using the plasma display panel.
[0002]
Plasma display devices are becoming widespread as large screen television receivers. In order to promote the spread, improvement of display performance and overall operation performance are being promoted.
[0003]
[Prior art]
A surface discharge type is adopted in an AC type plasma display panel for color display. The surface discharge format used here refers to the display electrodes that serve as anodes and cathodes in the display discharge that determines the amount of light emitted from the cell, arranged in parallel on the front or back substrate and addressed so as to intersect the display electrode pair. In this form, electrodes are arranged.
[0004]
There are two forms of display electrode arrangement in the surface discharge format. Here, for convenience, one is referred to as form A and the other as form B. In the form A, a pair of display electrodes is arranged for each row of the matrix display. The total number of display electrodes is twice the number of rows n. In the form A, since each row is independent on control, the driving sequence can be simplified. However, since the electrode gap (referred to as a reverse slit) between adjacent rows becomes a non-light emitting region, the utilization factor of the display surface is small. In the form B, the number of display electrodes obtained by adding 1 to the number n of rows is arranged at a ratio of three to two rows at equal intervals. In the form B, adjacent display electrodes constitute an electrode pair for surface discharge, and all display electrode gaps become surface discharge gaps. Form B is superior to Form A in terms of higher definition and display surface utilization.
[0005]
The drive sequence applied to the electrode arrangement of form B is an interlaced format in which the display of odd-numbered row data and the display of even-numbered row data are performed in a time-sharing manner. Conventionally, as disclosed in Japanese Patent Application Laid-Open No. 9-160525, only the odd-numbered cells in each column are lit in the odd-field display, and only the even-numbered cells are lit in the even-field display. Was done. The light emission unit of the matrix display was one cell.
[0006]
On the other hand, as a modified example of the cell structure of the plasma display panel of form B, as disclosed in JP-A-12-113828, the display electrodes are divided in the column direction and electrode gaps are formed between the cells ( As shown in FIG. 12) of Japanese Patent Laid-Open No. 12-113828) and Japanese Patent Laid-Open No. 2002-108279, the discharge space is made cell-by-cell by a mesh-like partition wall (discharge barrier) that divides the discharge space into cells. There is a partitioned structure (FIG. 2 of JP-A-2002-108279).
[0007]
[Problems to be solved by the invention]
The driving of a typical form B plasma display panel has a problem that it is difficult to separate discharges between cells arranged in the column direction. Since all the display electrode gaps have the same size suitable as a discharge gap, the discharge of each cell tends to excessively spread to the adjacent cell. Therefore, it is conceivable to employ the above-described modification as the panel structure.
[0008]
However, if the electrode gap is provided between the cells without increasing the row pitch, the area of the discharge portion of each cell is inevitably reduced, and the display brightness is lowered. Similarly, when the cells are partitioned by the partition walls, the discharge of one cell is similarly reduced and the luminance is lowered.
[0009]
An object of the present invention is to realize high-luminance display by an AC type plasma display panel having a structure in which discharge interference between cells hardly occurs. Another object is to provide a high-luminance matrix display with the same row pitch as the cell array pitch.
[0010]
[Means for Solving the Problems]
As a first solution, in the present invention, a plurality of cells constituting a screen are divided into a plurality of groups arranged in the column direction and two adjacent cells as one set, and partial addressing, transfer preparation, transfer, and By performing lighting maintenance in order, a matrix display using a set of two cells as a light emission unit is realized. Partial addressing is addressing performed on only one cell in each of the plurality of sets.
Addressing is an operation in which the charged state of a cell to be lit and the charged state of a cell that should not be lit are made different during a period in which lighting is maintained. The transfer preparation is an operation for causing discharge between display electrodes only in the cells to be lit among the address cells to be partially addressed. In the transfer preparation, the wall charge amounts of the display electrode pairs of the cells to be lit are made equal so that the wall charge distribution is the same as that in the case where the wall charges are formed by surface discharge. Transfer means that the wall charge amount of all cells to be lit is larger than the wall charge amount of other cells (cells that should not be lit), the cells to be lit among the address cells, and each of these cells. This is an operation for generating a discharge between the display electrodes in the cell pair. As a result of the transfer, the charged state of the cell to be lit becomes a state in which discharge occurs during the lighting maintenance period. “Lighting maintenance” is an operation of causing display discharges a number of times corresponding to the brightness to be displayed in all cells to be lit.
[0011]
Since the light emission unit is a set of two cells, the luminance is almost twice that in the case where the cell is the light emission unit. By performing the transfer, the time required for addressing is shortened as compared with the case where one addressing and the other addressing of each set of cells are performed. In the drive circuit in which only one display electrode of the display electrode pair is a scan electrode, the transfer relaxes the restriction on the positional relationship between the light emission unit and the scan electrode. By performing transfer preparation prior to transfer, transfer reliability is increased. Then, the frame is divided into two fields, and the grouping is performed for each field so that the position of the light emission unit is shifted by one cell in the column direction between the fields. In at least one field, the addressing, the transfer preparation, and the If the transfer and the lighting maintenance are performed, a matrix display with high luminance having the same row pitch as the cell arrangement pitch is realized.
[0012]
As a second solution, in the present invention, the display electrodes are arranged in the first electrode and the second electrode so that the electrode positional relationship in the column direction is opposite to the adjacent cells in the column direction for each of all the cells. By classifying the cells into electrodes and sequentially performing addressing including two-electrode simultaneous scanning and lighting maintenance, a matrix display using a set of two cells as a light emission unit is realized. In the two-electrode simultaneous scanning, an operation of temporarily biasing two adjacent second electrodes at a common timing with at least one first electrode interposed therebetween is repeated by switching the bias target. It is an operation.
[0013]
DETAILED DESCRIPTION OF THE INVENTION
[First Embodiment]
The first embodiment is a driving mode for performing transfer, and is applied to a plasma display panel having a structure in which discharge interference between cells in the column direction can occur.
[0014]
FIG. 1 shows a configuration of a display device according to the first embodiment. The display device 100 includes an AC-type plasma display panel (PDP) 1 having a large number of cells constituting rows and columns of a matrix display, and a drive unit 70 that controls light emission of the cells. ing.
[0015]
In the plasma display panel 1, display electrodes X and Y constituting an electrode pair for generating a surface discharge type display discharge are arranged in parallel, and address electrodes A are arranged so as to intersect the display electrodes X and Y. ing. The display electrodes X and Y extend in the horizontal direction, and the address electrodes A extend in the column direction (vertical direction). The total number of display electrodes X and Y is the number of cells in one column plus 1 (2n), and the total number of address electrodes A is the same as the number of columns (m). In the figure, the suffixes of the reference symbols of the display electrodes X and Y and the address electrode A indicate the arrangement order.
[0016]
The drive unit 70 includes a control circuit 71 responsible for drive control, a power supply circuit 73 that outputs drive power, an X driver 76 for controlling the potential of the display electrode X, a Y driver 77 for controlling the potential of the display electrode Y, and An A driver 78 for controlling the potential of the address electrode A is provided. The Y driver 77 includes a scan circuit that enables individual potential control for the n display electrodes Y. Frame data Df indicating the luminance levels of the three colors R, G, and B is input to the drive unit 70 together with various synchronization signals from an image output device such as a TV tuner or a computer. The frame data Df is temporarily stored in a frame memory in the control circuit 71. The control circuit 71 converts the frame data Df into subfield data Dsf for gradation display and serially transfers it to the A driver 78. The subfield data Dsf is display data of 1 bit per cell, and the value of each bit indicates whether or not light emission of the cell in the corresponding one subfield is required, strictly speaking, whether or not address discharge is required.
[0017]
FIG. 2 shows a cell structure of the plasma display panel 1. In FIG. 2, a portion corresponding to 3 × 2 cells in the plasma display panel 1 is drawn with the pair of substrate structures 10 and 20 separated so that the internal structure can be clearly understood.
[0018]
The plasma display panel 1 includes a pair of substrate structures 10 and 20. A board | substrate structure means the structure which consists of a glass substrate of the magnitude | size beyond a screen size and another at least 1 type of panel component. The substrate structure 10 on the front side includes a glass substrate 11, electrodes X ′ and Y ′, a dielectric layer 17, and a protective film 18. Each of the electrodes X ′ and Y ′ is composed of a thick strip-shaped transparent conductive film that forms a surface discharge gap and a thin strip-shaped metal film as a bus conductor that lowers the electric resistance. A pair of adjacent electrodes X ′ and X ′ constitute one display electrode X, and a pair of adjacent electrodes Y ′ and Y ′ constitute one display electrode Y. The display electrodes X and Y are covered with a dielectric layer 17 and a protective film 18. The substrate structure 20 on the back side includes a glass substrate 21, an address electrode A, an insulating layer 24, a plurality of partition walls 29, and phosphor layers 28R, 28G, and 28B. The partition wall 29 is a belt-like structure having a straight planar shape, and one partition wall 29 is provided for each electrode gap of the address electrode array. The partition wall 29 divides the discharge gas space for each column of the matrix display, and the column space 31 corresponding to each column is formed. The column space 31 is continuous across all rows. The phosphor layers 28R, 28G, and 28B emit light when excited by ultraviolet rays emitted by the discharge gas. Italic alphabets R, G, B in the figure indicate the emission color of the phosphor.
[0019]
FIG. 3 is a schematic diagram of an electrode arrangement. Two adjacent electrodes X ′ and X ′ are arranged with a gap G <b> 2 therebetween, connected on the outside of the screen 51 including the cells 60, and are electrically integrated as the display electrode X. Similarly, two adjacent electrodes Y ′ and Y ′ are arranged with a gap G <b> 2 therebetween, connected on the outside of the screen 51, and electrically integrated as the display electrode Y. The connecting portions of the display electrodes X and Y are distributed to one end and the other end of the screen 51 in order to facilitate connection with the driver. Each of the display electrodes X and Y is divided into two electrodes inside the screen 51. The display electrodes X and the display electrodes Y are arranged alternately one by one in the order of XYXY... XY. Anode and cathode). The total number of electrode pairs is the same as the number of cells in the column.
[0020]
Hereinafter, a method for driving the plasma display panel 1 in the display device 100 will be described.
FIG. 4 is a conceptual diagram of field division. A time-series frame F that is an input image is composed of an odd field F1 and an even field F2. If the frame F is in progressive format, it is converted to interlaced format. Each of the odd field F1 and the even field F2 includes q subfields SF weighted with luminance.₁, SF₂,... SFq (hereinafter, subscripts indicating the display order are omitted). Luminance weight {W₁, W₂,... Wq} defines the number of display discharges. The subfield arrangement may be in the order of weights or in another order. In order to display the q subfields SF constituting the odd field F1, the odd lines L of the screen are displayed.₁, L₃, L₅ .. Are used, and even number rows L are used to display q subfields SF constituting even field F2.₂ , L₄ , L₆... is used. It should be noted here that each row L is composed of twice as many cells as the number of columns m in order to increase luminance.
[0021]
The light emission unit of the matrix display performed by the display device 100 is a set of two cells arranged in the column direction and adjacent to each other. As shown in FIG. 5A, the light emitting unit U1 in the odd field is composed of two cells sharing one display electrode Y. As shown in FIG. 5B, the light emitting unit U2 in the even field is composed of two cells sharing one display electrode X. Since the amount of line shift between the odd-numbered field and the even-numbered field is the same as the cell pitch P in the column direction, display with the same resolution as conventional interlaced display using one cell as the light emission unit is possible.
[0022]
FIG. 6 shows a breakdown of the subfields. In the display of odd fields, the subfield period Tsf assigned to one subfield is divided into a reset period TR, an address period TA, and a sustain period TS. In the even field display, the subfield period Tsf is divided into a reset period TR, a partial address period TP, a transfer preparation period TU, a transfer period TM, and a sustain period TS. The partial address period TP, the transfer preparation period TU, and the transfer period TM are unique to the present invention.
[0023]
The reset period TR is a period for addressing preparation (generally called initialization) for equalizing wall charges for all cells. The address period TA is a period for addressing in which the wall charge amount of a cell to be lit is larger than that of other cells. The sustain period TS is a period for sustaining lighting that causes display discharge of the number of times corresponding to the brightness to be displayed.
[0024]
The partial address period TP is a period for partial addressing, which is addressing for only one cell of the light emitting unit U2. The transfer preparation period TU is a period for transfer preparation for reducing the bias of the wall charges between the display electrodes in the cells to be lit among the “address cells” to be subjected to partial addressing. The transfer period TM is a transfer period in which the address cell information (wall charge amount) is given to the cells forming a pair with each address cell.
[0025]
[Example 1]
FIG. 7 shows the drive voltage waveform of the odd field in the first embodiment. In the following, odd-numbered display electrodes X (X₁, X₃, X₅,..., Display electrode X_oddEven-numbered display electrodes X (X₂, X₄, X₆,..., Display electrode X_evenThat's it. Similarly, odd-numbered display electrodes Y (Y₁, Y₃, Y₅,..., Display electrode Y_oddEven-numbered display electrodes Y (Y₂, Y₄, Y₆,..., Display electrode Y_evenThat's it.
[0026]
In the reset period TR, a positive obtuse wave pulse is applied to the display electrode Y. That is, bias control is performed to monotonously increase the potential of the display electrode Y from 0 to Vr1. Subsequently, a negative blunt wave pulse is applied to the display electrode Y. That is, bias control is performed to monotonously drop the potential of the display electrode Y to −Vr2. At this time, in order to speed up the processing, a positive offset bias (Vr) is applied to the display electrode X._X) Is given. The potential of the address electrode A is kept at 0 throughout the reset period TR. The minute discharge generated by the first positive obtuse wave pulse application generates an appropriate wall voltage having the same polarity in all the cells regardless of the lighting / non-lighting in the previous display. The minute discharge generated by the second negative blunt wave pulse application adjusts the wall voltage to a value corresponding to the difference between the discharge start voltage and the amplitude of the applied voltage. The wall voltage adjustment value is generally zero or a value close to it when addressing in the writing format, and is generally a little smaller than the discharge start voltage value when performing addressing in the erasing format.
[0027]
In the address period TA, scan pulses having an amplitude of −Vy are sequentially applied to the display electrodes Y one by one. That is, row selection is performed. In synchronization with the row selection, an address pulse is applied to the address electrode A corresponding to the selected cell in the selected row. An address discharge occurs in the selected cell selected by the display electrode Y and the address electrode A, and a predetermined wall charge amount changes. The selected cell is a cell that should be lit in the case of the writing type, and a cell that should not be lit in the case of the erasing type. In the following description, addressing is a writing format.
[0028]
In the sustain period TS, positive sustain pulses having an amplitude of Vs are alternately applied to the display electrode Y and the display electrode X. A display discharge is generated between the display electrodes of the cells to be lit, each having an appropriate amount of wall charges.
[0029]
As shown in the figure, in the odd field, the display electrode X_oddAnd display electrode X_evenThe waveforms of are the same. Display electrode Y_oddAnd display electrode Y_evenAs for the waveform of the reset period TR and the sustain period TS, the waveforms are the same.
[0030]
FIG. 8 shows the drive voltage waveform of the even field in the first embodiment. Since the waveforms of the reset period TR and the sustain period TS are the same as the waveforms of the odd field, the description thereof is omitted.
[0031]
The partial address period TP is divided into a first half period TP1 and a second half period TP2.
In the first half period TP1, the display electrode X_evenIs the potential Va_XBiased to the display electrode Y_oddOne scan pulse with an amplitude of −Vy is sequentially applied. That is, the cell on the upstream side (upper side in FIG. 5) of the odd-numbered light emitting unit U2 in each column of the screen is selected. In synchronization with this selection, an address pulse for generating an address discharge is applied to the address electrode A corresponding to the cell to be lit among the selected address cells. Such an operation in the first half period TP1 (part of partial addressing) is referred to as “first half addressing”.
[0032]
In the second half period TP, the display electrode X_oddIs the potential Va_XBiased to the display electrode Y_evenOne scan pulse with an amplitude of −Vy is sequentially applied. That is, the upstream cell of the even-numbered light emitting unit U2 in each column of the screen is selected. In synchronization with this selection, an address pulse is applied to the address electrode A corresponding to the cell to be lit among the selected address cells. Such an operation in the second half period TP2 is referred to as “second half addressing”.
[0033]
In the transfer preparation period TU, among the “first half address cells” to be subjected to the first half addressing, the discharge between the display electrodes is caused twice only in the cells in which wall charges are formed by the address discharge (cells to be lit), Thereafter, the electrode potential is controlled so that the discharge between the display electrodes is generated twice only in the cells to be lit among the “second half address cells” to be subjected to the second half addressing. The display electrode X is temporarily at the potential Vu_XThe display electrode Y is temporarily biased to the potential Vu._YBiased.
[0034]
In preparation for transfer, it is necessary to prevent discharge from occurring in the address cell and to prevent discharge from occurring in the transfer cell. This condition is satisfied by setting the potential relationship as follows. In preparation for transfer to the first half address cell, the display electrode Y_oddHigh level, display electrode X_evenLow level (to generate discharge), display electrode X_oddHigh level (to reduce the voltage applied to the second half transfer cell), display electrode Y_evenIs at a low level (to reduce the voltage applied to the first half transfer cell). In the transfer preparation for the second half address cell, the display electrode Y_evenHigh level, display electrode X_oddLow level (to generate discharge), display electrode X_evenHigh level (to reduce the voltage applied to the second half transfer cell), display electrode Y_oddIs at a low level (to reduce the voltage applied to the first half transfer cell).
[0035]
In the transfer period TM, first, the electrode potential is set so that a discharge between display electrodes occurs in the cells to be lit among the first half address cells, and a discharge is induced between the display electrodes in the adjacent cells. Be controlled. The adjacent cell is a cell to be lit among the first half transfer cells which are a cell paired with the first half address cell. Of the first-half address cells, cells that should not be lit (cells in which no wall charges are formed) are controlled so that no discharge occurs. Next, the electrode potential is controlled so that a discharge between the display electrodes is generated in the cell to be lit among the second half address cells, and the discharge is induced between the display electrodes in the adjacent cells. The adjacent cell at this time is a cell to be lit among the latter half transfer cells which are a pair with the latter half address cell. The display electrode X of the cell causing the discharge has the potential Vm._XOr potential -Vm_XThe display electrode Y is biased to the potential Vm._YOr potential -Vm_YBiased.
[0036]
FIG. 9 shows the direction of transfer. The addressing contents are copied from the top to the bottom of the figure from the first half address cell to the first half transfer cell and from the second half address cell to the second half transfer cell. If the address cell is a cell to be lit, a wall charge equivalent to that of the address cell is formed in the transfer cell. If the address cell is a cell that should not be lit, no discharge occurs in the address cell. Therefore, no discharge occurs in the transfer cell, and a state in which the wall charges are small is maintained. In other words, the transfer reflects information on whether the address cell should be lit or not in the transfer cell.
[0037]
FIG. 10 shows the concept of transfer preparation and transfer. Here, focusing on the first-half address cells and the first-half transfer cells shown as representatives, operations unique to the present invention will be described.
As shown in FIG. 10A, in the first half addressing, the display electrode Y_oddA so-called counter discharge 91 is generated between the display electrode and the address electrode A, and a surface discharge 92 between the display electrodes is generated using this as a trigger. Since the counter discharge 91 is positively generated, if attention is paid to the display electrodes of the first half address cells at the end of the addressing, the wall charges are likely to be biased as shown in FIG. That is, the charge amount of the display electrode pair is often uneven. Wall charge bias makes transfer uncertain. Display electrode Y_oddSince the wall charges are also formed on the transfer cell side, the state of the first half address cell is easily transferred to the second half transfer cell, and display defects are likely to occur. As a countermeasure against these problems, the transfer preparation causes a surface discharge between the display electrodes only in the first half address cells. As a result, as shown in FIG. 10D, the charge amounts of the display electrode pairs of the first half address cells are equalized. In this example, since the number of times of discharge for transfer preparation is 2, the polarity of the wall charge at the end of transfer preparation is the same as the polarity at the start of transfer preparation. As shown in FIG. 10E, in the transfer, surface discharge occurs in the first half address cell, and the surface discharge also occurs in the first half transfer cell as a trigger. These surface discharges form the same wall charges in the first half address cells and the first half transfer cells as shown in FIG.
[0038]
[Example 2]
FIG. 11 shows the drive voltage waveform of the even field of the second embodiment. Of the waveform of the second embodiment, the transfer period TM is different from that of the first embodiment.
[0039]
In the second embodiment, the electrode potential is controlled so that a high voltage is not applied to the address cell during transfer and only a high voltage is applied to the transfer cell. In the transfer operation of the first embodiment, for example, at the time of transfer from the first half address cell to the first half transfer cell, the display electrode Y_oddAnd display electrode Y_evenBoth potential Vm_YTo display electrode X_evenNegative potential -Vm_XThus, the voltage applied to the transfer cell is set to be equal to or lower than the discharge start voltage and equal to or higher than the sustain voltage, and discharge is generated in the transfer cell using the discharge of the address cell as a trigger. In this case, since a high voltage is applied also to the address cell, the discharge is likely to spread and the effect of the trigger on the transfer cell is great. However, the discharge spreads in the direction toward the transfer cell (second-half transfer cell) sandwiching the display electrode Y, and the transfer operation becomes unstable. Example 2 solves this problem.
[0040]
Example 3
FIG. 12 shows a breakdown of subfields in the third embodiment. In both the odd field and the even field, there are a reset period TR, a partial address period TP, a transfer preparation period TU, a transfer period TM, and a sustain period TS.
[0041]
In the display of odd fields, addressing including transfer is performed instead of the addressing of the first embodiment in which the cells on both sides of the display electrode Y are selected. This solves the problem that the discharge spreads more than necessary and the addressing becomes unstable.
[0042]
FIG. 13 shows drive voltage waveforms in the odd field of the third embodiment. The drive waveform of Example 1 or Example 2 is applied to the even field. Of the waveform of the third embodiment, the portion from the partial address period TP to the transfer period TM is different from the waveform of the first embodiment.
[0043]
In Example 3, the display electrode Y_oddAnd display electrode X_oddThe cell paired with is the first half address cell, and the display electrode Y_evenAnd display electrode X_evenThe cell paired with is the latter half address cell. Display electrode Y_oddAnd display electrode X_evenThe cell paired with is the first half transfer cell, and the display electrode Y_evenAnd display electrode X_oddThe cell paired with is the latter half transcription cell.
[0044]
Example 4
FIG. 14 shows the direction of transfer in Example 4. In Example 4, the transfer is performed in both the odd field and the even field, and the transfer direction is different between the fields. In the odd field, transfer from the upstream side to the downstream side is performed, and in the even field, transfer from the downstream side to the upstream side is performed. In both fields, display electrode Y_evenAnd display electrode X_evenThe cell paired with is the first half address cell, and the display electrode Y_oddAnd display electrode X_oddThe cell paired with is the latter half address cell.
[0045]
Since each cell is fixed to either an address cell or a transfer cell, the allowable range for setting the drive voltage can be expanded by specifying the structure of each cell to be preferable as an address cell or a transfer cell. For example, the counter discharge start voltage of the address cell can be lowered by patterning the address electrode Ab as shown in FIG. 15 so that the portion in the address cell is locally thick. Since address discharge is more likely to occur in the address cell than in the transfer cell, addressing reliability is increased.
[0046]
The above first to fourth embodiments can be applied to driving a plasma display panel having display electrodes as shown in FIG.
In FIG. 16, each of the display electrodes X and Y is composed of two strip-shaped transparent conductive films 41 and one ladder-shaped metal film 42. The metal film 42 has two thin horizontal strips 421 along each transparent conductive film 41 and a vertical strip 422 that connects the horizontal strips 421 inside the screen. The vertical band portions 422 are arranged between the adjacent partition walls 29, and the arrangement positions thereof are selected so that the display electrodes X and the display electrodes Y alternate. In other words, when one cell is viewed, an electrode pair structure in which the electrode area is biased such that one display electrode has the vertical band portion 422 and the other does not exist is formed. In general, in the discharge by alternating pulses between electrodes having different electrode areas, the magnitude of the discharge is determined by the electrodes having a small area. Therefore, even if the connecting portion is provided in one non-discharge gap, the discharge does not spread if the other non-discharge gap is large. Since it is not necessary to overlap the partition wall 29, high accuracy is not required for alignment of the front substrate and the rear substrate in manufacturing.
[Second Embodiment]
The second embodiment is a driving mode in which two-electrode simultaneous scanning is performed, and is suitable for a plasma display panel having a structure in which discharge interference between cells in the column direction cannot occur. However, the present invention can also be applied to a plasma display panel having a structure in which discharge interference occurs between cells.
[0047]
FIG. 17 shows a configuration of a display device according to the second embodiment. The display device 200 includes an AC type plasma display panel (PDP) 2 having a large number of cells constituting rows and columns of a matrix display, and a drive unit 80 that controls light emission of the cells. ing.
[0048]
In the plasma display panel 2, display electrodes X and Y constituting an electrode pair for generating a surface discharge type display discharge are arranged in parallel, and address electrodes A are arranged so as to intersect these display electrodes Xb and Yb. ing. The display electrodes Xb and Yb extend in the horizontal direction, and the address electrodes A extend in the column direction (vertical direction). The total number of display electrodes X and Y is the number of cells in a column plus 1 (2n), and the total number of address electrodes A is the same as the number of columns (m). In the figure, the suffixes of the reference symbols of the display electrodes Xb and Yb and the address electrode A indicate the arrangement order.
[0049]
The drive unit 80 includes a control circuit 81 responsible for drive control, a power supply circuit 83 that outputs drive power, an X driver 86 for controlling the potential of the display electrode Xb, a Y driver 87 for controlling the potential of the display electrode Yb, and An A driver 88 for controlling the potential of the address electrode A is provided. The Y driver 87 includes a scan circuit that enables individual potential control for the n display electrodes Yb.
[0050]
FIG. 18 shows a cell structure of the plasma display panel 2. In FIG. 18, a portion corresponding to 3 × 2 cells in the plasma display panel 2 is drawn by separating the pair of substrate structures 10 b and 20 b so that the internal structure can be clearly understood.
[0051]
The plasma display panel 2 includes a pair of substrate structures 10b and 20b. The front-side substrate structure 10 b includes a glass substrate 11, electrodes Xb and Yb, a dielectric layer 17, and a protective film 18. Each of the electrodes Xb and Yb is composed of a thick strip-shaped transparent conductive film that forms a surface discharge gap and a thin strip-shaped metal film as a bus conductor that lowers the electrical resistance. The display electrodes Xb and Yb are covered with a dielectric layer 17 and a protective film 18. The substrate structure 20b on the back side includes the glass substrate 21, the address electrode A, the insulating layer 24, one mesh partition 290, and phosphor layers 28Rb, 28Gb, and 28Bb. The partition wall 290 partitions the discharge gas space for each cell. The phosphor layers 28Rb, 28Gb, 28Bb are excited by the ultraviolet rays emitted by the discharge gas and emit light. Italic alphabets R, G, B in the figure indicate the emission color of the phosphor.
[0052]
FIG. 19 is a schematic diagram of an electrode arrangement. In the screen 52 composed of the cells 62, the display electrodes Xb and the display electrodes Yb are arranged alternately one by one in the order of XYXY... XY, and the display electrodes Xb and the display electrodes Yb adjacent to each other across the discharge gap G1 face each other. An electrode pair (anode and cathode) for discharge is formed. The total number of electrode pairs is the same as the number of cells in the column.
[0053]
Hereinafter, a method for driving the plasma display panel 2 in the display device 200 will be described.
Example 5
FIG. 20 shows the drive voltage waveform of the even field of the fifth embodiment, and FIG. 21 shows the scanning order in the even field of the fifth embodiment. The waveforms of the reset period TR and the sustain period TS are the same as those in the first embodiment. The address period TA is divided into a first half period TA1 and a second half period TA2.
[0054]
In the first half period TA1, the display electrode Xb_oddV potential_XHAnd the display electrode Xb_evenV potential_XHLower potential V_XLThe display electrode Yb_oddAnd display electrode Yb_evenAt the same time, a scan pulse having an amplitude −Vy is applied. Thereby, the display electrode Xb_oddAddress operations are simultaneously performed on two cells sharing the same.
[0055]
In the second half period TA2, the display electrode Xb_evenV potential_XHAnd the display electrode Xb_oddV potential_XLThe display electrode Yb_oddAnd display electrode Yb_evenAt the same time, a scan pulse is applied. Thereby, the display electrode Xb_evenAddress operations are simultaneously performed on two cells sharing the same.
[0056]
For example, when the waveform of the first embodiment is applied to the odd field, addressing not based on transfer is realized. As a result, circuit elements and power sources specific to the transfer operation can be reduced.
[0057]
Display electrode Xb_oddAnd display electrode Xb_evenMay be replaced. However, it is necessary to scan the cells sandwiching the display electrode Xb. For example, Xb from the first in the scanning direction_odd, Yb_odd, Xb_even, Yb_evenDisplay electrode Xb when aligned with_odd  Is set to the high level in the first half, the first pulse of the first half scan is the display electrode Yb._oddOnly applied to. After the second shot, the display electrode Yb_oddAnd display electrode Yb_evenAre simultaneously scanned. The second half is display electrode Xb_evenBecomes high level and the display electrode Yb starts from the first pulse._oddAnd display electrode Yb_evenAre simultaneously scanned.
[0058]
Example 6
FIG. 22 shows drive voltage waveforms in the odd field of the sixth embodiment. The address operation is performed on the cells above and below the display electrode Yb in the address period, as in the first embodiment. In the sixth embodiment, the address period is divided into a first half period TA1 and a second half period TA2.
[0059]
In the first half period TA1, the display electrode Yb_oddAre scanned and the display electrode Yb is displayed in the latter half period TA2._evenAre scanned. A cell scanned in the first half is called a first half address cell, and a cell scanned in the second half is called a second half address cell. The first half address operation reduces the wall charge on the electrode on the second half address cell side of the display electrode Xb, and an address miss occurs at the second half address. Therefore, in the second half address period TA2, an address miss can be prevented by setting the voltage applied to the display electrode Xb higher than that in the first half address period. For even fields, transfer may be used as in the first and second embodiments, or simultaneous scanning may be used as in the fifth embodiment.
[0060]
Example 7
FIG. 23 shows drive voltage waveforms in the odd-numbered field of the seventh embodiment. In the sixth embodiment, the latter half address is prevented from being weakened by increasing the potential of the display electrode Xb of the latter half address. In the seventh embodiment, the bias potential by the scan pulse in the second half period TA2 is set to −V lower than that in the first half period TA1._YLBy doing so, the same effect as in the sixth embodiment can be obtained.
[0061]
Example 8
FIG. 24 shows the drive voltage waveform of the even field in the eighth embodiment. Even in the case where the two display electrodes Yb are scanned simultaneously as in the fifth embodiment, it is possible to prevent the latter half address from being weakened by increasing the potential of the display electrode Xb in the latter half period TA2.
[0062]
Example 9
FIG. 25 shows the drive voltage waveform of the even field in the ninth embodiment. In the eighth embodiment, the potential of the display electrode Xb in the latter half period TA2 is increased to prevent the latter half address from being weakened. However, the bias potential caused by the scan pulse in the latter half period TA2 is lower than that in the first half period TA1._YLBy doing so, the same effect as in Example 8 can be obtained.
[0063]
The above Examples 5 to 9 can be applied to driving a plasma display panel having display electrodes as shown in FIG.
In FIG. 26, each of the display electrodes Xb and Yb is composed of two strip-like transparent conductive films 41 and one ladder-like metal film 42b. The metal film 42b has two thin horizontal strips along each transparent conductive film 41 and a vertical strip that connects the horizontal strips inside the screen. The vertical belt portion is disposed between the partition walls 290. That is, the electrode gap G3 is formed at the boundary position of the cells arranged in the column direction. By forming the electrode gap G3, the facing area between the display electrode and the address electrode is reduced, and the interelectrode capacitance is reduced. In particular, in the portion where the partition wall 290 exists, it is effective to provide the electrode gap G3 because the dielectric constant of the partition wall is larger than the discharge gas.
[0064]
【The invention's effect】
According to the first to tenth aspects of the present invention, high-luminance display can be realized by an AC type plasma display panel having a structure in which discharge interference between cells hardly occurs.
[0065]
According to the invention of claim 3 or claim 4, it is possible to perform matrix display with high luminance having the same row pitch as the cell arrangement pitch.
[Brief description of the drawings]
FIG. 1 is a diagram illustrating a configuration of a display device according to a first embodiment.
FIG. 2 is a diagram showing a cell structure of a plasma display panel.
FIG. 3 is a schematic diagram of an electrode arrangement.
FIG. 4 is a conceptual diagram of field division.
FIG. 5 is a diagram illustrating grouping of cells.
FIG. 6 is a diagram showing a breakdown of subfields.
7 is a diagram showing drive voltage waveforms in odd-numbered fields in Example 1. FIG.
8 is a diagram illustrating a drive voltage waveform in an even field according to the first embodiment. FIG.
FIG. 9 is a diagram illustrating a direction of transfer.
FIG. 10 is a diagram showing a concept of transfer preparation and transfer.
FIG. 11 is a diagram illustrating a drive voltage waveform in an even field in Example 2;
12 is a diagram showing a breakdown of subfields in Example 3. FIG.
13 is a diagram showing a drive voltage waveform in an odd field in Example 3. FIG.
14 is a diagram showing a transfer direction in Example 4. FIG.
FIG. 15 is a diagram showing an example of specificization of an address cell structure.
FIG. 16 is a diagram showing a modification of the display electrode shape.
FIG. 17 is a diagram showing a configuration of a display device according to a second embodiment.
FIG. 18 is a diagram showing a cell structure of a plasma display panel.
FIG. 19 is a schematic diagram of an electrode arrangement.
20 is a diagram showing drive voltage waveforms in even fields in Example 5. FIG.
FIG. 21 is a diagram illustrating an order of scanning in an even field according to the fifth embodiment.
22 is a diagram showing drive voltage waveforms in an odd field in Example 6. FIG.
FIG. 23 is a diagram showing drive voltage waveforms in odd-numbered fields in Example 7.
24 is a diagram showing drive voltage waveforms in even fields in Example 8. FIG.
FIG. 25 is a diagram showing drive voltage waveforms in even-numbered fields in Example 9.
FIG. 26 is a diagram showing a modification of the display electrode shape.
[Explanation of symbols]
1, 2 Plasma display panel
100,200 display device
70, 80 drive unit (drive circuit)
51,52 screen
60, 62 cells
U1, U2 emission units
X, Y display electrode
Xb display electrode (first electrode)
Yb display electrode (second electrode)

Claims (10)

A method for driving an AC type plasma display panel having a screen in which a plurality of display electrodes defining a matrix display row and constituting a pair of electrodes for display discharge and a plurality of address electrodes defining a column are arranged There,
A matrix display in which a set of two cells is a light emission unit,
A grouping in which a plurality of cells constituting the screen are arranged in a column direction and two adjacent cells are grouped into one set,
By causing a discharge between the display electrode and the address electrode in one of the cell to be lit and the other cell, the wall charge amount of the cell to be lit is made larger than the wall charge amount of the other cell. Partial addressing for performing operations only on one cell in each of the plurality of sets;
Transfer preparation for causing discharge between display electrodes only in the cells to be lit among the address cells to be partially addressed, thereby making the wall charge amount of the display electrode pairs equal,
Among the address cells, the cells to be lit and the cells paired with each of these cells cause a discharge between the display electrodes, whereby the wall charge amount of all the cells to be lit in the screen is changed to other cells. Transfer more than the wall charge of
Lighting maintenance that causes display discharge of the number of times according to the brightness to be displayed in all the cells to be lit in the screen,
A method for driving a plasma display panel, which is realized by performing the steps. In the transfer, a sustain voltage lower than the discharge start voltage is applied between the display electrodes of the address cells, and a voltage lower than the discharge start voltage and higher than the sustain voltage is applied between the display electrodes of cells other than the address cells. The method for driving a plasma display panel according to claim 1. Divide the frame into two fields
The grouping is performed for each field so that the position of the light emitting unit is shifted by one cell in the column direction between the fields,
The method of driving a plasma display panel according to claim 1, wherein the addressing, the transfer preparation, the transfer, and the lighting maintenance are performed in at least one field. In both of the two fields, the addressing, the transfer preparation, the transfer, and the lighting maintenance are performed,
4. The method of driving a plasma display panel according to claim 3, wherein all address cells in the display of one of the two fields are address cells in the display of the other field. A method for driving an AC type plasma display panel having a screen in which a plurality of display electrodes defining a matrix display row and constituting a pair of electrodes for display discharge and a plurality of address electrodes defining a column are arranged There,
A matrix display in which a set of two cells is a light emission unit,
For each of all the cells, an electrode distinction for classifying the display electrode into a first electrode and a second electrode so that the electrode positional relationship in the column direction is opposite to the cell adjacent in the column direction;
Two-electrode simultaneous scanning that repeats an operation of temporarily biasing two adjacent second electrodes at a common timing with at least one first electrode interposed between them, and switching the bias target; and Addressing to increase the wall charge amount of all cells to be lit in the screen more than the wall charge amount of other cells by potential control according to display data for the address electrode;
Lighting maintenance that causes display discharge of the number of times according to the brightness to be displayed in all the cells to be lit in the screen,
A method for driving a plasma display panel, which is realized by performing the steps. Dividing the two-electrode simultaneous scanning into the first half and the second half,
In the first half and the second half, the second electrode corresponding to the light emitting units having an odd number in the column direction is set as the bias target, and on the other hand, the second electrode corresponding to the light emitting units having the even number in the column direction is set as the bias target.
6. The plasma display according to claim 5, wherein voltages applied between the first electrode and the second electrode in the second half and between the address electrode and the second electrode are set higher than voltages applied between the corresponding electrodes in the first half. Panel drive method. A display device comprising an AC type plasma display panel and a drive circuit for driving the plasma display panel,
The plasma display panel has a screen in which a plurality of display electrodes defining a matrix display row and constituting an electrode pair for display discharge and a plurality of address electrodes defining a column are arranged,
A plurality of cells constituting the screen form a set of a plurality of sets in which two adjacent cells arranged in the column direction are set as one set,
In order to realize a matrix display using a set of two cells as a light emission unit, the drive circuit
By causing a discharge between the display electrode and the address electrode in one of the cell to be lit and the other cell, the wall charge amount of the cell to be lit is made larger than the wall charge amount of the other cell. Partial addressing for performing operations only on one cell in each of the plurality of sets;
Transfer preparation for causing discharge between display electrodes only in the cells to be lit among the address cells to be partially addressed, thereby making the wall charge amount of the display electrode pairs equal,
Among the address cells, the cells to be lit and the cells paired with each of these cells cause a discharge between the display electrodes, whereby the wall charge amount of all the cells to be lit in the screen is changed to other cells. Transfer more than the wall charge of
A display device characterized by performing lighting maintenance that causes display discharge of the number of times corresponding to the brightness to be displayed in all the cells to be lit in the screen. The display device according to claim 7, wherein the plurality of display electrodes are arranged so as to provide an electrode gap at a boundary between cells arranged in a column direction. A display device comprising an AC type plasma display panel and a drive circuit for driving the plasma display panel,
The plasma display panel has a screen in which a plurality of display electrodes defining a matrix display row and constituting an electrode pair for display discharge and a plurality of address electrodes defining a column are arranged,
The plurality of display electrodes form a set of first and second electrodes arranged so that the electrode positional relationship in the column direction is reversed with respect to each cell in the column direction for each of all cells,
In order to realize a matrix display using a set of two cells as a light emission unit, the drive circuit
Two-electrode simultaneous scanning that repeats an operation of temporarily biasing two adjacent second electrodes at a common timing with at least one first electrode interposed between them, and switching the bias target; and Addressing to increase the wall charge amount of all cells to be lit in the screen more than the wall charge amount of other cells by potential control according to display data for the address electrode;
A display device characterized by performing lighting maintenance that causes display discharge of the number of times corresponding to the brightness to be displayed in all the cells to be lit in the screen. The plasma display panel has a mesh-like discharge barrier that partitions the screen into cells.
The plurality of display electrodes are arranged at a constant pitch so as to form a discharge gap for display discharge for each cell,
The number of display electrodes is the number of cells in the column direction on the screen plus one,
The display device according to claim 9, wherein each of the plurality of display electrodes is patterned so as to provide an electrode gap at a boundary between cells arranged in a column direction.

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