JP2005004605A - Simulation device and simulation method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To easily and speedily specify a test pattern to be used for re-simulation with respect to a signal required the re-simulation after performing simulation. <P>SOLUTION: The simulation device comprises: a simulation execution section 1021 executing the simulation by using a net list obtained from a net list acquisition section 101 and the test pattern obtained from an input section 105; an information addition section 1022 adding test pattern-associating information for associating a pattern actuated each signal in the course of the simulation with the each signal to the net list to form an information-added net list; a test pattern specifying section 106 referring to the information-added net list when the re-simulation is instructed, and specifies the test pattern associated with the signal instructed the re-simulation based on the test pattern-associating information. The simulation execution section 1021 then conducts the re-simulation by using the test pattern specified by the test pattern specifying section 106. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a technique for specifying a verification pattern operating on a signal in a netlist.
[0002]
[Prior art]
FIG. 9 explains the flow of the result display device disclosed in Japanese Patent Laid-Open No. 8-272845.
In the figure, 810 is a logic synthesis tool, 812 is a net list of logic circuits created by logic synthesis, 814 is an analysis tool, 816 is error information output from the analysis tool, 818 is circuit diagram creation means, and 820 is a circuit diagram. A logic circuit diagram 822 created by the creating unit 818 is an error display unit for displaying an error.
[0003]
Next, the operation will be described.
This result display device creates a logic circuit diagram 820 by the circuit diagram creation means 818 from the net list 812 of the logic circuit created by the logic synthesis tool, and further displays error information on the logic circuit diagram by the error display means 822. To display.
However, this conventional technique cannot specify a pattern that can be used for operation confirmation when analysis of a designated signal is required.
As a method for identifying a pattern that can be used for analysis of a specified internal signal, generally, simulation is performed using several patterns that are roughly targeted based on verification specifications and design data. Or, it has been necessary to refer to a test pattern and a design information file other than the net, for example, by identifying the operation node information. Therefore, if someone other than the person who directly performed the verification work needs to analyze it later, it was impossible to obtain the information that they wanted to know. There was a problem such as taking time and work.
[0004]
[Patent Document 1]
JP-A-8-272845
[0005]
[Problems to be solved by the invention]
In this way, when using the conventional result display device, in order to identify the pattern for confirming the operation of the specified signal, it is necessary to examine the data or perform a simulation to examine the result. There was a problem that it took time.
[0006]
In the present invention, in order to solve such a problem, when re-simulation of any signal becomes necessary after the simulation is performed, a test pattern to be used for re-simulation of the signal. One of the objects is to provide an apparatus and a method capable of easily specifying the above in a short time.
[0007]
[Means for Solving the Problems]
The simulation apparatus according to the present invention is
A netlist acquisition unit for acquiring a netlist created by logic synthesis;
A simulation execution unit for executing a predetermined simulation using at least one test pattern for each of at least one or more signals included in the netlist;
And an information adding unit for adding test pattern association information for associating the test pattern in which each signal is operated in the simulation by the simulation execution unit to each signal to the net list.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a design flow chart showing an operation pattern specifying procedure when the simulation apparatus according to the present embodiment is used.
In the figure, S101 is a logic synthesis that creates and outputs circuit connection information (netlist) from function description information, S102 is a netlist, S103 is a functional simulation and timing simulation for verifying the netlist, and a simulation for signals This is a simulation for adding test pattern association information from the result of the above and a test pattern association information addition process. S104 is an information-added netlist to which test pattern association information for associating a test pattern operating with a signal in the simulation and test pattern association information addition processing of S103 is added. Data release and design data check on the manufacturer side, S106 is used for analysis of the signal requested to confirm the operation by the design data check on the LSI manufacturer side, and S107 is used for analysis on the signal requested to operate from the LSI manufacturer side. A test pattern specifying process for specifying a test pattern, S108 is a re-simulation using the test pattern specified in the test pattern specifying process in S107, and S109 is an operation analysis operation for the signal specified in S106.
In the simulation and test pattern association information addition processing in S103, a simulation is performed on signals included in the netlist using a predetermined test pattern, and a test pattern in which each signal is operated is associated with each signal based on the result of the simulation. Is added to the netlist.
In the test pattern specifying process in S107, the test pattern used for analyzing the signal specified in S106 is specified with reference to the information addition netlist to which the test pattern association information is added.
The simulation apparatus according to the present embodiment performs a simulation and test pattern association information addition process in S103, a test pattern identification process in S107, and a re-simulation process in S108.
[0009]
Next, a configuration example of the simulation apparatus 1 according to the present embodiment will be described with reference to FIG.
The net list acquisition unit 101 acquires a net list created by logic synthesis.
The simulation unit 102 performs a predetermined simulation on the net list acquired by the net list acquisition unit 101. The simulation unit 102 includes a simulation execution unit 1021, an information addition unit 1022, and an information storage / acquisition unit 1023.
The simulation execution unit 1021 executes functional simulation and timing simulation for the netlist.
The information adding unit 1022 adds test pattern association information for associating each pattern with a test pattern in which each signal operates according to the simulation result of the simulation executing unit 1021 to the net list.
The information storage / acquisition unit 1023 stores the information addition netlist to which the test pattern association information is added by the information addition unit 1022 in the information addition netlist storage unit 104. Further, after the simulation by the simulation execution unit 1021 is completed, the test pattern used for the simulation is stored in the test pattern storage unit 103, and when re-simulation is performed in the simulation execution unit 1021, the test pattern specifying unit 106 The specified test pattern is acquired from the test pattern storage unit 103.
[0010]
The test pattern storage unit 103 stores the test pattern used for the simulation of the simulation execution unit 1021.
The information addition netlist storage unit 104 stores the information addition netlist to which the test pattern association information is added by the information addition unit 1022.
The input unit 105 inputs simulation instruction information for instructing the simulation execution unit 1021 to perform simulation and resimulation instruction information for instructing the simulation execution unit 1021 to perform re-simulation from the operator. The simulation instruction information includes a test pattern used for simulation in the simulation execution unit 1021, and the re-simulation instruction information includes a signal name to be re-simulated.
When the re-simulation instruction information is input, the test pattern specifying unit 106 acquires the information-added net list from the information-added net list storage unit 104, and is designated by the re-simulation instruction information with reference to the information-added net list. The test pattern associated with the signal is specified, and the signal name specified by the specified test pattern and re-simulation instruction information is notified to the simulation unit 102.
The output unit 107 outputs the information addition net list from the simulation unit 102 to the operator, and outputs a re-simulation result to the operator when the simulation unit 102 performs re-simulation.
[0011]
Although not shown, the simulation apparatus 1 can be realized by a computer having a CPU such as a microprocessor, a semiconductor memory, or a recording unit such as a magnetic disk. In the recording means, a program that realizes the function of each component included in the simulation apparatus 1 is recorded, and the CPU reads the program to control the operation of the simulation apparatus 1 and to control the function of each component. Can be realized.
[0012]
Next, the operation of the simulation apparatus 1 according to the first embodiment will be described.
First, the netlist acquisition unit 101 acquires (inputs) a netlist from logic synthesis.
As shown in FIG. 3, the net list includes signal names and logic gate connections as information.
Taking the row 202 in FIG. 3 as an example, AND2 is the logic cell from the left, the next A01 is the specific information for each cell, the inside of the next parenthesis is the connection information between the logic cell and the terminal, and the signal N0001 from the left to the terminal Y Are connected, the signal N0011 is connected to the terminal A, and the signal N0012 is connected to the terminal B.
[0013]
In parallel with the netlist acquisition by the netlist acquisition unit 101, the input unit 105 inputs simulation instruction information from the operator, and the simulation execution unit 1021 of the simulation unit 102 inputs the netlist from the netlist acquisition unit 101. Based on the test pattern from the unit 105, verification (timing, function verification) by simulation is performed. This corresponds to S103 in the flow of FIG.
For the signal operating in the simulation by the simulation execution unit 1021, the information adding unit 1022 adds test pattern association information for associating the test pattern in which each signal operates with each signal to the net list. As a means for adding, as soon as the signal operating in the simulation is checked, the test pattern association information may be added to the net list, or the operation signal information is output to a file once, and the net list is output from the file. Alternatively, the test pattern association information may be added to the net list.
[0014]
An example of an information addition net list to which test pattern association information is added by the information addition unit 1022 is shown in FIG.
In the row 302 in FIG. 4, the test pattern identification information is added as the test pattern association information such that the signal N0012 is N0012_TP1. That is, it can be seen from the test pattern identification information that the signal N0012 is operated with the test pattern TP1 in the simulation. When N0012 is operating even with another test pattern (for example, a test pattern with identification information TP3), the test pattern identification information is sequentially added to N0012_TP1_TP3.
When the simulation by the simulation execution unit 1021 is completed and the test pattern association information is added to the net list by the information addition unit 1022, the information storage / acquisition unit 1023 displays the information addition net list to which the test pattern association information is added. The test pattern stored in the additional netlist storage unit 104 and used for the simulation in the simulation execution unit 1021 is stored in the test pattern storage unit 103.
Further, the information addition net list is output from the simulation unit 102 to the output unit 107, and the information addition net list is output from the output unit 107 to the operator.
[0015]
After the information addition netlist is output, the design data is released to the LSI manufacturer as shown in S105 of FIG. The LSI manufacturer that obtained the design data uses the detailed delay information to perform timing simulation and technology-dependent checks. As a result of this check, there may be a signal that requires the design side to analyze the operation (re-simulation).
In the analysis, there are a case where a test pattern and a signal name are communicated from an LSI manufacturer, and a case where only a signal name is communicated. When only the signal name is notified, the test pattern in which the designated signal is operating must be specified. In the following description, it is assumed that only the signal name is notified from the LSI manufacturer.
[0016]
When an LSI manufacturer requests re-simulation, the input unit 105 inputs re-simulation instruction information including the requested signal name from the operator and outputs it to the test pattern specifying unit 106. Note that the signal for which re-simulation is instructed by the re-simulation instruction information is a signal that has already been simulated by the simulation execution unit 1021.
The test pattern specifying unit 106 that has input the re-simulation instruction information acquires the information-added net list corresponding to the signal name included in the re-simulation instruction information from the information-added net list storage unit 104, and stores the information-added net list in the acquired information-added net list. The test pattern associated with the signal is specified from the added test pattern association information. As shown in FIG. 4, test pattern identification information is added to each signal, such as N0012_TP1, in the information addition netlist. This makes it possible to understand only from the net name which node is running this pattern.
When the test pattern is specified by the test pattern specifying unit 106, the information storage / acquisition unit 1023 acquires the test pattern specified by the test pattern specifying unit 106 from the test pattern storage unit 103, and the information addition netlist Is acquired from the information addition netlist storage unit 104, and the simulation execution unit 1021 uses these test patterns and the information addition netlist to re-simulate a signal for which re-simulation is instructed, and outputs a re-simulation result. Output from 107.
Thereby, it is possible to proceed to the signal analysis work shown in S109 of FIG.
[0017]
As described above, according to the present embodiment, the information of the operating pattern is added to the internal signal of the netlist to identify it, so that the pattern in which the designated signal is operating is specified. Can be done easily and in a short period of time, and it is possible to save the trouble of simulating the pattern by estimation and viewing the result, thereby improving the efficiency of the logic design.
[0018]
Embodiment 2. FIG.
In the first embodiment, the test pattern identification information is added as the test pattern association information to be added to the net list. However, in this embodiment, different types of test pattern association information are added to the net list. .
In this embodiment, the design flow procedure is the same as that shown in FIG. 1, and the configuration of the simulation apparatus 1 according to this embodiment is the same as that shown in FIG.
In the present embodiment, only the format of the test pattern association information added to the net list in the information adding unit 1022 and the method of specifying the test pattern in the test pattern specifying unit 106 are different, and other operations are the same as those in the first embodiment. This is the same as described in.
[0019]
In the first embodiment, the identification information of the test pattern operating for each signal is added as the test pattern association information. However, in this embodiment, the identification information of the test pattern is not the identification information itself but a predetermined pattern. Correspondence information for associating ID information and ID information with test pattern identification information is added.
An example of an information addition net list by the information addition unit 1022 of this embodiment is shown in FIG.
In the line 402 in FIG. 5, ID03 is added to the signal N0012 as ID information to form N0012_ID03, and the association information is added to the line 404 in FIG. In the example of FIG. 5, the association information is added in the form of a comment. The leftmost part indicates ID03 which is ID information, and TP01 and TP03 which are identification information of test patterns actually operated with respect to ID03 are included. Indicated. Note that the association information is in the form of a comment in the netlist file, so that it is handled as an outside processing target by various CAD tools.
As a method of adding information in the information adding unit 1022, each signal is watched at the time of simulation, ID information is added to each signal at the end of the simulation, and association information is added as a comment.
The ID information and the association information are information that can specify a plurality of test patterns in a lump, and correspond to an example of the lump identification information.
[0020]
On the other hand, when the re-simulation instruction information is input, the test pattern specifying unit 106 acquires the information-added net list in the format shown in FIG. 5 from the information-added net list storage unit 104, and the signal for which re-simulation is instructed In addition to grasping the ID information, the test pattern identification information is derived based on the association information of the ID information, and the test pattern used for the re-simulation is specified.
The subsequent steps are the same as in the first embodiment, and the information storage / acquisition unit 1023 acquires the test pattern specified by the test pattern specifying unit 106 from the test pattern storage unit 103, and the information addition netlist is the information addition netlist storage unit. 104, the simulation execution unit 1021 performs re-simulation on the signal for which re-simulation is instructed using these test patterns and the information addition netlist, and outputs the re-simulation result from the output unit 107.
[0021]
As described above, according to the present embodiment, the information of the operating pattern is added to the internal signal in the net list file to identify it, so that the designated signal is operating. It is easy to specify the pattern, and it is possible to save the trouble of simulating the pattern by estimation and viewing the result. Furthermore, in the first embodiment, for a signal operating in many patterns, the signal name may become long by adding identification information of many test patterns. However, according to the present embodiment, the signal name Can be avoided, and the signal name is not obfuscated.
[0022]
Embodiment 3 FIG.
In the first embodiment, only test pattern identification information (test pattern association information) is added to the netlist. However, in the present embodiment, the number of signal value changes indicating the number of times the signal value has changed for each signal. The information is added to the netlist together with the test pattern identification information.
In this embodiment, the design flow procedure is the same as that shown in FIG. 1, and the configuration of the simulation apparatus 1 according to this embodiment is the same as that shown in FIG.
In the present embodiment, only the contents of information added to the net list in the information adding unit 1022 are different, and other operations are the same as those described in the first embodiment.
[0023]
The information adding unit 1022 in the present embodiment adds signal value change count information together with test pattern identification information to the net list for each signal.
That is, the information adding unit 1022 adds, for each signal, information on the number of times the signal value changes from 0 → 1 → 0 or 1 → 0 → 1 along with the identification information of the operating test pattern.
As a method of adding information in the information adding unit 1022, the number of signal value changes is also watched each time a simulation is performed for each test pattern, and the information is already added to each signal name every time the simulation for each test pattern is completed. Check the signal value change count, and if the measured signal value change count exceeds the already added signal value change count, add and update the test pattern identification information and signal value change count to the signal name. To do.
[0024]
An example of the information addition net list by the information addition unit 1022 of this embodiment is shown in FIG.
In the row 502 in FIG. 6, TP01 is added as the test pattern identification information to the signal N0012, and $ 05 is added as the signal value change value count information to form N0012_TP01 $ 05. This is an example expressing that the signal N0012 is operated five times (the signal value is changed five times) in the test pattern TP01.
Further, a simulation is performed with another pattern, and if N0012 is operating more, the update is performed. FIG. 7 shows an update example. Assuming that the N0012 signal is operated seven times by the test pattern TP03, the row 602 is updated to N0012_TP03 $ 07.
[0025]
When the re-simulation instruction information is input, as in the first embodiment, the test pattern specifying unit 106 acquires the information-added netlist in the format shown in FIG. Based on the test pattern association information shown in the netlist, a test pattern used for re-simulation is specified for a signal for which re-simulation is instructed.
Further, the information storage / acquisition unit 1023 acquires the test pattern specified by the test pattern specifying unit 106 from the test pattern storage unit 103, acquires the information addition netlist from the information addition netlist storage unit 104, and executes the simulation execution unit 1021. However, using these test patterns and the information addition netlist, re-simulation is performed on the signal for which re-simulation is instructed, and the re-simulation result is output from the output unit 107.
[0026]
As described above, according to the present embodiment, the information of the pattern that is operating and the number of operations in that pattern are added to the internal signal in the net list file to identify it. It is possible to easily identify the pattern in which the signal is operating. Therefore, it is possible to save the trouble of simulating the pattern by guessing and viewing the result. Further, in this embodiment, signal value change count information is also included. A signal with a large number of signal value changes moves the signal more frequently and is suitable for analysis, so that a pattern can be selected for efficient operation analysis.
[0027]
Embodiment 4 FIG.
In the present embodiment, a method in which the second embodiment and the third embodiment are combined will be described.
In this embodiment, the design flow procedure is the same as that shown in FIG. 1, and the configuration of the simulation apparatus 1 according to this embodiment is the same as that shown in FIG.
In the present embodiment, only the contents of information added to the net list in the information adding unit 1022 and the test pattern specifying method in the test pattern specifying unit 106 are different, and other operations are described in the first embodiment. Is the same.
[0028]
The information adding unit 1022 in the present embodiment adds information to the net list by a method combining the second embodiment and the third embodiment. Specifically, the information adding unit 1022 adds ID information to each signal as described in Embodiment 2, and adds association information as a comment. This association information associates ID information with test pattern identification information and signal change value count information in the test pattern.
That is, the number of times that the value of the signal has changed from 0 to 1 to 0 or from 1 to 0 to 1 is added together with the identification information of the test pattern operating on the signal.
[0029]
An example of an information addition net list by the information addition unit 1022 of this embodiment is shown in FIG.
In the signal N0012 in the row 702 in FIG. 8, the ID information is ID03. The line 704 in FIG. 8 is a line added as a comment. The leftmost part indicates ID03 which is ID information, and TP01 and TP03 which are identification information of test patterns actually operated on ID03 are respectively shown. Are displayed together with $ 05 and $ 07, which are the number of signal value changes, and in the form of TP01 $ 05 and TP03 $ 07.
[0030]
The operation of the test pattern specifying unit 106 when the re-simulation instruction information is input is the same as that of the second embodiment, and an information-added netlist in the format shown in FIG. 8 is acquired from the information-added netlist storage unit 104. ID information is grasped for a signal for which re-simulation is instructed, and test pattern identification information is derived based on the association information of the ID information, and a test pattern used for re-simulation is specified.
Here, for example, when a re-simulation is instructed for a signal in which a plurality of test patterns are associated, such as a signal N0012 indicated by 702 in FIG. 8, the information adding unit 1022 is associated. Although all test patterns may be specified as test patterns used for re-simulation, a predetermined number (for example, one) of test patterns is selected as a representative example from a plurality of test patterns based on signal value change frequency information. May be. A test pattern with a large number of signal value changes is considered to be a test pattern suitable for the analysis of the signal, so if there are multiple test patterns associated with it, a test pattern with a large number of signal value changes can be re-simulated. You may specify as a typical test pattern which should be used.
The subsequent steps are the same as in the first embodiment, and the information storage / acquisition unit 1023 acquires the test pattern specified by the test pattern specifying unit 106 from the test pattern storage unit 103, and the information addition netlist is the information addition netlist storage unit. 104, the simulation execution unit 1021 performs re-simulation on the signal for which re-simulation is instructed using these test patterns and the information addition netlist, and outputs the re-simulation result from the output unit 107.
[0031]
As described above, according to the present embodiment, information on the pattern operating in the net list file and the number of signal value changes in the pattern are added and identified. As a result, the pattern in which the designated signal is operating can be easily identified. Therefore, it is possible to save the trouble of simulating the pattern by guessing and viewing the result. Furthermore, the information on the number of operations is included as compared with the first embodiment, and the change of the signal name portion is reduced as in the third embodiment so that the signal name is not confused.
[0032]
Further, according to the present embodiment, when there are a plurality of test patterns associated with a signal for which re-simulation is instructed, a representative suitable for analysis is selected from the plurality of test patterns based on the signal value change count information. Specific test patterns can be specified, and signal analysis can be performed efficiently.
[0033]
【The invention's effect】
According to the present invention, since test pattern association information is added to the net list for each signal, even when re-simulation is required for any signal, a test pattern to be used for re-simulation can be easily and quickly. Can be specified.
[Brief description of the drawings]
FIG. 1 is a diagram showing a design flow when a simulation apparatus according to Embodiments 1 to 4 is used.
FIG. 2 is a diagram illustrating a configuration example of a simulation apparatus according to the first to fourth embodiments.
FIG. 3 is a diagram showing an example of a net list before adding information.
FIG. 4 is a diagram showing an example of an information addition net list according to the first embodiment.
FIG. 5 is a diagram showing an example of an information addition net list according to the second embodiment.
6 is a diagram showing an example of an information addition net list according to Embodiment 3. FIG.
7 shows an example of an information addition net list according to Embodiment 3. FIG.
FIG. 8 is a diagram showing an example of an information addition net list according to the fourth embodiment.
FIG. 9 is a diagram illustrating a conventional technique.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 Simulation apparatus, 101 Net list acquisition part, 102 Simulation part, 103 Test pattern memory | storage part, 104 Information addition net list memory | storage part, 105 Input part, 106 Test pattern specification part, 107 Output part, 1021 Simulation execution part, 1022 Information addition Part, 1023 information storage / acquisition part.

Claims (8)

A netlist acquisition unit for acquiring a netlist created by logic synthesis;
A simulation execution unit for executing a predetermined simulation using at least one test pattern for each of at least one or more signals included in the netlist;
A simulation apparatus, comprising: an information addition unit that adds test pattern association information for associating a test pattern in which each signal is operated in a simulation by the simulation execution unit to each signal to a net list. The simulation apparatus further includes:
An input unit for inputting re-simulation instruction information for instructing re-simulation for any signal for which simulation has been executed by the simulation execution unit;
Based on the test pattern association information added to the net list by the information addition unit, a test pattern identification unit that identifies a test pattern associated with a signal for which re-simulation is instructed by re-simulation instruction information,
The simulation execution unit
The simulation apparatus according to claim 1, wherein re-simulation is performed on a signal for which re-simulation is instructed by re-simulation instruction information, using the test pattern specified by the test pattern specifying unit. The information adding unit includes:
The simulation apparatus according to claim 1, wherein identification information of the operated test pattern is added to the net list for each signal as the test pattern association information. The information adding unit includes:
The simulation apparatus according to claim 1, wherein as the test pattern association information, collective identification information capable of collectively identifying a plurality of operated test patterns is added to the net list for each signal. The information adding unit includes:
The signal value change frequency information indicating the number of times the signal value of each signal has changed in the simulation by the simulation execution unit is added to the netlist together with the test pattern association information for each signal. Simulation equipment. The simulation apparatus further includes:
An input unit for inputting re-simulation instruction information for instructing re-simulation for any signal for which simulation has been executed by the simulation execution unit;
Test pattern specification for specifying a test pattern to be used for re-simulation for a signal for which re-simulation is instructed by re-simulation instruction information based on the test pattern association information and signal value change count information added to the net list by the information adding unit And
The simulation execution unit
6. The simulation apparatus according to claim 5, wherein re-simulation is performed on a signal for which re-simulation is instructed by re-simulation instruction information, using the test pattern specified by the test pattern specifying unit. A netlist acquisition step of acquiring a netlist created by logic synthesis;
A simulation execution step of executing a predetermined simulation using at least one test pattern for each of at least one or more signals included in the netlist;
A simulation method comprising: an information addition step of adding test pattern association information for associating a test pattern in which each signal is operated in the simulation by the simulation execution step to each signal to a net list. The simulation method further includes:
An input step for inputting re-simulation instruction information for instructing re-simulation for any signal for which simulation has been executed by the simulation execution step;
A test pattern specifying step for specifying a test pattern associated with a signal for which re-simulation is instructed by re-simulation instruction information based on the test pattern association information added to the netlist by the information adding step;
The simulation execution step includes:
The simulation method according to claim 7, wherein re-simulation is performed on a signal for which re-simulation is instructed by re-simulation instruction information, using the test pattern specified in the test pattern specifying step.

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