JP2004527036A - Design verification method and device for complex IC without logic simulation - Google Patents

Abstract

A verification method and apparatus for designing a complex IC by using an event tester and a field programmable gate array (FPGA) or a combination of an event tester and an emulator board. This design verification method eliminates the need for a logic simulation process that is a bottleneck for current IC design verification. By removing this slow simulation from the design verification process, a wide range of design verification can be performed prior to manufacturing the designed IC. In addition, since such a wide range of design verification can be performed, it is not necessary to create a prototype required before mass production.

Description

【Technical field】
[0001]
The present invention relates to a method and apparatus for verifying the design of a complex IC. In particular, the present invention relates to a method and apparatus for quickly, accurately, and cost-effectively verifying the design of a complex IC such as a system-on-chip (SOC) using an event-based test system without using a logic simulation technique.
[Background Art]
[0002]
The current design of a semiconductor integrated circuit (IC) such as VSLI is referred to as Verilog or VHDL in a hardware design environment using a computer generally called EDA (Electronic Design Automation). This is performed using a hardware description language (HDL). Hardware design is performed for each block or sub-block, and the design is verified by a simulator (Verilog / VHDL simulator) at a behavioral level, a gate level, or the like. Such a simulation aims at verifying that the function intended by the designer is performed before the hardware design is created as a silicon IC. However, at present, the hardware design has been only partially verified because the speed of the simulator for simulating the entire chip is too slow.
[0003]
Verification of the design is the most important and difficult task in the design of a complex IC, since a design error cannot be found and eliminated without a full functional verification. At the same time, design verification of the entire chip is indispensable in the product development and production cycle. However, due to the slow simulation speed and the large size of today's IC designs, it is almost impossible to verify the entire chip design using current verification tools and methods (M. Keating and P. Bricaud, "Reuse methodology manual for system-on-a-chip design", Kluwer Academic Publishers, 0-7923-8175-0, 1998; R. Rajsuman, "System-on-a-chip: Design and Test ", Artech House Publishers Inc., ISBN 1-58053-107-5, 2000).
[0004]
Design verification is one of the most important tasks in any system design project, such as the above-mentioned system-on-chip design project (Rajsuman, "System-on-a-chip: Design and Test", 2000, supra). ). Design verification is to confirm that a system performs an intended operation, and to give reliability to the system operation. Verification of the design of a complex IC refers to verifying the operation of the IC hardware for both function and timing performance. It is achieved in today's technology using a wide range of behavioral simulation, logic and timing simulations, as well as emulation or hardware prototypes.
[0005]
In the initial stage of the IC design process, together with development of design specifications and RTL (register transfer level) coding, a behavioral model is created to form a test bench for system simulation. Generally, in the initial stage of design, the purpose is to develop effective test items and test environments for blocks before an RTL model or a functional model is specified. Efficient design verification depends on test quality, test bench integrity, various model abstraction levels, EDA tools, and simulation environment.
The design verification method follows the design hierarchy. First, it is individually verified that the design of the end-level block is correct. Once the function of these blocks has been verified, the correct interface between these blocks is verified for the signal processing type and data content.
[0006]
The most important next step is to run the application software or equivalent test bench on the full chip model to verify the entire chip. The execution of application software can be verified only by activating the full-chip software in real time, so co-simulation with hardware and software is required. Co-simulation can be performed using an instruction set architecture (ISA) model, a bus functional model (BFM), or a behavioral C / C ++ model. Other technologies used today besides co-simulation are emulation or hardware prototypes (C. Flynn, "Developing an emulation environment", Integrated System Design Magazine, pp. 46-52, April 2001; A Dieckman, "HW-SW co-verification with emulation, co-simulation and FPGA based prototyping", Proceedings of Design and Test in Europe, pp. 98-101, 2001; prototypes-A case study ", Proceedings of Design and Test in Europe, pp.109-113, 2001).
[0007]
Emulation systems are very expensive (costs on the order of $ 1 million), but their speed is much faster than that of co-simulation (roughly 100K to 1M cycles / sec). Simulation speeds at different levels of the design description are shown in comparison in FIG. Here, as described above, BFM is referred to as a bus functional model, ISA is referred to as an instruction set architecture, and RTL is referred to as a register transfer level. The logic shown in FIG. 1 means a gate level used for a netlist. None of the existing verification tools or methods can drive software applications extensively for design verification. Therefore, only the functionality of the limited chip is verified.
[0008]
Even if the engineers perform optimal design verification, the first silicon product will operate normally only about 80% of its functions at wafer level test, and 50% at the test incorporated into the intended system. More than a percentage will fail. The fundamental reason for this is the lack of sufficient real-time application execution in system-level testing. The prototype using FPGA is very troublesome to execute because of using an EDA simulation tool, has a low execution speed, and is still unsuitable for design verification (A. Dieckman, "HW-SW co-verification with emulation"). Procedings of Design and Test in Europe, pp. 98-101, 2001; R. Ulrich et al., "Debugging of FPGA based prototypes-A case study", Proceedings of Design and Test in Europe, pp. 109-113, 2001).
[0009]
Thus, in today's technology, the only means to perform this system level verification is to use silicon prototypes using ASICs. An example of such a current IC product development cycle is shown in FIG. As shown in FIG. 2, when the initial design is completed, a silicon prototype is created. This silicon prototype is used to form a system board for complete functional verification (in-system test). For this prototype chip, debug any errors in its operation, modify the design, and finally mass produce the IC.
[0010]
Specifically, in FIG. 2, the designer considers the requirements for designing a complex IC to be designed (step 21). The designer determines the specifications of the IC design based on the necessary items (step 22). In the design input process of step 23, blocks and sub-blocks of the target IC are described using a hardware description language such as Verilog / VHDL. The initial design thus obtained is evaluated by executing an initial test bench 28, generally through a design verification process 25 by a logic / timing simulation 26 (step 24). As a result of performing the logic simulation, an input / output data file, that is, a VCD (value change dump) file 29 is formed. The data included in the VCD file 29 is a list in which the input / output events are described in relation to the time length, that is, the delay time, and is thus event format data.
[0011]
Based on the design data created as described above, a silicon prototype is formed in a process indicated by numeral 30. In this process 30, in step 31, a silicon prototype 33 is created. The obtained silicon prototype 33 is independently verified for error detection (silicon verification 32, characteristic test 35). In the current technology, such a single verification of the silicon prototype 33 is performed by an IC tester. The current IC tester is a cycle-based test system, and has an architecture for generating test vectors using test pattern data formed in a cycle format.
[0012]
The cycle-based test system cannot directly use the VCD file 29 formed under the EDA environment because the file data is in the event format. Therefore, the test vectors in the VCD file are converted into cycle format data by cyclization (vector cycling) 34. Further, it is necessary to create a test program for the IC tester based on the data in the cycle format. This is because a test vector in the event format cannot be completely converted into a test vector in the cycle format. Silicon prototype design verification with such current IC testers may still yield incomplete and inaccurate results. Also, it takes time to convert event-format data created in an EDA environment to cycle-format so as to match a cycle-based test system.
[0013]
In the design verification / debug process 40, the silicon prototype 33 is further verified by performing an in-system test 37. In the in-system test 37, the silicon prototype 33 is mounted on a circuit board as a part of the intended system, and the operation of the entire system is verified. By this in-system verification, a system error is detected and the cause of the error is pursued, and a design bug is corrected (step 39). Such an in-system test requires a silicon prototype for the designed chip, and requires software, a board, and peripheral hardware for driving the prototype. There is a problem that it takes a long time.
[0014]
During the silicon prototype stage 30 and the design verification / debug stage 40 of FIG. 2, a lot of mutual cooperation between the design engineer and the test engineer is performed to detect a design error and investigate the cause of the error. Correct design errors. A simulation 43 is executed on the final design 41 that has been reached in this way, using a newly formed test bench 45. Then, a silicon product 49 is created by a manufacturing process based on the design data, and a production test 47 is performed on the silicon product 49.
As shown in FIG. 2, the conventional design verification process is not completely closed loop. In other words, all stages from initial design to silicon prototype production, debug / verification, and final design are sequential in one direction. Therefore, the execution of each of these steps takes a very long time and is expensive. If an error occurs at any stage, a complete redo is necessary.
DISCLOSURE OF THE INVENTION
[Problems to be solved by the invention]
[0015]
In order to improve the above problem, the applicant of the present invention has proposed a verification method based on an event tester in U.S. Patent Application Nos. 09 / 428,746 and 09 / 941,396 owned by the present applicant. In this method, design verification is performed using a silicon prototype and an initial simulation test bench together with various tools in an electronic design automation (EDA) environment in an event type test system (event tester). To realize this, various EDA tools and simulators are linked to an event test system, an initial design simulation vector and a test bench are executed, and the test bench and the test vector are changed by an event tester so as to obtain a desired result. . Since the EDA tool is linked to the event tester, a final test bench can be formed by the changed contents.
An example of this method is shown in the block diagram of FIG. It should be noted that this example method is prior art only to the applicant and is not a publicly disclosed technique or prior art to the present invention. The basic difference between FIG. 2 and FIG. 3 is that all processes from initial design to silicon prototype formation, debug / verification, bug fixing, final manufacturing process or mass production are completely looped by the method of FIG. That is to realize.
[0016]
In the method of the above-mentioned U.S. Patent Application and FIG. 3, in order to perform a complete functional design, that is, a sufficient design verification at a chip level, a full-chip functional test vector formed by a design simulation (initial test bench) is used as an event. Performed by tester. These vectors are in the form of events, and are generally generated by executing a software application on the behavioral model or Verilog / VHDL model of the target IC. These vectors may be performed simultaneously or at different times for different parts of the IC, but the overall behavior of the IC is determined by the integrated response of these parts. After this step, a silicon chip (silicon prototype / prototype) is formed as shown in FIG.
[0017]
When the prototype chip becomes available, the prototype chip is connected to an event test system and a design simulation vector based on an initial test bench is executed to verify the operation of the chip. More specifically, in FIG. 3, the event tester 52 gives the function of the silicon prototype 33 to the silicon prototype 33 a test vector formed based on the event data generated from the VCD (Value Change Dump) file 29. Test. Since the VCD file 29 is configured in the event format, the data of the VCD file 29 can be directly used in the event tester 52.
[0018]
EDA tools, such as simulation, analysis and debug 55 and waveform editor viewer 56, are connected to the event tester 52 through an interface 67 such as an API (Programmed Application Interface). The event tester 52 has software tools for observing and editing a waveform, for example, an event waveform editor viewer 58 and a DUT (device under test) waveform editor viewer 59. These editor viewers 58 and 59 are linked to the EDA tools 55 and 56 via an API interface 67 so that they can communicate with each other and access each other's databases. The event tester 52 can change a test vector (event) via the event waveform editor / viewer 58.
[0019]
By executing the test vector, the event tester 52 forms a test result file 53, and feeds back the result data to the EDA environment and the EDA tool via the test bench feedback 69. The result of executing the test vector is examined in the event tester 52, and the event is changed and edited in the event tester 52 (waveform editor viewers 58 and 59) so that incorrect operation of the IC (intended design) is corrected. . A new test bench 51 is created based on the changed event. To obtain such a new test bench, EDA tools such as a test bench generation tool 65, a simulation analysis tool 55, and a waveform viewer 56 are linked to the event tester 52. When these processes are completed, in FIG. 3, a final IC device 62 is produced by a final silicon production process 61, and the device is tested in a production test 63.
[0020]
The method of FIG. 3 requires a physical silicon chip (prototype) for design verification, and thus the verification process as a whole is still expensive. To remedy this limitation, the aforementioned U.S. patent application Ser. No. 09 / 941,396 describes an alternative process for forming a new bug-free test bench and device model using an initial design data description and its simulation test bench. Is disclosed. Note that this technique is also the applicant's internal knowledge and not the prior art of the present invention. In this process, the initial device design is mounted on the event tester along with the initial test bench. Using an API (Programmed Application Interface), the event tester is linked to the simulator used in the initial design phase. Therefore, the event tester can have test benches for design data described in Verilog or VHDL and all of their logic models, behavioral, BFM, ISA, and applications.
[0021]
Using a device model based on the initial design and its test bench, the design results are verified by an event tester. Since the environment and the verification result of the entire verification system are in the form of an event, any operational errors of the device can be verified immediately. Since the event tester can change and edit the event and change the time scale, the event tester can change and correct the event so as to correct such an operation error. Once all operational errors have been corrected, the corrected device model is saved and a new test bench and test vectors are created. The stored device model is used in a silicon manufacturing process and a mass production process.
However, since the design verification method using this device model is based on a simulation as in the method of FIG. 3, there is a problem that the speed is low. Therefore, in order to improve this problem, a new design verification method and device are required.
[0022]
Accordingly, an object of the present invention is to provide a method and apparatus for performing design verification of a complex IC at high speed and at low cost by using an event type test system without using logic simulation.
[Means for Solving the Problems]
[0023]
In a first aspect of the present invention, a method for verifying the design of a complex IC includes connecting a field programmable gate array (FPGA) to the event tester, and using the design data formed in the EDA environment. Forming an IC equivalent to the IC intended for the FPGA by in-line programming the FPGA, providing a test vector obtained from the IC design data to the FPGA by an event tester, and outputting a response output from the FPGA. Evaluating, detecting an error in the response output, and changing the in-line programming of the FPGA so that the design error is corrected, and detecting and designing the error until the event tester obtains error-free design data. Steps to repeat error correction steps By constructed.
[0024]
Preferably, the method further comprises the step of converting the obtained design data for in-line programming of the FPGA. The step of in-line programming the FPGA via the event tester further includes transmitting programming data to the FPGA via the event tester's control bus.
In the present invention, preferably, the step of applying the test vector to the IC formed on the FPGA includes the step of executing a test bench formed under an EDA environment and the step of executing application software on the intended IC via an event tester. have.
The method of the present invention comprises the steps of extracting event data from a test bench formed in an EDA environment, mounting the extracted event data on an event tester, generating a test vector using the event data, and Applying to the FPGA via the test fixture of the event tester.
[0025]
In the second embodiment of the present invention, an emulator board is used instead of an FPGA. A method for verifying the design of a complex IC according to the present invention includes the steps of connecting an emulator board to an event tester and supplying design data of the intended IC to the emulator board so as to emulate the function of the intended IC by the emulator board. Providing a test vector obtained from IC design data to an emulator board by an event tester, evaluating a response output from the emulator board, and correcting a design error by detecting an error in the response output. Changing the design data supplied to the emulator board, and repeating the steps of error detection and design error correction until error-free design data is obtained in the event tester.
[0026]
Yet another aspect of the present invention is an apparatus for verifying the design of a complex IC. This design verification device is composed of various means for realizing the above-described design verification method, and uses a combination of an event tester and an FPGA or a combination of an event tester and an emulator board to execute a high-speed test pattern application or Perform response evaluation, design debugging and error correction.
【The invention's effect】
[0027]
In the design verification according to the present invention, design verification is performed by using an event tester and in-line programming of an FPGA instead of using a slow EDA tool. Simulations at the whole chip level are not used, and the speed of the application software running on the FPGA is much faster than the simulations, enabling a wide range of verifications impossible with current technology .
Since the slow simulation in the flow of the design verification process has been eliminated, extensive design verification can be performed before the designed IC is manufactured. In addition, since a wide range of design verification has become possible, it is no longer necessary to create prototypes that were required before mass production. As described above, the design verification method of the present invention is very efficient and low cost, and uses a process basically different from the verification method using any conventional system.
BEST MODE FOR CARRYING OUT THE INVENTION
[0028]
Applicants have disclosed event-based test systems in their proprietary U.S. patent applications Ser. Nos. 09 / 406,300, 09 / 340,371 and 09 / 286,226. The new verification method and apparatus according to the present invention changes the design verification paradigm by overcoming the limitations in the prior art.
As is well known, an IC tester (semiconductor test system) has a test rate as fast as 100 MHz to 1 GHz, and is much faster than, for example, any current logic simulator. As described above, the conventional techniques shown in FIGS. 2 and 3 use a logic simulator as a part of the design verification method, and therefore cannot utilize the high test rate of the IC tester. The present invention speeds up the design process itself by removing slow simulations from the design verification process and improves designer productivity.
[0029]
Two major advantages of the present invention are:
(1) By removing the slow simulation process from the design verification process, a wide range of design verification can be performed before manufacturing an IC intended to be performed; and
(2) Since a wide range of design verification has become possible, it is possible to eliminate the need for forming prototypes which were required before mass production.
The design verification method of the present invention is very efficient and low cost, and uses a process that is fundamentally different from any of the conventional design verification methods described above.
[0030]
The present invention performs design verification using an event-type test system (event tester) and an in-line programmed FPGA instead of the slow EDA simulation tool. The basic concept of an event-based test system is disclosed in U.S. patent application Ser. Nos. 09 / 406,300 and 09 / 340,371. The FPGA programs on the event tester via the control bus in the event tester (in-line programming). Thus, one or more FPGAs having a netlist (generally a gate level description) of the intended complex IC chip can be implemented on the event tester.
[0031]
Since the actual IC design is implemented in the FPGA, the software application can be executed via the event tester for the purpose of design verification. Errors that occur during the software application are detected by the event tester and diagnosed directly on the event tester. Since the FPGA is programmed in-line, it is possible to correct the cause of the error that occurs in the netlist of the design data. In this manner, a wide range of design verification can be performed by executing an actual software application for a long time.
This design verification method is shown in FIG. In this example, the event tester 92 connects an FPGA (field programmable gate array) board 94 via a control bus. Similar to FIGS. 2 and 3, in an EDA environment, initial design data 85 for a complex IC is formed at each stage 81-83 of the design. In addition, a test bench 87 is created, which is typically in the form of Verilog / VHDL. The event data file 91 is created based on the test bench data 87 and the application software 88 through an event extraction process 89.
[0032]
As is well known, an FPGA has a memory therein to configure an intended circuit. Accordingly, a large-scale integrated circuit can be formed on the FPGA by writing appropriate data into the memory of the FPGA (programming). In the present invention, the event tester 92 provides configuration data (configuration data) to the FPGA via a control bus for programming (in-line programming) the FPGA. Generally, such configuration data is formed by translating the event data 91 based on rules specific to the FPGA stored in the in-line programming 93.
[0033]
After forming the intended IC on the FPGA board 94, the event tester supplies a test pattern (test vector) to the FPGA board 94 via a test fixture (for example, pogo pins or the like). During the execution of the test, all errors are detected by the event tester and diagnosed directly on the event tester. Since the FPGA is programmed in-line, the cause of the error can be corrected by the design netlist. As disclosed in the above-mentioned patent application, the event tester can change the event (test pattern) for each of the timing, the attribute, and the repetition rate, so that a wide range of tests can be performed on the design IC. In addition, since high-speed operation can be performed by a combination of the event tester and the FPGA, a software application at an at-speed (actual speed) can be executed for a long time, and thus a wide range of design verification can be performed. After detecting all errors and modifying the design, a final design 97 is established and used in the mass production stage 98.
[0034]
In the embodiment of the present invention, the FPGA board 94 is mounted on a test fixture, and various signals connected to the test fixture are used to control the FPGA. These signals provide various functions, and in-line programming of the FPGA is also performed via these signals.
Examples of such signals are:
(1) 32-bit control bus and 32-bit control word; these signals are implemented as open collectors in the tester controller in the present embodiment. These signals can also be used as bidirectional signals.
(2) 64-bit analog input / output signal; Both the 32-bit control word and the 64-bit signal have a general-purpose interface, and each of the bits can be individually controlled.
(3) Power supply connection: In the present embodiment, there are 16 DUT (device under test) power supplies and + 5V, + 15V, -5V, -15V power supplies, and each power supply for the DUT is 2A and 8V. is there. These power supplies have a parallel connection terminal and a floating terminal for use in high voltage applications.
[0035]
The inline programming of the FPGA is performed using a parallel interface or a serial interface. In a serial interface, multiple devices (FPGAs) can be connected in a daisy-chain arrangement. This method allows all FPGAs in the system to be programmed using only two control signals.
Another possible method is to configure multiple FPGAs in parallel using a bus. In such a parallel configuration, each device requires its own clock and data. With both buses, a total of 96 control bits are available, so that up to 48 FPGAs can be programmed in parallel (one clock and one data line per FPGA).
[0036]
The third possible method is the most common method, which is a combination of parallel connection and daisy chain connection. This example is shown in FIG. In the example of FIG. 5, an FPGA board 94 is connected to an FPGA 94 connected in series and in parallel. ₁ −94 ₆ Having. The event tester 92 supplies data and a clock to the FPGA 94 in parallel for in-line programming (creating an IC intended for the FPGA). The resulting IC has an interface 95, with which the event tester communicates with the pin card via a test fixture.
[0037]
As described above, the design verification method of the present invention performs design verification using an event tester and an in-line programmed FPGA instead of a slow simulation. The invention does not use full-chip (whole-chip) level simulations, and because application software can run much faster on FPGAs (compared to simulations), the present invention allows a wide range of technologies not possible with today's technology. Can be verified.
[0038]
FIG. 6 shows a second embodiment of the present invention. In this embodiment, an emulator is used instead of inline programming of the FPGA. In this case, the control bus of the event tester (the above-described 32-bit control word, 64-bit analog signal) is mapped to the interface bus of the emulator. 32 or 64 bits of the available 96 bits are used). Emulator vendors, such as ICOS Systems, have published emulation interfaces so that emulation systems can be connected to any system.
[0039]
Since the interface of the emulation system is open to the public, an emulator can be used in place of the in-line programmed FPGA as shown in FIG. This embodiment uses only an emulator board (rather than the entire emulation system), so the cost is somewhat more expensive than the FPGA method, but much less expensive than using the entire emulation system. In addition, when application data is loaded on the emulation board and the design error is debugged by an event tester, the verification speed is limited to a slow communication bus.
[0040]
Specifically, in FIG. 6, the emulator board 104 is connected to the event tester 92 via an emulator interface bus. The emulator board 104 receives data such as a test bench and application software via the emulator board interface 101. The emulator board 104 is further loaded with design data via a data loading step 102. As a result, the emulator board 104 emulates the design IC.
By executing the test bench on the emulator board, event data is created in the event file 105. The event tester 92 tests the design data of the emulator board 104 via the emulator interface bus using the event data, and evaluates the response output of the emulator board 104. After detecting all errors and correcting the design data, a final design 107 for mass production is established.
[0041]
7A and 7B compare the verification method of the present invention and the verification method shown in FIG. 3 (not the conventional method) side by side. 7A and 7B, a design data file 102 and a test bench 103 are formed by the step 101 of IC design. 7A, the logic simulation 105 is executed using the design data file 102 and the test bench 103. As is well known, this logic simulation constituted by a software process is very slow in operation compared to the intended operation speed of the IC. In the method of FIG. 7A, a silicon prototype 111 is created based on design data, and is tested by the event tester 110.
[0042]
The logic simulator 105 forms input / output signal data, for example, a VCD (value change dump) file 107, extracts the event data, and creates an event data file 108. The event tester 110 generates a test vector using the event data, and supplies the test vector to the silicon prototype 111. Therefore, a design error is detected in the silicon debug / verification step 112, a design bug is corrected in the bug correction step 106, and the corrected design bug is fed back to the design step.
[0043]
In the present invention shown in FIG. 7B, the test system 115 has a configuration in which the event tester 120 and the FPGA 124 are combined. The design data 102 is used to program the FPGA and implement the intended IC in the FPGA. The event data 116 is generated by using the test bench 103, and the event tester 120 generates a test vector generated by the event data 116. Since the FPGA 124 operates the intended IC at a speed closest to the actual IC speed, the application software can be executed as an at-speed test by the test method of the present invention.
[0044]
7A and 7B, the new method of the present invention eliminates the logic simulator 105 from the design verification process. Since the logic simulation has a low operation speed, it is a bottleneck for the current design verification. By removing this simulation process, a wide range of verification can be performed in a short time. The method of the present invention can debug all design errors of the event tester 120 without the need for an ASIC prototype. The verification process of the present invention is significantly more cost-effective and faster than other existing methods.
[0045]
As described above, the present invention verifies a design using an FPGA inline programmed with an event tester without using a slow EDA simulation tool. In addition to not using full-chip level simulation, the application software runs very fast (compared to simulation) on the FPGA, enabling a wide range of design verification not possible with current technology.
Since the low-speed simulation is removed from the design verification process, a wide range of design verification can be performed before the designed IC is manufactured. In addition, a wide range of design verification has been made possible, eliminating the need to create prototypes that were required before mass production. The design verification of the present invention is very efficient and low cost, and uses a process that is fundamentally different from the design verification methods in any of the existing systems described above.
[0046]
While only preferred embodiments have been set forth, various forms and modifications of the present invention are possible in the appended claims, based on the foregoing disclosure, without departing from the spirit and scope of the invention.
[Brief description of the drawings]
[0047]
FIG. 1 is a diagram illustrating the relationship between various levels of abstraction and the simulation speed in the development of a complex IC.
FIG. 2 is a schematic diagram showing a process of design verification using a conventional silicon prototype.
FIG. 3 is a schematic diagram illustrating an example of another design verification method, which is applicant's internal knowledge and is the subject of US patent application Ser. No. 09 / 941,396.
FIG. 4 is a block diagram showing a basic configuration example of a design verification method and apparatus of the present invention using a combination of an event tester and an inline program of an FPGA.
FIG. 5 is a schematic diagram showing a configuration example of an FPGA of the present invention in a parallel and daisy-chain configuration.
FIG. 6 is a block diagram showing a design verification method of the present invention using a combination of an emulator board and an event tester, and a basic configuration example of a device thereof.
7A and 7B are schematic diagrams comparing the verification method of FIG. 3 with the verification method of the present invention.

Claims (15)

In a method of verifying a complex IC design that has undergone a design process in an electronic design automation (EDA) environment,
Connecting a field programmable gate array (FPGA) to an event tester;
In-line programming of an FPGA via an event tester based on the IC design data created under the EDA environment to form an IC equivalent to the intended IC on the FPGA;
Providing a test vector obtained from the IC design data to the FPGA by an event tester, and evaluating a response output of the FPGA;
Correcting the design error by detecting an error in the response output and changing the in-line programming of the FPGA;
Repeating the above error detection and design error correction steps until error-free design data is obtained in the event tester;
Verification method of complex IC design composed of The method of claim 1, further comprising receiving design data and modifying the design data for in-line programming of the FPGA. The method of claim 1, wherein the step of in-line programming the FPGA via the event tester further comprises transmitting programming data to the FPGA via a control bus of the event tester. 2. The complex IC of claim 1, wherein the step of providing a test vector further comprises the step of executing application software for the intended IC formed on the FPGA and a test bench formed in an EDA environment. How to verify the design. The method of claim 1, further comprising extracting event data from a test bench formed in an EDA environment. 6. The method according to claim 5, further comprising: storing the extracted event data in an event tester, generating a test vector using the extracted event data, and providing the test vector to the FPGA via a test fixture of the event tester. Verification method for the described complex IC design. In a method of verifying a complex IC design that has undergone a design process in an electronic design automation (EDA) environment,
Connecting the emulator board to the event tester;
Supplying design data of the intended IC to an emulator board to emulate the function of the intended IC;
Providing a test vector obtained from the IC design data to an emulator board by an event tester and evaluating a response output of the emulator board;
Correcting the design error by detecting an error in the response output and changing the IC design data supplied to the emulator board;
Repeating the above error detection and design correction steps until error-free design data is obtained in the event tester;
Verification method of complex IC design composed of The method of claim 7, further comprising the step of receiving the design data and modifying the design data for an emulator board. 9. The complex IC design of claim 7, wherein the step of providing a test vector further comprises the step of executing application software for an intended IC formed on an emulator board and a test bench formed in an EDA environment. Verification method. The method for verifying a complex IC design according to claim 7, further comprising a step of creating event data from a test bench formed in an EDA environment. 11. The method according to claim 10, further comprising: storing the extracted event data in an event tester, generating a test vector using the extracted event data, and providing the test vector to the emulator board via a test fixture of the event tester. 3. A method for verifying a complex IC design described in 1. In a verification device for a complex IC design whose design process was performed in an electronic design automation (EDA) environment,
Means for connecting a field programmable gate array (FPGA) to an event tester;
Means for in-line programming the FPGA via an event tester based on the design data created in the EDA environment to form an IC equivalent to the intended IC on the FPGA;
Means for giving a test vector obtained from the design data of the IC by the event tester to the FPGA, and evaluating a response output of the FPGA;
Means for detecting an error in the response output and correcting the design error by changing the in-line programming of the FPGA;
Means for repeating the above error detection and design correction until error-free design data is obtained in the event tester;
Verification device for complex IC design. 13. The complex IC of claim 12, wherein the means for providing a test vector further comprises means for executing application software for an intended IC formed on the FPGA and a test bench formed in an EDA environment. Verification device for design. In a verification device for a complex IC design whose design process was performed in an electronic design automation (EDA) environment,
Means for connecting the emulator board to the event tester;
Means for supplying design data of an intended IC to an emulator board to emulate the function of the intended IC;
Means for giving a test vector obtained from the IC design data to an emulator board by an event tester and evaluating a response output of the emulator board;
Means for detecting an error in the response output and correcting the design error by changing the design data supplied to the emulator board;
Means for repeating the above-mentioned error detection and design correction until error-free design data is obtained in the event tester;
Verification device for complex IC design. 15. The complex of claim 14, wherein the means for providing a test vector further comprises means for executing application software for an intended IC formed on the emulator board and a test bench formed in an EDA environment. Verification device for IC design.

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