CN105259444A - FPGA device test model establishing method - Google Patents

Abstract

The invention relates to an FPGA device test model establishing method. The establishing method comprises following steps of establishing a test model for an individual logic unit; establishing a bidirectional reuse test model of an I/O base pin; when the logic units are integer multiples of the I/O base pins, equally dividing the logic units according to numbers of the base pins and then cascading the logic units so as to allow the coverage rate of usage of the inner logic units and the I/O base pins of an FPGA to achieve 100%; when the logic units are not integer multiples of the I/O base pins, configuring the whole logic units and the I/O base pins in the FPGA to be a cascading chain with X string A logic units and a cascading chain with Y string (A+1) logic units so as to allow the coverage rate of usage of the inner logic units and the I/O base pins of an FPGA to achieve 100%; and establishing a test model of an embedded type array. According to the invention, design verification and production test vectors of manufactures can be easily and quickly simulated, thereby achieving automatic testing of the FPGA device.

Description

FPGA device detection method for establishing model

Technical field

The present invention relates to the method for building up of test model, specifically FPGA device detection method for establishing model.

Background technology

FPGA device (field programmable gate array) has that performance is good, scale is large, can the advantages such as overprogram, development investment be little, become the vitals that various electronic product is indispensable.Because the personation renovation device on market gets more and more, seriously reduce the dependability of FPGA, cause user to enter before factory inspection is received must test at FPGA device.

Usually, for the test of FPGA device, need the test vector obtaining producer's design verification and production, adopt the method for boundary scan, completed the functional test of device by boundary scan control and boundary scan data chain.But test vector, as the vital strategic secrets of production firm, be difficult to obtain, and this method can only complete functional test, and can not carry out the test of DC parameter.

In the figure vector situation not having production firm, generally adopt the programming and testing method based on practical application, namely according to after the actual demand design programming of user, FPGA device is tested as a special circuit.But due to the privacy problem of content of programming, be sometimes difficult to accomplish, and the method is not suitable for the test in enormous quantities before factory yet.

For this reason, the present invention proposes a kind of FPGA device detection method for establishing model, can simulate the test vector of production firm's design verification and production with the FPGA device detection model that the method is set up quickly and easily, thus realizes the automatic test to FPGA device.

Summary of the invention

The object of the invention is to propose a kind of FPGA device detection method for establishing model.

For achieving the above object, the present invention adopts following technical scheme:

The method for building up of FPGA device detection model, comprises the following steps:

S1. the test model of single logical block is set up:

S11. the look-up table of logical block inside is configured to four input logic gates;

S12. the programmable register of logical block inside is configured to trigger;

S13. by described four input logic gates and trigger cascade, the test model of single logical block is formed;

S2. the two-way multiplexing test model of I/O pin is set up:

S21. select FPGA overall pin as direction end, the I/O state of control I/O pin;

S22. select FPGA common I/O pin, be connected to the I/O end of model;

S23. the input of described four input logic gates is connected to the I end of model, the output of described trigger is connected to the O end of model, forms the two-way multiplexing test model of I/O pin;

S3. the logic unit model described in step S1 and the I/O pin model described in step S2 are carried out cascade:

S31., when number of logic cells is the integral multiple of I/O number of pin, according to the quantity of pin, logical block is divided equally, and then cascade, make the use coverage rate of FPGA internal logic unit and I/O pin reach 100%;

S32., when number of logic cells is not the integral multiple of I/O number of pin, cascade is carried out in the steps below:

S321. logical block initial number A in each cascade chain is determined by following formula:

$Int\left(\frac{N}{M}\right)=A$

In formula: M is two-way I/O number of pin, and N is number of logic cells, N>M, and N can not be divided exactly by M;

S322. two kinds of cascade chains are selected, comprise A logical block and (A+1) individual logical block respectively, described logical block initial number A is substituted into following equations group, the number Y of the number X obtaining the first cascade chain comprising A logical block and the second cascade chain comprising (A+1) individual logical block:

$\left\{\begin{array}{c}X+Y=M\\ X\×A+Y\×(A+1)=N\end{array}\right.$

In system of equations: M is two-way I/O number of pin, and N is number of logic cells;

S323. inner for FPGA all logical blocks are become the cascade chain of X string A logical block and the cascade chain of Y string (A+1) individual logical block with I/O pin configuration, make the use coverage rate of FPGA internal logic unit and I/O pin reach 100%;

S4. the test model of embedded Array is set up:

S41. the amount of capacity of RAM contained by the single inner embedded Array of FPGA is determined;

S42. select with the SRAM of the capacity such as RAM described in step S41 as basic storage unit;

S43. by inner for FPGA all EBA with basic storage units in series described in step S42, form the test model of memory chains, cover the inner all unit of embedded Array.

Further, described trigger is d type flip flop.

The structure of the present invention's foundation FPGA device and principle of work, for the most important ingredient in its inside: logical block (CLB), I/O pin and embedded Array (EAB) set up corresponding model respectively, then obtain FPGA test model by cascade.By this test model, the test vector of production firm's design verification and production can be simulated quickly and easily, thus realize the automatic test to FPGA device.

Accompanying drawing explanation

Fig. 1 is the Establishing process schematic diagram of FPGA test model;

Fig. 2 is that logical block designs a model schematic diagram;

Fig. 3 is the two-way multiplexing test model schematic diagram of I/O pin;

Fig. 4 is embedded Array test model schematic diagram.

Embodiment

Below in conjunction with the drawings and specific embodiments, the present invention will be further described, but this embodiment should not be construed as limitation of the present invention.

Embodiment one

Measurand: the FPGA device XC3S400-4FTG256I of XILINX company, inner containing logical block 8064, I/O pin one 25, inner embedded Array capacity 288Kbit.

Modeling procedure:

S1. the test model of single logical block is set up:

S11. the look-up table of XC3S400-4FTG256I logical block inside is configured to four inputs and door;

S12. the programmable register of logical block inside is configured to J-K flip flop;

S13. by described four inputs and door and J-K flip flop cascade, the test model of single logical block is formed;

S2. the two-way multiplexing test model of I/O pin is set up:

S21. select XC3S400-4FTG256I overall pin as direction end, the I/O state of control I/O pin;

S22. select XC3S400-4FTG256I common I/O pin, be connected to the I/O end of model;

S23. the input of described four input logic gates is connected to the I end of model, the output of described trigger is connected to the O end of model, forms the two-way multiplexing test model of I/O pin;

S3. the logic unit model described in step S1 and the I/O pin model described in step S2 are carried out cascade:

XC3S400-4FTG256I number of logic cells is not the integral multiple of I/O number of pin, carries out cascade in the steps below:

S321. logical block initial number A in each cascade chain is determined by following formula:

$A=Int\left(\frac{N}{M}\right)$

In formula, M is two-way I/O number of pin 125, N is number of logic cells 8064, calculates A=64.

S322. select two kinds of cascade chains, comprise 64 logical blocks and 65 logical blocks respectively, substitute into following equations group, the number Y of the number X obtaining the first cascade chain comprising 64 logical blocks and the second cascade chain of comprising 65 logical blocks:

$\left\{\begin{array}{c}X+Y=N\\ X\×A+Y\×(A+1)=M\end{array}\right.$

In system of equations: M is two-way I/O number of pin 125, N is number of logic cells 8064, A=64, calculates X=61, Y=64.

S323. inner for XC3S400-4FTG256I all logical blocks are become the cascade chain of 61 strings, 64 logical blocks and the cascade chain of 64 strings, 65 logical blocks with I/O pin configuration, make the use coverage rate of FPGA internal logic unit and I/O pin reach 100%;

S4. the test model of embedded Array is set up:

S41. the amount of capacity determining RAM contained by the single inner embedded Array of XC3S400-4FTG256I is 18Kbit;

S42. a capacity is selected to be that the SRAM of 18Kbit is as basic storage unit;

S43. by inner for XC3S400-4FTG256I all embedded Array with 18Kbit basic storage units in series 16 described in step S42, form the test model of memory chains, cover the inner all 288Kbit storage unit of embedded Array.

Embodiment two

Measurand: logical block 576 is contained, I/O pin 72, inner embedded Array capacity 6144bit in the FPGA device EPF10K inside that ALTERA company produces.

Modeling procedure:

S1. the test model of single logical block is set up:

S11. the look-up table of logical block inside is configured to four input rejection gates;

S12. the programmable register of logical block inside is configured to d type flip flop;

S13. by described four input rejection gate and d type flip flop cascades, the test model of single logical block is formed;

S2. the two-way multiplexing test model of I/O pin is set up:

S21. select EPF10K overall pin as direction end, the I/O state of control I/O pin;

S22. select EPF10K common I/O pin, be connected to the I/O end of model;

S23. the input of described four input logic gates is connected to the I end of model, the output of described trigger is connected to the O end of model, forms the two-way multiplexing test model of I/O pin;

S3. the logic unit model described in step S1 and the I/O pin model described in step S2 are carried out cascade:

EPF10K number of logic cells is the integral multiple of I/O number of pin, and logical block being divided equally according to the quantity of pin is 8 parts, is configured to the cascade chain of 72 strings, 8 logical blocks, makes the use coverage rate of EPF10K internal logic unit and I/O pin reach 100%;

S4. the test model of embedded Array is set up:

S41. the amount of capacity 2048bit of RAM contained by the single inner embedded Array of FPGA is determined;

S42. capacity is selected to be that the SRAM of 2048bit is as basic storage unit;

S43. by inner for EPF10K all embedded Array with basic storage units in series described in step S42 3, form the test model of memory chains, the inner all 6144bit storage unit of covering internal embedded Array.

The content be not described in detail in this instructions, belongs to the known prior art of those skilled in the art.

Claims (2)

1. The method for building up of 1.FPGA device detection model, comprises the following steps:

   S1. the test model of single logical block is set up:

   S11. the look-up table of logical block inside is configured to four input logic gates;

   S12. the programmable register of logical block inside is configured to trigger;

   S13. by described four input logic gates and trigger cascade, the test model of single logical block is formed;

   S2. the two-way multiplexing test model of I/O pin is set up:

   S21. select FPGA overall pin as direction end, the I/O state of control I/O pin;

   S22. select FPGA common I/O pin, be connected to the I/O end of model;

   S23. the input of described four input logic gates is connected to the I end of model, the output of described trigger is connected to the O end of model, forms the two-way multiplexing test model of I/O pin;

   S3. the logic unit model described in step S1 and the I/O pin model described in step S2 are carried out cascade:

   S31., when number of logic cells is the integral multiple of I/O number of pin, according to the quantity of pin, logical block is divided equally, and then cascade, make the use coverage rate of FPGA internal logic unit and I/O pin reach 100%;

   S32., when number of logic cells is not the integral multiple of I/O number of pin, cascade is carried out in the steps below:

   S321. logical block initial number A in each cascade chain is determined by following formula:

   $Int\left(\frac{N}{M}\right)=A$

   In formula: M is two-way I/O number of pin, and N is number of logic cells, N>M, and N can not be divided exactly by M;

   S322. two kinds of cascade chains are selected, comprise A logical block and (A+1) individual logical block respectively, described logical block initial number A is substituted into following equations group, the number Y of the number X obtaining the first cascade chain comprising A logical block and the second cascade chain comprising (A+1) individual logical block:

   $\left\{\begin{array}{c}X+Y=M\\ X\×A+Y\×(A+1)=N\end{array}\right.$

   In system of equations: M is two-way I/O number of pin, and N is number of logic cells;

   S323. inner for FPGA all logical blocks are become the cascade chain of X string A logical block and the cascade chain of Y string (A+1) individual logical block with I/O pin configuration, make the use coverage rate of FPGA internal logic unit and I/O pin reach 100%;

   S4. the test model of embedded Array is set up:

   S41. the amount of capacity of RAM contained by the single inner embedded Array of FPGA is determined;

   S42. select with the SRAM of the capacity such as RAM described in step S41 as basic storage unit;

   S43. by inner for FPGA all EBA with basic storage units in series described in step S42, form the test model of memory chains, cover the inner all unit of embedded Array.
2. 2. FPGA device detection method for establishing model according to claim 1, is characterized in that: described trigger is d type flip flop.