JP2004523860A - Method and apparatus for forming a battery in an integrated circuit - Google Patents

Abstract

A method and structure for providing a battery in an integrated circuit that supplies a voltage to a low-current electronic device present in the integrated circuit.
A method according to the present invention includes a FEOL process for forming a layer of electronic devices on a semiconductor wafer and a BEOL integration for subsequently interconnecting the electronic devices to form a complete electrical circuit of the integrated circuit. And BEOL integration involves forming a multilayer structure 450 of interconnect levels 901,..., 900 + N on layer 900 of electronic device 410. Each wiring level includes conductive metallization 432, 434, 442, 444 (eg, metal plated vias, conductive wiring, etc.) embedded in an insulating material. A battery 420 is formed in at least one interconnect level during BEOL integration. The conductive metallization electrically connects the positive terminal 424 and the negative terminal 422 of the battery to the electronic device. Batteries come in a number of different geometries related to the structural and geometric relationships between the battery electrodes and the electrolyte. A plurality of cells can be formed within at least one interconnect level and conductively connected to an electronic device. A plurality of batteries can be connected in series or in parallel.
[Selection diagram] Fig. 1

Description

【Technical field】
[0001]
The present invention relates to a method and structure for realizing a battery in an integrated circuit for supplying a voltage to a small current electronic device present in the integrated circuit.
[Background Art]
[0002]
2. Description of the Related Art An integrated circuit (including a semiconductor chip) includes an electronic device formed on a bulk silicon substrate, and a metal wiring pattern for conductively connecting these electronic devices to form an electric circuit. The term “conductive” and its analogues mean “electrically conductive” (= conductivity) unless otherwise specified. Electronic devices include field effect transistors, bipolar transistors, diodes, and the like. The metal wiring pattern includes a conductive wiring, a metal plating via (via), and the like. In an integrated circuit, a metal wiring pattern has a multilayer structure. In this multilayer structure, each layer has an intra-layer metal wiring pattern embedded in an insulating material such as a dielectric material. The predetermined-layer in-layer metal wiring pattern is conductively connected to at least one other-layer in-layer metal wiring pattern, and is also conductively connected to the electronic device.
[0003]
Integrated circuit electronic devices require a bias voltage and a reference voltage. These are provided by existing or standard voltage sources. Existing or standard voltage sources include batteries that are readily available by commerce. For certain integrated circuit applications requiring non-standard bias voltages and non-standard reference voltages, existing or standard voltage sources are not suitable. The non-standard bias voltage or the non-standard reference voltage is any voltage that is not included in the voltage group supplied by the standard voltage source.
DISCLOSURE OF THE INVENTION
[Problems to be solved by the invention]
[0004]
There is a need for a method and structure for providing a non-standard bias voltage and a non-standard reference voltage according to the specific requirements of a particular integrated circuit.
[Means for Solving the Problems]
[0005]
The present invention realizes an electrochemical structure having the following components in an integrated circuit. That is, a semiconductor wafer, an electronic device layer formed on the semiconductor wafer, N (N = 1, 2, 3,...) Wiring levels formed on the electronic device layer, and a wiring level , K (I = 1, 2,..., N, K = I, I + 1,..., N). However, the electronic device layer includes at least one electronic device. N is at least 1, and the N wiring levels represent wiring level 1, wiring level 2,..., Wiring level N. The N wiring levels have a first conductive metallization and a second conductive metallization. The first conductive metallization connects a first electrode of the at least one battery to the at least one electronic device. The second conductive metallization connects a second electrode of the at least one battery to the at least one electronic device.
[0006]
The present invention provides a method for forming an electrochemical structure in an integrated circuit. The method comprises the steps of providing a semiconductor wafer, forming an electronic device layer on the semiconductor wafer, and providing N (N = 1, 2, 3,...) Wiring levels on the electronic device layer. And forming at least one battery in the wiring levels I, I + 1,..., K (I = 1, 2,..., N, K = I, I + 1,. And a step of performing However, the electronic device layer includes at least one electronic device. N is at least 1, and the N wiring levels represent wiring level 1, wiring level 2,..., Wiring level N. The N wiring levels have a first conductive metallization and a second conductive metallization. The first conductive metallization connects a first electrode of the at least one battery to the at least one electronic device. The second conductive metallization connects a second electrode of the at least one battery to the at least one electronic device.
[0007]
According to the present invention, it is possible to supply a non-standard bias voltage and a non-standard reference voltage according to the specific requirements of a specific integrated circuit. The present invention also eliminates the need for extra wiring levels and the need for an external voltage source that requires a large size and volume to supply voltage to an integrated circuit that requires only low power input.
BEST MODE FOR CARRYING OUT THE INVENTION
[0008]
Integrated circuits are manufactured, inter alia, by FEOL (Front-End-Of-Line) processing followed by BEOL (Back-End-Of-Line) integration. FEOL processing consists of forming an electronic device layer on a semiconductor wafer. This includes auxiliary steps that define the electronic device (eg, photolithography, heat treatment, ion implantation, oxidation, etc.). Semiconductor wafers include, among others, bulk crystalline silicon wafers with (or without) a buried oxide layer. Electronic devices include transistors, bipolar transistors, diodes, among others. In BEOL integration, electronic devices are conductively connected to each other to form a complete electrical circuit by forming a multilayer structure on and above the electronic device layers. Each layer of the multilayer structure is considered a wiring level with conductive metallization embedded in an insulating material (eg, metal plated vias, conductive wiring, etc.). (A level is a surface having a flat surface.) Therefore, one layer of the multilayer structure is referred to herein as a “wiring level”. Each wiring level is formed by the following steps, among others. Providing a layer of dielectric material on a previously formed layer, forming a trench or via in the dielectric material, and forming a metal in the trench or via (or on the sidewall of the trench or via). And polishing (ie, planarizing) the exposed surface of the dielectric material layer. As a result of forming the interconnect levels, the conductive metallization in each interconnect level is conductively connected with the conductive metallization in another interconnect level. Then, as a result of the BEOL integration, a completed circuit group of the integrated circuit is formed. To be clear, BEOL integration starts with the first step, where possible, of forming the first metallization on (or in or connected to) the semiconductor wafer. This is done even if the formation of the electronic device layer is not completed.
[0009]
The present invention provides a method and structure for forming a battery at (or on) the wiring level of the above-described multilayer structure in an integrated circuit. The battery according to the invention is formed in at least one interconnect level during BEOL integration. Although the extra wiring level of the multilayer structure is formed so that a battery can be formed, a battery can be formed without forming an extra wiring level depending on circumstances. Such a situation is when a battery is provided on a part of the interconnect level where conductive metallization is sparse. The battery according to the present invention is formed directly above at least one electronic device or at a position above at least one electronic device but laterally offset from the electronic device.
[0010]
FIG. 1 shows a bulk semiconductor wafer 402, an electronic device layer 900 connected to the bulk semiconductor wafer 402, N wiring levels formed on the electronic device layer 900 during BEOL integration, and BEOL integration according to an embodiment of the present invention. FIG. 3 illustrates an integrated circuit 400 including a battery 420 formed therein. , 900 + J,..., 900 + N, and the battery 420 exists at the wiring level 900 + J (where 2 <J <N). Fabrication of the integrated circuit 400 begins with the step of providing a bulk semiconductor wafer 402 (eg, a bulk single crystal silicon wafer with or without a buried oxide layer). Next, in the FEOL process, the electronic device layer 900 is formed on the bulk semiconductor wafer 402 by any method known to those skilled in the art. Electronic device layer 900 comprises a plurality of electronic devices in the background of a semiconductor material (eg, p-type silicon), but the integrated circuit comprises millions or more of electronic devices. Electronic devices include semiconductor devices such as field effect transistors, bipolar transistors, and diodes, among others. For illustrative purposes, electronic device layer 900 includes a field effect transistor (FET) 410. The FET 410 includes a source / drain 411, a source / drain 412, a channel 413, a gate 414, a gate insulating film 415, and an insulating spacer 418.
[0011]
After the FEOL processing, BEOL integration is performed. In BEOL integration, N wiring levels (N ≧ 1) are formed. Also, forming a conductive metallization to be embedded in an insulating material (for example, a dielectric material) is included. Conductive metallization includes conductive wiring, metal plated vias, and the like. The conductive metallization functions to conductively connect the electronic devices on the electronic device layer 900. Reference numeral 432, which represents conductive metallization, represents conductive metallization in wiring levels 901,..., 900 + J, and includes all types of conductive metallizations (e.g., conductive wiring, metal plated vias) in each wiring level. Etc.). Reference numeral 434 representing a conductive metallization represents a conductive metallization in the wiring levels 901,..., 900 + J, and includes all types of conductive metallizations (e.g., conductive wiring, metal plated vias) in each wiring level. Etc.). Electrical conductor 442 is a type of conductive metallization, representing a conductive plate, conductive plug, or similar conductive enclosed space in wiring level 900 + J-1. Electrical conductor 444 is also a type of conductive metallization, representing a conductive plate, conductive plug, or similar conductive enclosed space in wiring level 900 + J + 1. Although not shown, wiring levels 900 + J + 2,..., 900 + N also include all types of conductive metallization (eg, conductive wiring, metal plated vias, etc.).
[0012]
The wiring level 901 is formed on the electronic device layer 900 and the wiring level 900 + I is formed on the wiring level 900 + I-1 using any method known to those skilled in the art (where I = 2, 3,...). ., N). Each of the N wiring levels is formed, inter alia, by the following steps. That is, a step of providing a layer of a dielectric material on the previously formed wiring level (or on the electronic device layer 900 when the wiring level 901 is formed), and forming a trench or a via in the dielectric material. A step of filling a metal (for example, copper) in the trench or the via (or a side wall of the trench or the via), and a step of polishing (ie, planarizing) the formed wiring-level exposed surface. The step of forming interconnect levels causes each interconnect level to become another interconnect level, to at least one electronic device formed during the FEOL process, and / or to at least one electronic structure external to integrated circuit 400 or Conductively connected to an electrical device. ("A and / or B" represents "A and B, A, or B".) As described above, a complete circuit of the integrated circuit 400 is formed.
[0013]
As will be described below when forming the battery 38 associated with FIGS. 2-7, the battery 39 associated with FIGS. 8-13, or the battery 170 associated with FIG. Form. The battery 420 is formed in parallel with other processes typically performed in connection with the J-th interconnect level (eg, forming vias using photolithography, adding metallization through a damascene process, etc.). Battery 420 has a negative terminal 422 that is conductively connected to conductor 442. Battery 420 has a positive terminal 424 conductively connected to conductor 444. Battery 420 supplies voltage to FET 410 via the following conductive path. That is, a conductive path composed of the positive terminal 424-conductor 444-conductive metallization 434-source / drain 412 of the FET 410 and a conductive path composed of the negative terminal 422-conductor 442-conductive metallization 432-FET 410 of the source / drain 411. And As described above, the battery 420 is at the J-th wiring level. Here, J represents any positive integer in the range of 1 ≦ J ≦ N. Therefore, the battery 420 can be formed at an arbitrary wiring level in the integrated circuit 400. Alternatively, the battery 420 can be formed on the surface 448 of the wiring level 900 + N. In general, the battery 420 has a wiring level of 900 + I to 900 + K (I is any value among values 1, 2,..., N, and K is any value among I, I + 1,. A) can exist at the wiring level. Generally, the battery 420 is a single battery, a plurality of batteries connected in series as illustrated in FIGS. 15 to 17 described below, or a plurality of batteries connected in parallel as illustrated in FIG. 18 described later. It represents.
[0014]
The wiring level configuration shown in FIG. 1 is a specific example, and many other wiring level configurations are possible. For example, while the battery 420 of FIG. 1 is provided at a single wiring level 900 + J, the battery 420 may exist at multiple wiring levels. Specifically, the battery 170 of FIG. 14 includes a first conductive layer 172 (which is an electrode), an electrolyte 174, and a second conductive layer 176 (which is also an electrode), as described later. However, each exists at a different wiring level. Alternatively, the first conductive layer 172, the electrolyte 174, and the second conductive layer 176 may be at a single interconnect level. Similarly, conductive metallization can be provided at the required interconnect level. The wiring levels in the above-described embodiment are for explanation and description. Accordingly, the present invention is not exhausted and is not limited to the precise form disclosed herein. Many modifications and variations are possible. Modifications apparent to those skilled in the art are within the scope of the invention as defined in the claims.
[0015]
Here is a summary of the limitations on wiring-level expressions. That is, the wiring level including the battery or a portion of the battery (eg, battery electrodes) cannot exceed the physical range of the battery in the direction of reference numeral 450. Thus, in FIG. 1, a single wiring level cannot include both battery 420 and conductor 442. 3 because conductor 442 is beyond the physical range of battery 420, ie, conductor 442 does not occupy the space between positive terminal 424 and negative terminal 422 of battery 420. In contrast, multiple wiring levels can be defined between the positive terminal 424 and the negative terminal 422 of the battery 420. This is because each of the multiple wiring levels does not exceed the physical range of the battery 420. Also note that batteries can be provided within multiple wiring levels. For example, batteries can be provided within two wiring levels. As a result, the first electrode of the battery can be provided at the first wiring level of the two wiring levels, and the electrolyte and the second electrode of the battery can be provided at the second wiring level of the two wiring levels. The above described wiring level representational limitations help to clarify the features of the present invention for the relationship between conductive metallization placement and battery placement.
[0016]
At the wiring level 900 + J where the battery 420 is provided (or at a plurality of wiring levels within the wiring level 900 + J (when defined as such)), neither the conductor 444 nor the conductor 442 can be arranged. However, the battery 420 can be rotated 90 degrees (ie, from the direction of reference numeral 450 to the direction of reference numeral 451). As a result of such rotation, the positive terminal and the negative terminal of the battery 420 can be positioned as shown in FIG. That is, the conductors (for example, conductors 444 and 442) connected to the positive terminal and the negative terminal of battery 420 have the same wiring level 900 + J (or wiring level 900 + J within wiring level 900 + J) as battery 420 is provided. If it is defined in the above)). In summary, two possibilities for the arrangement of conductor 444 and conductor 442 relative to the location where battery 420 is located are within the scope of the invention. A first possibility is to place both conductors 444 and 442 outside the wiring level or wiring levels where battery 420 is provided. A second possibility is to place both conductors 444 and 442 within the wiring level or multiple wiring levels where battery 420 is provided.
[0017]
Here, as shown in FIGS. 20 (a), 20 (b), 20 (c), and 21, some geometric shapes of the battery are presented. The battery geometries presented here include U-shaped batteries, U-shaped batteries with extensions, and S-shaped batteries.
[0018]
FIG. 20 (a) is a diagram illustrating an electrolyte 600 of a U-type battery according to an embodiment of the present invention. The electrolyte 600 has a “U” shape (in cross section) and includes a base 602, an arm 604, and an arm 606. Base 602, arm 604, and arm 606 together define a cavity 610.
[0019]
FIG. 20 (b) is a diagram illustrating a U-type battery 650 including the electrolyte 600 of FIG. 20 (a) according to an embodiment of the present invention. Cavity 610 is partially or completely filled with a conductive material to form cavity electrode 620. A base electrode 622 having a conductive material is in contact with part of the base 602 of the electrolyte 600. In general, the electrolyte 600 of the U-cell 650 need not be exactly "U" shaped, but need to have a base, two arms, and a cavity. As a result, when the cavity is partially or completely filled with a conductive material, the conductive material of the resulting cavity electrode will contact the base and the two arms.
[0020]
FIG. 20C is a diagram illustrating a U-shaped battery 670 with an extension portion obtained by adding extension portions 624 and 626 to the U-type battery 650 of FIG. 20B. The extensions 624, 626 each include the conductive material of the base electrode 622 and must be in contact with a portion of the arms 604, 606 of the electrolyte 600, respectively. If both extensions 624, 626 are present, battery 670 is a U-shaped battery with dual extensions. If only one of the extensions 624, 626 is present (both cannot be present), the battery 670 is a U-type battery with a single extension.
[0021]
FIG. 21 is a diagram illustrating an S-type battery 680 according to an embodiment of the present invention. The S-type battery 680 includes an electrolyte 684 sandwiched between two electrodes 682 and 686. The feature of the S-type battery is that the electrolyte sandwiched between the two electrodes has a stratified structure (ie, has a stratified structure).
[0022]
The battery of the present invention eliminates the need for an external voltage source for specific applications requiring a non-standard bias voltage or a non-standard reference voltage. Also, according to the battery of the present invention, an external voltage source or an external current source that supplies a voltage or a current to an integrated circuit that requires a low power input, respectively (such an external voltage source or an external current source is more than desired) Also requires many wiring levels, large dimensions, and a large occupied volume). For example, the batteries of the present invention are advantageously used for biomedical applications. This is because in biomedical applications, a sensor is attached to a catheter that is inserted into the human body, and the sensor has a battery in the integrated circuit that supplies power to the integrated circuit of the sensor. As another example, the battery of the present invention can be formed in a low power integrated circuit in a disk drive head. Then, the battery of the present invention can supply the power required by the head of the disk drive device and can be periodically recharged. Also, the thermal cycles experienced by the battery during BEOL integration can be reduced compared to FEOL processing. This is because the temperature to which the battery of the present invention is exposed during BEOL integration is lower than in FEOL processing. The battery of the present invention is particularly suitable for highly reactive lithium or lithiated vanadium oxide (Li ₈ V _Two O _Five ), It is advantageous to reduce thermal cycling.
[0023]
2-7 illustrate an apparatus and method for forming a battery for use in an integrated circuit (eg, integrated circuit 400 described above in conjunction with FIG. 1) during BEOL integration, in accordance with an embodiment of the present invention.
[0024]
FIG. 2 is a front sectional view of the first electrochemical substrate 1. The first electrochemical substrate 1 is made of SiO _Two And a first conductive layer 8 provided in the substrate 2. The first conductive layer 8 is formed using any method known to those skilled in the art, for example, using the damascene procedure described in Beyer, US Pat. No. 5,965,459 (1999). Substrate 2 represents a portion of a wiring level (eg, any of wiring levels 901, 902,..., 900 + N described above in connection with integrated circuit 400 of FIG. 1). First, the substrate 2 is exposed to the surface of the electronic device layer 900 or the surface of one of the wiring levels 901,..., 900 + J,. Deposit using any method.
[0025]
The substrate 2 is then patterned and etched by any method known to a person skilled in the art, for example, in particular by a photolithographic method. As a result, a shallow first trench 3 is formed. The width of the first trench 3 in the direction of reference numeral 5 is about 0.3 μm (ie, microns) to about 5 μm, and the height is about 0.3 μm to about 5 μm. Next, after the first trench 3 is filled with the first conductive material, the excess first conductive material is removed by polishing, for example, by CMP (chemical mechanical polishing), and the processed surface 4 of the substrate 2 is planarized. I do. When the first trench 3 is filled with a first conductive material, a first conductive layer 8 is formed. The first conductive layer 8 is formed using reactive sputtering of vanadium as described in US Pat. No. 5,338,625 to Bates et al. (1994), or any method known to those skilled in the art. If the first conductive material is V _Two O _Five Where the first conductive material functions as the cathode of the electrolyte cell. The first conductive material is Li ₈ V _Two O _Five Where the first conductive material functions as the anode of the electrolyte cell. An electrolyte cell derived from the electrochemical substrate 1 is a battery 38 shown later in FIG.
[0026]
FIG. 3A shows an example in which an etch stop layer 9 (for example, a silicon nitride layer) is formed on the planarized substrate 2 of FIG. 2, and a first level dielectric (ILD) layer is formed on the etch stop layer 9. FIG. 10 is a view after forming No. 10; The etch stop layer 9 and the first ILD layer 10 can be formed by any method known to those skilled in the art. The etch stop layer 9 functions as a barrier layer for etching, and residual ions remain in the substrate 2 during a subsequent patterning step, wet etching step, or planarization step (which will be described later with reference to FIG. 5). Prevent chemical diffusion. Etch stop layer 9 has a thickness of about 0.015 μm to about 0.3 μm. If the etch stop function of the etch stop layer 9 is unnecessary, the etch stop layer 9 may be omitted. The thickness of the first interlevel dielectric (ILD) layer 10 is between about 0.285 μm and about 4.7 μm.
[0027]
Next, the second trench 13 is formed in the first ILD layer 10 by any method known to those skilled in the art (for example, the following two steps). That is, in the first step, the first ILD layer 10 is patterned and etched using any appropriate photolithography method known to those skilled in the art. By this patterning and etching, a part of the first ILD layer 10 is removed, and a part of the first ILD layer 10 is left on the etch stop layer 9. In a second step, the first portion 18 of the etch stop layer 9 is patterned and etched to remove the first portion 18 of the etch stop layer 9. As a result, the second portion 15 of the etch stop layer 9 remains on the first portion 17 of the first conductive layer 8, and the second portion 11 of the first conductive layer 8 is exposed.
[0028]
If the cross section of the second trench 13 is rectangular, the second trench has a first wall 32, a second wall 34, and a bottom wall. However, the bottom wall forms substantially the same plane as the surface 36 of the exposed second portion 11 of the first conductive layer 8. Alternatively, the cross section of the second trench 13 may be circular.
[0029]
FIG. 3B is an alternative to FIG. 3A, in which the etch stop layer 9 in FIG. The diffusion barrier film 14 is provided on the surface of the second ILD layer 10, on the first wall 32 and the second wall 34 of the second trench 13, and on the surface 36 of the first conductive layer 8. Diffusion barrier film 14 can be deposited by any method known to those skilled in the art. Diffusion barrier film 14 functions as a diffusion barrier film, allowing impurities to leak into the bulk semiconductor wafer (eg, bulk semiconductor wafer 402 of FIG. 1) and into the electronic device layer immediately above the bulk semiconductor wafer (eg, layer 900 of FIG. 1). To prevent Such impurities originate, inter alia, from the electrolyte of the battery in the electrochemical substrate 1. In the example of FIG. 1, impurities leak and permeate in the order of the electrolyte-conductor 442 of the battery 420-the conductive metallization 432-the gate 414 of the FET 410. As another example, impurities leak and permeate in the order of the electrolyte-conductor 444 of the battery 420-the source / drain 412 of the conductive metallization 434 -FET 410. The material of the diffusion barrier film 14 must be a conductive material so as not to insulate the first conductive layer 8 from the electrolyte layer 41 (the electrolyte layer 41 subsequently formed as described later with reference to FIGS. 4 and 5). is there. Alternatively, when the bottom portion 16 of the diffusion barrier film 14 is removed by RIE (reactive ion etching), it is not necessary to use a conductive material for the diffusion barrier film 14 (in RIE, the first conductive layer 8 is electrically connected to the electrolyte layer 41 from the electrolyte layer 41). Is not electrically insulated). In order to function effectively as a diffusion barrier, the thickness of the diffusion barrier film 14 needs to be a minimum value determined by the material of the diffusion barrier film 14. A typical minimum thickness for some materials is about 5 nm. FIGS. 4 to 7 show the etch stop layer 9 of FIG. 3A, which will be described later. In FIGS. 4 to 7, the etch stop layer 9 of FIG. A diffusion barrier layer 14 may be used. Similarly, FIGS. 8-18 (described below) show an etch stop layer 89 (see especially FIG. 9) similar to the etch stop layer 9 of FIG. Also in FIG. 18, a diffusion barrier layer (for example, the diffusion barrier layer 14 in FIG. 3B) may be used instead of the etch stop layer 89.
[0030]
FIG. 4 shows the remaining portion 12 of the first ILD layer 10 of FIG. 3A, the first wall 32 of the second trench, the second wall 34 of the second trench, and the first conductive layer. FIG. 7 shows a state in which an electrolyte layer 41 has been formed on the surface 36 of the second part 11 of the layer 8 and a third trench 44 has been obtained in the electrolyte layer 41. The third trench 44 has a rectangular or circular cross section in a plane perpendicular to the direction indicated by reference numeral 6. The electrolyte layer 41 includes a first portion 48 on the first ILD layer 10 and a second portion 42 in the first ILD layer 10. Electrolyte layer 41 can be formed by any method known to those skilled in the art, for example, as described in Bates et al., US Pat. No. 5,338,625 (1994). According to Bates et al., Electrolyte materials such as lithium phosphorus oxynitride (Lipon) or similar materials are replaced by N _Two Li in the atmosphere _Three PO _Four The thickness is faithfully deposited on the underlying shape to a uniform thickness of about 0.11 μm to about 1.8 μm by a known method such as RF magnetron sputtering. Next, a second conductive layer 49 is formed on the electrolyte layer 41 so as to conform to the underlying shape. The second conductive layer 49 includes a first portion 50 above the first portion 48 of the electrolyte layer 41 and a second portion 53 in the second portion 42 of the electrolyte layer 41. The second conductive layer 49 is made of a second conductive material, for example, lithium metal or lithiated vanadium oxide (Li). ₈ V _Two O _Five ). As a result, the third trench 44 is filled with the second conductive material. Again, a film of lithium metal is deposited on a film of lithium phosphorus oxynitride (Lipon) by the method described in US Pat. No. 5,338,625 to Bates et al.
[0031]
FIG. 5 shows the structure 1 by removing the first portion 50 of the second conductive layer 49 and the first portion 48 of the electrolyte layer 41 of FIG. 4 using any method known to those skilled in the art, for example, CMP. FIG. 5 is a diagram in which the surface 57 of FIG. In the example shown in FIG. 5, the planarization of the structure 1 forms a conductive metal plug or contact 46 (formerly the second portion 53 of the second conductive layer 49 in FIG. 3A). The height (in the direction of reference numeral 6) of the contact 46 is about 0.225 μm to about 3.8 μm, and the width (in the direction of reference numeral 5) is about 0.08 μm to about 1.4 μm. The electrolyte layer 41 (ie, the second portion 42 shown in FIG. 4) separates the second conductive material of the conductive metal plug or contact 46 from the second portion 11 of the first conductive layer 8.
[0032]
The structure 1 shown in FIG. 5 includes an electrolyte cell or battery 38. In the battery 38, the first conductive layer 8 and the first conductive plug or contact 46 are electrodes, and the electrolyte layer 41 is used when lithium ions or other alkali metal ions move from the anode of the battery 38 to the cathode of the battery 38. To provide a medium that relies on For example, in battery 38, the conductive plug or contact 46 is made of metallic lithium or Li ₈ V _Two O _Five The anode is derived from the second conductive material such as _Two O _Five If the cathode is from a first conductive material, such as, lithium ions migrate from the conductive plug or contact 46 to the first conductive layer 8 during the discharge cycle of the battery. Conversely, in the battery 38, the first conductive layer 8 is made of metallic lithium or Li ₈ V _Two O _Five Is an anode because it is derived from a first conductive material such as _Two O _Five If the cathode is from a second conductive material, such as, lithium ions migrate from the first conductive layer 8 to the conductive plug or contact 46 during the discharge cycle of the battery.
[0033]
Where electrodes 8 and 46 are electrodes of a thin film lithium battery, electrodes 8 and 46 are made of materials such as those described by Lee et al. In that case, the cathode is V _Two O _Five , Electrolyte is lithium phosphorus oxynitride (Lipon), anode is Li ₈ V _Two O _Five It is. "All-solid rocking chair (rocking chair) type lithium battery formed on flexible Al substrate" (Electrochemical and Solid State Letters Vol. 2, No. 9, pp. 425-427 (1999)) (") All-Solid-State Rocking Chair Lithium Battery on a Flexible Al Substrate ", Electrochemical and Solid-State Letters, 2 (9) 425-427 (1999)). Bates, U.S. Pat. No. 5,567,210 (1996), describes surface area versus lithium / Lipon / V. _Two O _Five Performance characteristics related to battery output are described. Bates are amorphous LiMn _Two O _Four Cathode is single crystal LiCoO _Two Amorphous LiMn for applications that can achieve lower discharge rates and require battery fabrication at room temperature. _Two O _Four A cathode is recommended. John B. Bates 'Material, v1-5 / 1/98, URL "http://www.ccs.ornl.gov/3M/bates.html" (John B. Bates' Material, v1-5 / 1 / 98, url "http://www.ccs.ornl.gov/3M/bates.html"). Also, Park et al., “All-solid-state lithium thin-film rechargeable battery using lithium manganese oxide” (Electrochemical and Solid State Letters, Vol. 2, No. 2, February 1999) 58-59) (Park et al., "All-Solid-State Lithium Thin-Film Rechargeable Battery With Lithium Manganese Oxide", Electrochemical and Solid-State Letters, 2 (2) Feb. (1999) 58-59) Reference (Li / Lipon / LiMn _Two O _Four And has a nearly constant potential of 4.0 [volts] V, good coulombic efficiency, and the ability to withstand high current densities. Planar microcells connected in series by metallization Park et al. Stated that they were able to obtain a high voltage of about 32 volts (V) from eight batteries connected in series). U.S. Pat. No. 5,308,720 (1994) to Kurokawa et al. Discloses an anode composed of "a material that reversibly stores and releases lithium", a "non-aqueous electrolyte, and a composite oxide containing lithium, nickel, and oxygen. A non-aqueous battery with a "positive electrode" is disclosed. Another electrolyte cell is M / PbSnI _Four / (AgI, Ag). Here, M is a cathode and is made of Sn or Pb, and PbSnI _Four Is an electrolyte, and AgI and Ag are anodes. T. A. Kuku's "PbSnI vacuum deposited _Four Ion Transport Studies on Vacum Deposited PbSnI (Shin Solid Film, Vol. 340, No. 1, pp. 292-296 (1999)) _Four Thin Films ", Thin Solid Films, 340 (1) 292-296 (1999). Gregor is a silver (Ag) cathode, silver oxide (Ag). _Two O) It has been proposed to form a thin film battery which is composed of an electrolyte and copper (Cu) and is suitable as a fine element for supplying a bias potential to a field effect transistor formed on a substrate. See "Thin Film Voltage Source", IBM Technical Disclosure Britain, November 1964, p. 433 ("Thin Film Voltage Source", IBM Technical Disclosure Bulletin, Nov. 1964 p.433). Also, the electrolyte cell can be constituted by an Ag / Zn battery by using potassium hydroxide in water.
[0034]
FIG. 6 is a diagram after a path leading to the conductive metal plug of FIG. The path comprises an interconnect via 65 and a contact hole or via 72. The path leading to the conductive metal plug or contact 46 can be formed using techniques known to those skilled in the art, for example, a "dual damascene" technique. For example, US Pat. No. 5,759,911 to Cronin et al. (1998) describes a “dual damascene” technique for simultaneously forming a group of conductive lines that are patterned using two masks. There, a stud via connection is formed during BEOL integration in an integrated circuit that passes through the insulating layer and leads to the underlying metallization. See also, Cronin's U.S. Patent No. 5,960,254 (1999), which describes a dual damascene approach. See also, Chow et al., US Pat. No. 4,789,648 (1988), which describes a dual damascene approach. In the present invention, as preparation for using the dual damascene method, first, the second ILD layer 58 is formed on the flattened surface 57. The second ILD layer 58 has a thickness of about 0.15 μm to about 2.5 μm and comprises an interlevel dielectric material, such as, for example, sputtered quartz. Next, contact holes or vias 72 are defined using photolithography. This photolithography is performed by forming a first mask layer 63 made of a photoresist on the second ILD layer 58 by a method known to those skilled in the art. To facilitate alignment, standard alignment means are used, for example, as described in Cronin et al., US Pat. No. 5,759,911. Then, an etch stop layer (not shown) may be deposited on the second ILD layer 58 or on the first mask layer 63. Next, on the second ILD layer 58 and the first mask layer 63, a third ILD layer 60 made of an interlevel dielectric material such as, for example, sputtered glass is formed.
[0035]
Next, the third ILD layer 60 is patterned using the required second mask in a "dual damascene" manner and etched using methods suitable for patterning and etching known to those skilled in the art. As a result of removing a portion of the third ILD layer 60 and leaving the remaining portion 62, an interconnect via 65 reaching the first mask layer 63 is formed in the third ILD layer 60. Further, by removing the portion of the second ILD layer 58 that is not protected from etching by the first mask layer 63 and leaving the remaining portion 55 of the second ILD layer 58, the second ILD layer 58 is formed in the second ILD layer 58. A contact hole or via 72 is formed.
[0036]
FIG. 7 shows the interconnect via 65 and the contact hole or via 72 of FIG. 6 after the second conductive plug or contact 85 has been formed by filling the third conductive material. The third conductive material includes any conductive material, especially Cu, W, Al, TiN, Ta or a similar material. Excess third conductive material is removed by etching or CMP known to those skilled in the art. As a result, a flat surface 82 of the electrochemical structure 1 is obtained. This planarization results in a third ILD layer 60 and a surface 82 of a second conductive plug or contact 85. The surface 82 of the second conductive plug or contact 85 extends from the surface 82 to the first conductive plug or contact 46.
[0037]
If the cross-section of the interconnect via 65 and the contact via 72 is rectangular, the height from surface 82 to the first conductive plug or contact 46 in the direction of reference numeral 6 is about 0.2 μm to about 3.7 μm. The width of contact holes or vias 72 (see FIG. 6) in the direction of reference numeral 5 is about 0.7 μm to about 1.2 μm, and the width of interconnect vias 65 (see FIG. 6) in the direction of reference numeral 5 is about 0.17 μm to about 2.9 μm.
[0038]
The second ILD layer 58 and the third ILD layer 60 are combined to form a composite ILD layer. Generally, a composite ILD layer includes at least one stacked ILD layer. Similarly, interconnect vias 65 and contact holes or vias 72 (see FIG. 6) combine to form a composite trench. In general, a composite trench includes at least one successively stacked trench such that successive trenches partially or completely overlap. For example, interconnect vias 65 and contact holes or vias 72 are groups of trenches that overlap at interface 64 (see FIG. 6).
[0039]
The battery 38 in FIG. 7 is an example of the U-type battery described above with reference to FIGS. 20 (a) and 20 (b).
[0040]
Relating the electrochemical structure 1 of FIG. 7 to the integrated circuit 400 of FIG. 1, the battery 38 is at wiring level 900 + J and the second conductive plug or contact 85 is at wiring level 900 + J + 1. Thus, the second conductive plug or contact 85 extends the conductive plug of battery 38 to another wiring level that is electrically connected to at least one electronic device to which battery 38 is to be powered. For example, second conductive plug or contact 85 is similar to conductor 444 of FIG. 1 electrically connecting to FET 410 via conductive metallization 434 of FIG. 1 as described above.
[0041]
8-13 illustrate an apparatus for forming a battery during BEOL integration for use in or on an integrated circuit (eg, integrated circuit 400 described above in connection with FIG. 1) in accordance with an embodiment of the present invention. It is a figure showing a method.
[0042]
FIG. 8 is a front sectional view of an electrochemical structure 71 including an insulating layer 84 including an insulating material 75 and a first conductive plate 88. The insulating layer 84 represents a wiring level (eg, any of the wiring levels 901,..., 900 + N described above in connection with the integrated circuit 400 of FIG. 1). The interconnect level has conductive metallization embedded in a dielectric material. The insulating material is SiO _Two Such as any dielectric material.
[0043]
The insulating layer 84 is typically formed on the electronic device layer 900 or on one of the interconnect levels 901,..., 900 + J,. It is formed using. For example, chemical vapor deposition (CVD) or a similar technique can be used to form the insulating layer 84. The insulating material 75 has flattened SiO. _Two , Glass material (for example, reflowed PSG (phosphosilicate glass)), SiO _Two And silicon nitride, or an insulating material such as a polymer (eg, polyimide). The insulating material 75 is made of silicon nitride (ie, Si _Three N _Four ), Plastic or similar material, Si _Three N _Four And plastics also function as ion barriers to prevent residual ions remaining after processing from contaminating underlying integrated circuit chips, such as electronic device layer 900. This can prevent the underlying integrated circuit from malfunctioning. Residual ions include, inter alia, alkali metal ions such as lithium ions, sodium ions, or chloride ions. The processing includes wet chemical etching and CMP of the surface 82 of the insulating layer 84, among others.
[0044]
The first conductive plate 88 is formed using any method known to those skilled in the art, for example, using the damascene procedure described in Beyer US Pat. No. 5,965,459. The width of the first conductive plate 88 (in the direction of reference numeral 83) is about 0.3 μm to about 5 μm, and the height of the first conductive plate 88 (in the direction of reference numeral 81) is about 0.3 μm. It is about 5 μm.
[0045]
FIG. 9 is a diagram after an etch stop layer 89 is formed on the insulating layer 84 of FIG. 8 and then an interlevel dielectric (ILD) layer 90 is sequentially formed on the etch stop layer 89. Etch stop layer 89 is made of silicon nitride, among others, and is formed using any method known to those skilled in the art, for example, CVD. The etch stop layer 89 functions as a barrier to etching and prevents residual ions from subsequent patterning or planarization steps described below with reference to FIG. 13 from diffusing into the insulating layer 84. The etch stop layer 89 can be formed of a material such as silicon nitride or alumina. The thickness (in the direction of reference numeral 81) of the etch stop layer 89 is between about 0.015 μm and about 0.3 μm. Etch stop layer 9 has a thickness of about 0.015 μm to about 0.3 μm. If the etch stop function of the etch stop layer 89 is unnecessary, the etch stop layer 89 may be omitted. ILD layer 90 is formed on etch stop layer 89 with an interlevel dielectric material including a material such as, for example, sputtered quartz or oxide. The thickness (in the direction of reference numeral 81) of the ILD layer 90 is from about 0.285 μm to about 4.7 μm. Next, a first trench 93 is formed on the ILD layer 90 using the same procedure as described above with reference to FIG. 3A for forming the second trench 13.
[0046]
FIG. 10 shows the ILD layer 90 of FIG. 9, the first wall 102 of the first trench (see FIG. 9), the first conductive plate 88, and the second of the first trench (see FIG. 9). FIG. 10 is a diagram after the first conductive layer 110 is deposited to a uniform thickness of about 0.08 μm to about 1.3 μm on the wall of FIG. As a result of depositing the first conductive layer 110, a second trench 115 is formed in the first conductive layer 110. First conductive layer 110 can be formed of any suitable conductive material for use in forming the electrodes of battery 38 shown in FIG.
[0047]
FIG. 11 shows a uniform thickness of the electrolyte layer 121 on the first wall 122, the second wall 124, and the bottom surface 125 of the second trench 115 of FIG. 10, for example, from about 0.08 μm to about 1.3 μm. FIG. 7 is a view after the film is faithfully deposited on the underlying shape. As a result of depositing the electrolyte layer 121, a third trench 123 is formed in the electrolyte layer 121. The electrolyte layer 121 may be formed by known methods, for example, as described in Bates et al., US Pat. No. 5,338,625 (1994). _Two Li in the atmosphere _Three PO _Four Can be formed using a method of RF magnetron sputtering. The electrolyte layer 121 is formed of an electrolyte material such as lithium phosphorus oxynitride (Lipon) or a similar material.
[0048]
FIG. 12 is a view after the third trench 123 of FIG. 11 is filled with the second conductive material. This filling is performed by depositing a second conductive layer 135 on the electrolyte layer 121.
[0049]
FIG. 13 is a diagram after the portions of the second conductive layer 135, the electrolyte layer 121, and the first conductive layer 110 in FIG. 12 are removed by planarization. This planarization can be performed using any method known to those skilled in the art, such as CMP, as described above in connection with the planarization of the structure 1 shown in FIG. This planarization leaves a remaining portion 152 of the second conductive layer 135, a remaining portion of the electrolyte layer 121, and a remaining portion of the first conductive layer 110 in addition to the conductive contact 165. FIG. 13 shows the remaining portion of the first conductive layer 110 and the remaining portion 152 of the second conductive layer 135 as electrodes (anode and cathode, or cathode and anode, respectively), and the remaining portion of the electrolyte layer 121 as electrolyte. Have. The conductive contact 165 is in conductive contact with the remaining portion 152 of the second conductive layer 135 (see FIG. 12). The height (in the direction of reference numeral 81) of the conductive contact 165 is between about 0.15 μm and about 2.5 μm, and the width (in the direction of reference number 83) is between about 0.04 μm and about 0.7 μm.
The height (in the direction of reference numeral 81) of the remaining portion 152 of the second conductive layer 135 is from about 0.15 μm to about 2.5 μm, and the width (in the direction of reference number 83) is from about 0.1 μm to about 1. 7 μm.
[0050]
The battery 39 is an example of the U-shaped battery with the double extension described above with reference to FIG. If the process of FIG. 10 for forming the first conductive layer 110 is changed to prevent the first conductive layer 110 from being formed on the first wall 102 or the second wall, the battery 39 can be formed as shown in FIG. An example of a U-shaped battery with a single extension as described above in connection with c).
[0051]
The battery 39 is an example of a battery provided with a U-shaped electrolyte because the electrolyte layer 121 has a “U” shape. The U-shaped electrolyte 121 has “arms” 117 and 118 extending in the direction of reference numeral 81. One electrode, the first conductive layer 110, is in contact with the arms 117,118. Thus, battery 39 is considered to be a battery having electrode arm contacts and a U-shaped electrolyte.
[0052]
Associating the electrochemical structure 71 of FIG. 13 with the integrated circuit of FIG. 1, the battery 39 is at wiring level 900 + J, and the first conductive plug 88 is at wiring level 900 + J-1. Accordingly, conductive contacts 165 extend the conductive connection of battery 39 to other wiring levels that are electrically connected to at least one electronic device to which battery 39 is to be powered. For example, conductive contact 165 is similar to conductor 444 of FIG. 1 described above as being electrically connected to source / drain 412 of FET 410 via conductive metallization 434. Similarly, conductive plate 68 is similar to conductor 442 of FIG. 1 electrically connecting to gate 414 of FET 410 via conductive metallization 432.
[0053]
FIG. 14 illustrates the formation of a battery 170 of electrochemical structures 181 during BEOL integration for use in or on an integrated circuit (eg, integrated circuit 400 described above in connection with FIG. 1) according to an embodiment of the present invention. FIG. 2 is a diagram showing an apparatus and a method for performing the method.
[0054]
The electrochemical structure 181 includes a planar battery 170 provided between the first insulating layer 171 and the second insulating layer 180. The first insulating layer 171 includes a first conductive plate 173 electrically connected to a first conductive layer 172 functioning as a first electrode of the planar battery 170. The second insulating layer 180 includes a first conductive plate 182 that is electrically connected to a second conductive layer 176 functioning as a second electrode of the planar battery 170.
[0055]
The first conductive plate 173 can be formed in the first insulating layer 171 by any method known to those skilled in the art. For example, the first conductive plate 173 is formed by the following three steps. In the first step, the first insulating layer 171 is formed on the above-described electronic device layer 900 of FIG. 1 or on the wiring levels 901,..., 900 + N−1 using any method known to those skilled in the art. Is deposited. In the second step, the first portion of the first insulating layer 171 is removed by, for example, RIE to leave the second portion 177 of the first insulating layer 171. As a result, a first trench 178 is formed. In a third step, the first trench is filled with a conductive metal to form a first conductive plate 173. The second conductive plate 182 in the second insulating layer 180 can be formed by a method similar to the method of forming the first conductive plate 173. This includes formation of the second trench 179. First conductive plate 173 and second conductive plate 182 are formed of a conductive metal, including, among others, Cu, W, Al, TiN, Ta, or a similar metal. When the first conductive plate 173 or the second conductive plate 182 includes copper, the first conductive plate 173 or the second conductive plate 182 is damascene copper plated into the trench 178 or 179, respectively. Can be formed.
[0056]
In the planar battery 170, a first conductive layer 172 is deposited over the first insulating layer 171, an electrolyte layer 174 is deposited over the first conductive layer 172, and a second conductive layer 176 is deposited over the electrolyte layer 174. Can be formed. The first conductive layer 172 and the second conductive layer 176 can be formed using an appropriate material depending on the function as an anode or a cathode. The electrolyte layer 174 can be formed of Lipon or a material equivalent thereto. The thickness (in the direction of reference numeral 81) of the first conductive layer 172 and the second conductive layer 176 is about 0.1 μm to about 1.3 μm. The thickness (in the direction of reference numeral 81) of the electrolyte layer 174 is from about 0.04 μm to about 0.7 μm.
[0057]
The planar battery 170 may be fabricated using existing patterning and etching techniques, such as RIE, as known to those skilled in the art, to optimize the battery 170 to the desired characteristics, such as shape, such that the planar battery 170 is integrated with the planar battery 170. It is formed so as to fit in or on the circuit. Bates US Pat. No. 5,567,210 includes lithium / Lipon / V _Two O _Five Performance characteristics related to battery surface area and power are described. Further, by optimizing the shape of the battery 170, the output power of the flat battery 170 can be adapted to the requirements of the application. The output voltage of the battery 170 is controlled by the material of the battery 170 (that is, each material of the first conductive layer 172, the electrolyte layer 174, and the second conductive layer 174) (for example, about 1 to about 1 to about a bias voltage or a reference voltage). A voltage of about 5 volts is supplied).
[0058]
ILD layer 180 can be formed by depositing an interlevel dielectric material, such as sputtered quartz, on second conductive layer 176. The thickness (in the direction of reference numeral 81) of the ILD layer 180 is between about 0.3 μm and about 5 μm. The formation of the surface 311 of the first insulating layer 171 and the surface 312 of the second insulating layer 180 can be performed using any method known to those skilled in the art, for example, the above-described CMP.
[0059]
Battery 170 is an example of the S-type battery described above with reference to FIG.
[0060]
Associating the electrochemical structure 181 of FIG. 14 with the integrated circuit 400 of FIG. 1, the battery 170 is at the wiring level 900 + J, the first conductive layer 173 is at the wiring level 900 + J-1, and the second conductive layer 173 is at the wiring level 900 + J-1. Layer 182 is at wiring level 900 + J + 1. Thus, the first conductive plate 173 and the second conductive plate 182 provide a conductive connection for the battery 170 to other wiring levels electrically connected to at least one electronic device to which the battery 170 is to supply power. Stretched out. For example, the first conductive plate 173 and the second conductive plate 182 are each electrically connected to the FET 410 via the conductive metallization 432 and the conductive metallization 434 of FIG. Similar to conductors 442 and 444 of FIG.
[0061]
15 to 17 are front sectional views of a series-connected battery group according to the embodiment of the present invention. The structure 186 of FIG. 15, the structure 207 of FIG. 16, and the structure 208 of FIG. 17 are different configurations of a battery group that is conductively connected in series. The battery groups of FIGS. 15 to 17 are formed during a BEOL integration step performed during formation of an integrated circuit.
[0062]
FIG. 15 is a front cross-sectional view of an electrochemical structure 186 having a battery 188 and a battery 189 embedded in an insulator 187 in an integrated circuit. Battery 188 and battery 189 are connected in series such that the negative terminal of battery 188 is electrically connected to the positive terminal of battery 189 by conductive interconnects 196, 198, 200. The conductive interconnects 196, 198, 200 can be formed of a conductive metal, including Cu, W, Al, TiN, Ta, or similar metals, among others. Battery 188 and battery 189 may be formed by any of the methods described above (and any of the materials described above) to form battery 38 of FIGS. 2-7, battery 39 of FIGS. 8-13, or battery 170 of FIG. Can be. The conductive plate 194 is in conductive contact with the positive terminal of the battery 188, and the conductive plate 202 is in conductive contact with the negative terminal of the battery 189.
[0063]
Associating the electrochemical structure 186 of FIG. 15 with the integrated circuit 400 of FIG. 1, the battery 188, the battery 189, and the conductive interconnect 198 are at wiring level 900 + J, and the conductive plate 202 and the conductive interconnect 196 are present. Is at interconnect level 900 + J-1, and conductive plate 194 and conductive interconnect 200 are at interconnect level 900 + J + 1. Thus, conductive plate 202 and conductive plate 194 electrically connect the conductive connection of series connected batteries 188, 189 to at least one electronic device to which series connected batteries 188, 189 are to be powered. It has been stretched to the wiring level. For example, conductive plate 202 and conductive plate 194 may each be connected to the above-described conductor 442 of FIG. 1 electrically connected to FET 410 via conductive metallization 432 and conductive metallization 434 of FIG. Similar to conductor 444.
[0064]
FIG. 15 has three wiring levels. Although the batteries 188 and 189 connected in series are at the same wiring level, the battery 188 or the battery 189 may be at the wiring level shown, for example, using at least one conductive interconnect (similar to the conductive interconnect 198). By moving to a lower or higher wiring level, the series connected batteries 188 and 189 can also be relocated to a different wiring level.
[0065]
FIG. 16 is a front cross-sectional view of an electrochemical structure 207 in which the conductive interconnect 198 is replaced by a battery 210 in the electrochemical structure 186 of FIG. The electrochemical structure 207 includes a battery 188, a battery 201, and a battery 189 embedded in an insulator 187 in an integrated circuit. Battery 188, battery 201, and battery 189 have the negative terminal of battery 188 electrically connected to the positive terminal of battery 201 via conductive interconnect 196, and the negative terminal of battery 201 is electrically conductively connected to the positive terminal of battery 189. By being electrically connected at 200, they are connected in series. The conductive interconnects 196, 200 can be formed of a conductive metal, including, inter alia, Cu, W, Al, TiN, Ta, or similar metals. The batteries 188, 201, 189 are formed by any of the methods described above (and any of the materials described above) for forming the battery 38 of FIGS. 2-7, the battery 39 of FIGS. 8-13, or the battery 170 of FIG. be able to. The conductive plate 194 is in conductive contact with the positive terminal of the battery 188, and the conductive plate 202 is in conductive contact with the negative terminal of the battery 189.
[0066]
Associating the electrochemical structure 207 of FIG. 16 with the integrated circuit 400 of FIG. 1, the batteries 188, 201, 189 are at wiring level 900 + J, and the conductive plate 202 and conductive interconnect 196 are at wiring level 900 + J-1. And conductive plate 194 and conductive interconnect 200 are at interconnect level 900 + J + 1. Thus, conductive plate 202 and conductive plate 194 connect the conductive connection of series connected batteries 188, 201, 189 to at least one electronic device to which series connected batteries 188, 201, 189 are to supply power. It extends to other wiring levels that are electrically connected. For example, conductive plate 202 and conductive plate 194 may each be connected to the above-described conductor 442 of FIG. 1 electrically connected to FET 410 via conductive metallization 432 and conductive metallization 434 of FIG. Similar to conductor 444.
[0067]
FIG. 16 has three wiring levels. The series-connected cells 188, 201, 189 are at the same wiring level, but, for example, using at least one conductive interconnect (similar to the conductive interconnect 198), for example, the cells 188, 201, and / or By moving the battery 189 to a wiring level below or above the wiring level shown, the batteries 188, 201, 189 connected in series can also be relocated to a different wiring level. In general, the batteries 188, 201, 189 connected in series may all be at the same wiring level as shown in FIG. 16, or each may be at a different wiring level, or two of the three batteries described above. At the same wiring level, and the third (or remaining) battery can be at a different wiring level.
[0068]
FIG. 17 is a front cross-sectional view of an electrochemical structure 208 including a battery 214, a battery 216, and a battery 218 embedded in an insulator 209 in an integrated circuit. Battery 214, battery 216, and battery 218 are directly connected in series (by contact) without intervening conductive interconnects as shown. Battery 214, battery 216, and battery 218 may be any of the methods described above (and any materials described above) for forming battery 38 of FIGS. 2-7, battery 39 of FIGS. 8-13, or battery 170 of FIG. Can be formed. T-shaped conductive contact 210 is in conductive contact with the positive terminal of battery 214, and H-shaped conductive contact 220 is in conductive contact with the negative terminal of battery 218.
[0069]
Associating the electrochemical structure 208 of FIG. 17 with the integrated circuit 400 of FIG. 1, the batteries 214, 216, 218 are at interconnect level 900 + J and the H-shaped conductive contacts 220 are at interconnect level 900 + J-1. , T-shaped conductive contact 210 is at wiring level 900 + J + 1. Therefore, the H-shaped conductive contact 220 and the T-shaped conductive contact 210 should supply the conductive connection of the series-connected batteries 214, 216, 218, and the series-connected batteries 214, 216, 218 should supply power. It extends to other wiring levels that are electrically connected to at least one electronic device. For example, the H-shaped conductive contact 220 and the T-shaped conductive contact 210 are respectively electrically connected to the FET 410 via the conductive metallization 432 and the conductive metallization 434 of FIG. Similar to conductors 442 and 444 of FIG.
[0070]
The components 221, 222, and 223 of the H-shaped conductive contacts 220 can be formed at different wiring levels. To assign to different wiring levels, components 221, 222 and 223 are assigned to a single wiring level, or components 221 and 222 are assigned to a first wiring level and component 223 is assigned to a second wiring level. Or the component 221 is assigned to the first wiring level, the component 222 is assigned to the second wiring level, and the component 223 is assigned to the third wiring level.
[0071]
The series connection composed of the batteries 218, 216, and 214 in FIG. 17 can be realized by connecting the U-type batteries in series according to the procedures shown in FIGS. To be clear, first, the first conductive layer 110 is named a first conductive layer. 13, in the first step, a first conductive layer (which functions as a first polarity, for example, a positive electrode) is deposited on the ILD layer 90 so as to conform to the underlying shape. In the second step, the electrolyte layer 121 is deposited on the first conductive layer faithfully in the shape of the base. Thus, a trench is formed in the electrolyte layer 121. In the third step, the second conductive layer () is deposited in the trench defined by the electrolyte layer 121 so as to conform to the underlying shape, and includes the first conductive layer, the electrolyte layer 121, and the second conductive layer. To form a first U-shaped battery. It should be noted that each deposition faithful to the underlying shape forms a trench in the deposited layer faithful to the underlying shape as described above for the electrolyte layer 121. To form a second U-type battery in series with the first U-type battery, the following three steps are performed. That is, a third conductive layer (which functions as an electrode of the first polarity) is deposited on the second conductive layer faithfully in the base shape, and a fourth conductive layer (which is formed on the third conductive layer) is formed on the third conductive layer. Function as an electrode of the second polarity) faithfully depositing on the underlying shape. Therefore, the second U-type battery includes a third conductive layer, a second electrolyte layer, and a fourth conductive layer. The three-step process described above can be repeated as many times as necessary. By repeating each of the above three steps, a new U-shaped battery is formed in series with the U-shaped battery previously formed. The last step of forming the U-shaped battery is a step of depositing the underlying shape faithfully. The trench of the electrolyte layer which was finally faithfully deposited in the underlying shape is formed of a conductive material by using a conductive material in FIG. Filling the third trench can be replaced by a filling step by a method similar to the method of forming the second conductive layer 135 in FIG.
[0072]
FIGS. 15, 16, and 17 show two batteries, three batteries, and three batteries connected in series in an integrated circuit, respectively. Any number of batteries are included.
[0073]
FIG. 18 is a front sectional view of an electrochemical structure 240 including a battery 242 and a battery 244 embedded in an insulator 249 in an integrated circuit. Battery 242 and battery 244 are connected in parallel. That is, as shown, the negative terminals of batteries 242, 244 are conductively connected to conductive plate 248, and the positive terminals of batteries 242, 244 are conductively connected to conductive plate 246.
[0074]
Associating the electrochemical structure 240 of FIG. 18 with the integrated circuit 400 of FIG. 1, the batteries 242 and 244 are at wiring level 900 + J, the conductive plate 248 is at wiring level 900 + J-1, and the conductive plate 246 exists at the wiring level 900 + J + 1. Thus, conductive plate 248 and conductive plate 246 electrically connect the conductive connection of batteries 242, 244 connected in parallel to at least one electronic device to which batteries 242, 244 connected in parallel are to be powered. Stretched to other wiring levels. For example, conductive plate 248 and conductive plate 246 may be respectively connected to conductive layer 432 and conductive metallization 434 of FIG. And conductor 444.
[0075]
The electrochemical structure 240 of FIG. 18 with the batteries connected in parallel can also be provided within a single wiring level, such as wiring level 900 + J of FIG.
[0076]
Although FIG. 18 shows two batteries connected in parallel in the integrated circuit, the present invention includes any number of batteries connected in parallel in the integrated circuit.
[Industrial applicability]
[0077]
According to the present invention, since a battery can be formed in an integrated circuit, it is possible to supply a non-standard bias voltage and a non-standard reference voltage according to specific requirements of a specific integrated circuit. The present invention also eliminates the need for extra wiring levels and the need for an external voltage source that requires a large size and volume to supply voltage to an integrated circuit that requires only low power input.
[Brief description of the drawings]
[0078]
FIG. 1 is a front cross-sectional view of an integrated circuit with a battery and conductive metallization, according to an embodiment of the present invention.
FIG. 2 is a front cross-sectional view of a first electrochemical structure including a substrate and a first conductive layer provided in the substrate, according to an embodiment of the present invention.
FIG. 3 (a) Depositing an etch stop layer and a first interlevel dielectric (ILD) layer on the substrate of FIG. 2 and forming a trench in the first ILD layer and the etch stop layer. FIG. 5 is a diagram after the first portion of the first conductive layer is exposed. (B) A diffusion barrier formed by forming the etch stop layer of FIG. 3A on the surface of the first ILD layer, the first and second walls of the second trench, and the surface of the first conductive layer. It is the figure replaced by the film.
FIG. 4 is a diagram showing a state in which an electrolyte layer is faithfully formed on the wall of the second trench and the first portion of the first conductive layer in FIG. FIG. 11 is a view after the third trench is filled with a second conductive material after being obtained.
FIG. 5 is a diagram after the surface of the first ILD layer of FIG. 4 is flattened to remove an extra electrolyte material and an extra second conductive material of the electrolyte layer.
FIG. 6 forms a second ILD layer and a third ILD layer on the surface of the first ILD layer of FIG. 5, and forms interconnect vias and contact holes in the third ILD layer and the second ILD layer; It is a figure after each hole was formed.
FIG. 7 illustrates the interconnect vias and contact holes of FIG. 6 after filling with a third conductive material and removing excess third conductive material by planarization.
FIG. 8 is a front cross-sectional view of a second electrochemical structure with a first conductive plate provided in an insulating layer, according to an embodiment of the present invention.
9 forms an etch stop layer on the insulating layer of FIG. 8, forms a first interlevel dielectric (ILD) layer on the etch stop layer, and forms a first ILD layer and an etch stop layer. FIG. 5 is a view after exposing a portion of the first conductive plate by forming a first trench in FIG.
10 shows a first conductive layer formed on the first wall and the second wall of the first trench of FIG. 9 and the above-mentioned portion of the first conductive plate, the first conductive layer being faithfully conforming to the underlying shape; FIG. 7 is a view after a second trench is obtained in the conductive layer of FIG.
FIG. 11 shows a third trench formed in the electrolyte layer by forming an electrolyte layer on the first, second, and bottom walls of the second trench of FIG. It is a figure after.
FIG. 12 is a view after filling a third trench of FIG. 11 with a second conductive material;
FIG. 13 is a plan view of the surface of the first ILD layer of FIG. 12 to remove the second conductive material, the electrolyte layer, and the portion of the first conductive material, and to remove the conductive portion in the remaining portion of the second conductive material. It is a figure after forming a contact.
FIG. 14 is a front cross-sectional view of a planar battery according to an embodiment of the present invention.
FIG. 15 is a front cross-sectional view of two batteries connected in series, according to an embodiment of the present invention.
FIG. 16 is a front cross-sectional view of three batteries connected in series, according to an embodiment of the present invention.
FIG. 17 is a front cross-sectional view of three batteries connected in series according to an embodiment of the present invention.
FIG. 18 is a front cross-sectional view of three batteries connected in parallel according to an embodiment of the present invention.
FIG. 19 is a view after rotating the battery in FIG. 1 by 90 degrees and adjusting the size of the conductive metallization to fit the rotated battery.
FIG. 20 (a) shows an electrolyte of a U-type battery according to an embodiment of the present invention. (B) It is a figure which shows the U type battery provided with the electrolyte of FIG.20 (a). FIG. 21 (c) is a diagram showing the U-type battery of FIG. 20 (b) after adding an extension.
FIG. 21 is a view showing an S-type battery according to an embodiment of the present invention.
[Explanation of symbols]
[0079]
1 First electrochemical substrate
2 Substrate
3 First trench
4 Surface
5 directions
8 First conductive layer
9 Etch stop layer
10 First ILD layer
12 remaining parts
13 Second trench
15 Second part
17 First part
32 1st wall
34 Second wall
36 surface
38 batteries
41 Electrolyte layer
44 Third Trench
48 First Part
49 Second conductive layer
50 First part
53 Second Part
55 Remaining part
57 surface
58 Second ILD Layer
60 Third ILD layer
62 Remaining part
63 First Mask Layer
64 interface
65 Interconnect Via
71 Electrochemical structure
72 Contact holes or vias
75 Insulation material
82 surface
84 insulating layer
85 Second conductive plug or contact
88 first conductive plate
89 Etch Stop Layer
90 ILD layer
93 First trench
102 First wall
105 Second wall
110 first conductive layer
115 Second trench
121 electrolyte layer
122 First wall
123 Third Trench
124 Second wall
135 second conductive layer
152 Remaining part
165 conductive contact
170 batteries
171 First insulating layer
172 first conductive layer
173 First conductive plate
174 electrolyte layer
176 second conductive layer
178 First Trench
179 Second Trench
180 second insulating layer
181 Electrochemical structure
182 second conductive plate
186 structure
187 insulator
188 battery
189 batteries
194 conductive plate
196 conductive interconnect
198 conductive interconnect
200 conductive interconnect
201 Battery
202 conductive plate
207 Structure
208 Structure
209 Insulator
210 Conductive contact
214 batteries
216 Battery
218 batteries
220 conductive contacts
221 components
222 component
223 component
240 electrochemical structure
242 battery
244 batteries
246 conductive plate
248 conductive plate
249 insulation
311 surface
312 surface
400 integrated circuit
402 Bulk semiconductor wafer
410 Field Effect Transistor (FET)
411 Source / Drain
412 source / drain
413 channels
414 gate
415 Gate insulating film
418 Insulating spacer
420 batteries
422 negative terminal
424 positive terminal
432 Conductive Metallization
434 Conductive Metallization
442 electric conductor
444 electrical conductor
600 electrolyte
602 base
604 arm
606 arm
620 hollow electrode
624 extension
626 Extension
650 U-type battery
670 U-type battery
680 S type battery
682 electrodes
684 electrolyte
686 electrodes
900 Electronic device layer
900 + J-1 wiring level
900 + J wiring level
900 + J + 1 wiring level
900 + N wiring level

Claims (30)

A semiconductor wafer (402);
An electronic device layer (900) including at least one electronic device (410) and formed on the semiconductor wafer;
A plurality of wiring levels (901,..., 900 + N) formed on the electronic device layer comprising a first conductive metallization (432, 442) and a second conductive metallization (444, 434); ,
At least one battery (420) formed in said wiring level;
The first conductive metallization electrically conductively connects a first electrode of the at least one battery to the at least one electronic device, and the second conductive metallization connects a second electrode of the battery. An integrated circuit conductively connected to said at least one electronic device. The wiring level and the at least one battery are formed during BEOL (Back-End-Of-Line) integration of the integrated circuit;
The integrated circuit according to claim 1. The at least one battery is one of a plurality of batteries connected in series;
The integrated circuit according to claim 1. The plurality of batteries connected in series comprises a plurality of U-shaped batteries connected in series,
An integrated circuit according to claim 3. Wherein each pair of the plurality of cells is conductively connected to each other by a conductive interconnect;
An integrated circuit according to claim 3. The plurality of batteries are directly connected to each other,
An integrated circuit according to claim 3. The at least one battery is one of a plurality of batteries connected in parallel;
The integrated circuit according to claim 1. The first conductive metallization comprises a first conductor in conductive contact with the first electrode;
The second conductive metallization comprises a second conductor in conductive contact with the second electrode;
Both a first conductor and a second conductor are inside the wiring level forming the battery;
The integrated circuit according to claim 1. The first conductive metallization comprises a first conductor in conductive contact with the first electrode;
The second conductive metallization comprises a second conductor in conductive contact with the second electrode;
Both the first conductor and the second conductor are outside the wiring level forming the battery;
The integrated circuit according to claim 1. Wherein said at least one battery is a lithium, lithiated vanadium oxide _{(Li 8 V 2 O 5)} , AgI, Ag, and an anode material selected from the group consisting of _{Zn, V 2 O 5, LiMn} 2 O 4, LiCoO 2 , Sn, Pb, and a cathode material selected from the group consisting of Ag;
Wherein the electrolyte of the first battery comprises lithium phosphorus oxynitride;
The integrated circuit according to claim 1. The at least one battery includes one U-shaped battery;
The integrated circuit according to claim 1. The at least one battery includes one S-type battery;
The integrated circuit according to claim 1. Preparing a semiconductor wafer (402);
Forming an electronic device layer (900) including at least one electronic device on the semiconductor wafer;
Forming a plurality of wiring levels (901,..., 900 + N) on the electronic device layer;
Forming a first conductive metallization (432, 442) and a second conductive metallization (434, 444) in the plurality of wiring levels;
Forming at least one battery in the plurality of interconnect levels;
The first conductive metallization electrically connects a first electrode of the at least one battery to the at least one electronic device, and the second conductive metallization includes a second electrode of the at least one battery. Are electrically conductively connected to the at least one electronic device;
A method for forming an integrated circuit. Forming the at least one battery comprises:
Forming an exposed insulating layer at a first wiring level, and forming an exposed first conductive layer in the insulating layer;
Forming an interlevel dielectric (ILD) layer on the exposed first conductive layer and the exposed insulating layer;
Forming a first trench in the ILD layer by removing a portion of the ILD layer exposing a portion of the first conductive layer;
An electrolyte layer is deposited on the ILD layer and the sidewalls of the first trench, and in the first trench on the first conductive layer, faithfully in an underlying shape, and an electrolyte layer defined by the electrolyte layer. Forming two trenches;
Depositing a second conductive material in the second trench and on the electrolyte layer such that the second conductive material overfills the second trench;
After the surface portions of the electrolyte layer and the second conductive material are polished and removed to obtain flat surfaces of the electrolyte layer and the second conductive material, the first conductive layer is used as a first electrode. Forming a U-type battery using the electrolyte layer as an electrolyte and using the second conductive material as a second electrode.
The method according to claim 13. Forming an ILD layer on the exposed first conductive layer and the exposed insulating layer;
Forming an etch stop layer on the exposed first conductive layer and the exposed insulating layer, and forming the ILD layer on the etch stop layer;
The step of forming a first trench in the first ILD layer further comprises:
Removing a portion of the etch stop layer to expose the portion of the first conductive layer,
The method according to claim 14. After the step of forming the first trench,
Depositing a conductive diffusion barrier film on the ILD layer, on sidewalls of the first trench, and on the exposed portion of the first conductive layer, faithfully in an underlying shape;
The process of depositing the electrolyte layer faithfully in the base shape,
Depositing the electrolyte layer on the diffusion barrier layer,
The method according to claim 14. After the step of forming the first trench,
Depositing a diffusion barrier film on the ILD layer, on sidewalls of the first trench, and on the exposed portion of the first conductive layer;
Removing the diffusion barrier film present on the exposed portion of the first conductive layer,
The process of depositing the electrolyte layer faithfully in the base shape,
Depositing the electrolyte layer in the first trench on the diffusion barrier film and on the first conductive layer,
The method according to claim 14. Forming the first conductive metallization and the second conductive metallization,
Forming a composite ILD layer on the planarized surface;
Forming a composite trench in the composite ILD layer to expose a portion of the second conductive material;
Overfilling the composite trench with a third conductive material that is conductively connected to the second conductive material;
Polishing the surface portion of the third conductive material to flatten the surface of the third conductive material to form a conductive contact made of the third conductive material;
The first conductive metallization or the second conductive metallization includes the conductive contact;
The method according to claim 14. Forming the at least one battery comprises forming a first battery;
Forming a first battery, forming a first conductive metallization, and forming a second conductive metallization,
Forming an exposed insulating layer in the first wiring level and forming an exposed conductive plate in the insulating layer;
Forming an interlevel dielectric (ILD) layer on the exposed conductive plate and the exposed insulating layer;
Forming a first trench in the ILD by removing a portion of the ILD layer to expose a portion of the first conductive plate;
A first conductive layer is deposited on the ILD layer, on the side wall of the first trench, and on the exposed portion of the first conductive plate so as to adhere to an underlying shape, and is formed by the first conductive layer. Forming a defined second trench;
Depositing an electrolyte layer on the first conductive layer to form a third trench defined by the electrolyte layer;
Depositing a second conductive material in the third trench and on the electrolyte layer to overfill the third trench with a second conductive material;
Polishing the surface portion of the second conductive material, the electrolyte layer, and the first conductive layer to form a planarized surface including the second conductive material,
The first conductive metallization includes the conductive plate;
The second conductive metallization includes the conductive contact;
Forming a U-shaped battery with a double extension using the first conductive layer as a first electrode, the electrolyte layer as an electrolyte, and the second conductive material as a second electrode;
The method according to claim 13. Forming an exposed insulating layer in the first wiring level and forming an exposed conductive plate in the dielectric layer;
Forming an etch stop layer on the exposed first conductive plate and the exposed insulating layer, and forming the ILD layer on the etch stop layer;
The step of forming a first trench in the ILD layer further comprises:
Removing a portion of the etch stop layer to expose the portion of the first conductive plate.
The method according to claim 19. Forming the at least one battery comprises:
Forming a first battery,
Forming a first battery, forming a first conductive metallization, and forming a second conductive metallization,
Forming an exposed insulating layer in a first interconnect level and forming an exposed first conductive plate in the dielectric;
Forming a first conductive layer on the insulating layer, the first conductive layer being in conductive contact with the first conductive plate;
Forming an electrolyte layer containing an electrolyte material on the first conductive layer;
Forming a second conductive layer on the electrolyte layer,
The second conductive layer includes a second conductive material;
The first conductive metallization includes the first conductive plate;
Forming an S-type battery using the first conductive layer as a first electrode, the electrolyte layer as an electrolyte, and the second conductive layer as a second electrode;
The method according to claim 13. further,
Forming an interlevel dielectric (ILD) layer on the second conductive layer;
Removing a portion of the ILD layer to form a trench in the ILD layer to expose a portion of the second conductive layer;
Overfilling the trench with a third conductive material;
Polishing the surface of the third conductive material to flatten the surfaces of the ILD layer and the third conductive material,
A second conductive plate made of a third conductive material is formed on the flattened surface;
The second conductive plate is in conductive contact with the second conductive layer;
The second conductive metallization includes the second conductive plate;
A method according to claim 21. Forming a plurality of batteries connected in series including at least one battery.
The method according to claim 13. Electrically conductively connecting said plurality of cells by each conductive interconnect.
A method according to claim 23. Including a step of electrically conductively connecting the plurality of batteries directly to each other,
A method according to claim 23. Forming a plurality of batteries connected in parallel including at least one battery.
The method according to claim 13. Forming a first conductive metallization,
Forming a first conductive contact in conductive contact with the first electrode,
Forming a second conductive metallization,
Forming a second conductive contact in conductive contact with the second electrode,
The first conductive contact and the second conductive contact are inside the interconnect level forming the battery;
The method according to claim 13. Forming a first conductive metallization,
Forming a first conductive contact in conductive contact with the first electrode,
Forming a second conductive metallization,
Forming a second conductive contact in conductive contact with the second electrode,
The first conductive contact and the second conductive contact are external to the interconnect level forming the battery;
The method according to claim 13. Forming the at least one battery comprises:
Forming an anode of the battery with an anode material selected from the group consisting of lithium, lithiated vanadium oxide (Li ₈ V ₂ O ₅ ), AgI, Ag, and Zn;
Forming a cathode of the battery with a cathode material selected from the group consisting of V ₂ O ₅ , LiMn ₂ O ₄ , LiCoO ₂ , Sn, Pb, and Ag;
Wherein the electrolyte of the battery comprises lithium phosphorus oxynitride,
29. The method according to one of claims 13 to 28. The step of forming an electronic device layer,
Forming the electronic device layer during FEOL processing of an integrated circuit,
The step of forming the plurality of wiring levels includes:
Forming the interconnect level during BEOL integration of an integrated circuit,
The step of forming a first conductive metallization and a second conductive metallization comprises:
Forming the first conductive metallization and the second conductive metallization during BEOL integration of an integrated circuit,
The step of forming at least one battery includes:
Forming the at least one battery during BEOL integration of an integrated circuit,
The method according to claim 13.

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