JP2004505289A5 - - Google Patents

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Publication number
JP2004505289A5
JP2004505289A5 JP2001549180A JP2001549180A JP2004505289A5 JP 2004505289 A5 JP2004505289 A5 JP 2004505289A5 JP 2001549180 A JP2001549180 A JP 2001549180A JP 2001549180 A JP2001549180 A JP 2001549180A JP 2004505289 A5 JP2004505289 A5 JP 2004505289A5
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JP
Japan
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binary data
bits
tap
providing
linear feedback
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JP2001549180A
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English (en)
Japanese (ja)
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JP4828068B2 (ja
JP2004505289A (ja
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Priority claimed from US09/453,008 external-priority patent/US6763363B1/en
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Publication of JP2004505289A publication Critical patent/JP2004505289A/ja
Publication of JP2004505289A5 publication Critical patent/JP2004505289A5/ja
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Publication of JP4828068B2 publication Critical patent/JP4828068B2/ja
Anticipated expiration legal-status Critical
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JP2001549180A 1999-12-02 2000-12-01 コンピュータで効率的な線形フィードバック・シフト・レジスタ Expired - Fee Related JP4828068B2 (ja)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
US09/453,008 US6763363B1 (en) 1999-12-02 1999-12-02 Computer efficient linear feedback shift register
US09/453,008 1999-12-02
PCT/US2000/032633 WO2001048594A2 (en) 1999-12-02 2000-12-01 Computer efficient linear feedback shift register

Publications (3)

Publication Number Publication Date
JP2004505289A JP2004505289A (ja) 2004-02-19
JP2004505289A5 true JP2004505289A5 (enExample) 2007-09-13
JP4828068B2 JP4828068B2 (ja) 2011-11-30

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ID=23798867

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2001549180A Expired - Fee Related JP4828068B2 (ja) 1999-12-02 2000-12-01 コンピュータで効率的な線形フィードバック・シフト・レジスタ

Country Status (6)

Country Link
US (1) US6763363B1 (enExample)
EP (1) EP1234227A2 (enExample)
JP (1) JP4828068B2 (enExample)
AU (1) AU4900401A (enExample)
CA (1) CA2392706A1 (enExample)
WO (1) WO2001048594A2 (enExample)

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US7860251B1 (en) * 2002-03-26 2010-12-28 National Semiconductor Corporation Encryption-decryption circuit and method of operation
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US7505589B2 (en) * 2003-09-09 2009-03-17 Temarylogic, Llc Ternary and higher multi-value digital scramblers/descramblers
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JP4486961B2 (ja) * 2004-05-24 2010-06-23 株式会社エルイーテック 乱数取出し方法及びこれを用いた乱数生成装置
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US20070088997A1 (en) * 2005-09-26 2007-04-19 Peter Lablans Generation and self-synchronizing detection of sequences using addressable memories
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US9026791B2 (en) 2013-03-11 2015-05-05 Qualcomm Incorporated Linear feedback shift register (LFSR)
JP5786144B2 (ja) 2013-06-18 2015-09-30 パナソニックＩｐマネジメント株式会社 乱数発生装置
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