JP2004502265A5 - - Google Patents
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- Publication number
- JP2004502265A5 JP2004502265A5 JP2002505624A JP2002505624A JP2004502265A5 JP 2004502265 A5 JP2004502265 A5 JP 2004502265A5 JP 2002505624 A JP2002505624 A JP 2002505624A JP 2002505624 A JP2002505624 A JP 2002505624A JP 2004502265 A5 JP2004502265 A5 JP 2004502265A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Withdrawn
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Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| PCT/IL2000/000327 WO2002001570A1 (en) | 2000-06-07 | 2000-06-07 | Call out memory with reduced surface |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2004502265A JP2004502265A (ja) | 2004-01-22 |
| JP2004502265A5 true JP2004502265A5 (https=) | 2004-12-24 |
Family
ID=11042980
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2002505624A Withdrawn JP2004502265A (ja) | 2000-06-07 | 2000-06-07 | 小型コールアウトメモリ |
Country Status (6)
| Country | Link |
|---|---|
| EP (1) | EP1295296A1 (https=) |
| JP (1) | JP2004502265A (https=) |
| CN (1) | CN1375102A (https=) |
| AU (1) | AU5098900A (https=) |
| IL (1) | IL147999A0 (https=) |
| WO (1) | WO2002001570A1 (https=) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9275734B2 (en) | 2010-02-18 | 2016-03-01 | Katsumi Inoue | Memory having information refinement detection function by applying a logic operation in parallel for each memory address to the match/mismatch results of data items and memory addresses, information detection method using memory, and memory address comparison circuit for the memory |
| EP4557513A3 (en) * | 2013-05-15 | 2025-07-30 | TactoTek Oy | Enabling arrangement for an electronic device with housing-integrated functionalities and method therefor |
| US12025707B2 (en) | 2018-08-07 | 2024-07-02 | Groundprobe Pty Ltd | Wall visualisation from virtual point of view |
Family Cites Families (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3140695B2 (ja) * | 1996-10-17 | 2001-03-05 | 川崎製鉄株式会社 | 連想メモリ装置 |
| AU1092599A (en) * | 1997-10-30 | 1999-05-24 | Netlogic Microsystems, Inc. | Synchronous content addressable memory with single cycle operation |
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2000
- 2000-06-07 EP EP00935450A patent/EP1295296A1/en not_active Withdrawn
- 2000-06-07 CN CN00812567.8A patent/CN1375102A/zh active Pending
- 2000-06-07 AU AU50989/00A patent/AU5098900A/en not_active Abandoned
- 2000-06-07 JP JP2002505624A patent/JP2004502265A/ja not_active Withdrawn
- 2000-06-07 WO PCT/IL2000/000327 patent/WO2002001570A1/en not_active Ceased
- 2000-06-07 IL IL14799900A patent/IL147999A0/xx unknown