JP2004500623A5 - - Google Patents
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- Publication number
- JP2004500623A5 JP2004500623A5 JP2001525526A JP2001525526A JP2004500623A5 JP 2004500623 A5 JP2004500623 A5 JP 2004500623A5 JP 2001525526 A JP2001525526 A JP 2001525526A JP 2001525526 A JP2001525526 A JP 2001525526A JP 2004500623 A5 JP2004500623 A5 JP 2004500623A5
- Authority
- JP
- Japan
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19945494 | 1999-09-22 | ||
| DE10018722A DE10018722A1 (de) | 1999-09-22 | 2000-04-15 | Verfahren und Schaltungsanordnung zum Speichern von Datenworten in einem RAM Modul |
| PCT/EP2000/008398 WO2001022225A1 (de) | 1999-09-22 | 2000-08-29 | Verfahren und schaltungsanordnung zum speichern von datenworten in einem ram modul |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JP2004500623A JP2004500623A (ja) | 2004-01-08 |
| JP2004500623A5 true JP2004500623A5 (enExample) | 2007-12-20 |
Family
ID=26005322
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2001525526A Pending JP2004500623A (ja) | 1999-09-22 | 2000-08-29 | Ｒａｍモジュールにデータ語を記憶する方法と回路装置 |
Country Status (4)
| Country | Link |
|---|---|
| US (1) | US6901552B1 (enExample) |
| EP (1) | EP1222545B1 (enExample) |
| JP (1) | JP2004500623A (enExample) |
| WO (1) | WO2001022225A1 (enExample) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE10109449B4 (de) * | 2000-08-02 | 2012-11-08 | Continental Teves Ag & Co. Ohg | Verfahren und Schaltungsanordnung zur Speicherung von Prüfbit-Worten |
| US20040148559A1 (en) * | 2003-01-23 | 2004-07-29 | Fetzer Eric S. | Method and circuit for reducing silent data corruption in storage arrays with no increase in read and write times |
| DE102005027455A1 (de) * | 2005-06-14 | 2006-12-28 | Infineon Technologies Ag | Verfahren und Schaltungsanordnung zur Fehlererkennung in einem Datensatz |
| EP1748374A1 (fr) * | 2005-07-08 | 2007-01-31 | STMicroelectronics SA | Procédé et dispositif de protection d'une mémoire contre les attaques par injection d'erreur |
| US7447948B2 (en) * | 2005-11-21 | 2008-11-04 | Intel Corporation | ECC coding for high speed implementation |
| US8589737B2 (en) * | 2008-06-20 | 2013-11-19 | Freescale Semiconductor, Inc. | Memory system with redundant data storage and error correction |
| EP2294581B1 (en) * | 2008-06-20 | 2013-01-09 | Freescale Semiconductor, Inc. | A system for distributing available memory resource |
| FR3078439A1 (fr) * | 2018-02-27 | 2019-08-30 | Stmicroelectronics (Rousset) Sas | Procede de gestion du routage de transactions entre des equipements sources, au moins un equipement cible, par exemple une memoire multiports, et systeme sur puce correspondant |
| EP3683679A1 (en) * | 2019-01-15 | 2020-07-22 | ARM Limited | Checksum generation |
| KR102871983B1 (ko) * | 2019-12-30 | 2025-10-16 | 삼성전자주식회사 | 안전 민감 데이터의 무결성 점검 장치 및 이를 포함하는 전자 기기 |
| US11694761B2 (en) * | 2021-09-17 | 2023-07-04 | Nxp B.V. | Method to increase the usable word width of a memory providing an error correction scheme |
Family Cites Families (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| IT1002271B (it) | 1973-12-27 | 1976-05-20 | Honeywell Inf Systems | Perfezionamento ai dispositivi di controllo di parita nelle memorie a semiconduttori |
| US4277844A (en) * | 1979-07-26 | 1981-07-07 | Storage Technology Corporation | Method of detecting and correcting errors in digital data storage systems |
| US4384353A (en) | 1981-02-19 | 1983-05-17 | Fairchild Camera And Instrument Corp. | Method and means for internal error check in a digital memory |
| JP2642094B2 (ja) * | 1985-05-20 | 1997-08-20 | 日本電信電話株式会社 | 半導体記憶装置 |
| US4710934A (en) | 1985-11-08 | 1987-12-01 | Texas Instruments Incorporated | Random access memory with error correction capability |
| DE68926410T2 (de) | 1988-06-24 | 1996-09-12 | Nippon Electric Co | Mit einer Paritätsteuerungseinheit auf demselben Chip bestückter Mikroprozessor |
| JPH08115268A (ja) * | 1994-10-13 | 1996-05-07 | Toshiba Corp | メモリ回路装置 |
| JPH09167120A (ja) * | 1995-12-15 | 1997-06-24 | Denso Corp | 記憶装置の誤り訂正装置 |
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2000
- 2000-08-29 EP EP00956493A patent/EP1222545B1/de not_active Expired - Lifetime
- 2000-08-29 JP JP2001525526A patent/JP2004500623A/ja active Pending
- 2000-08-29 WO PCT/EP2000/008398 patent/WO2001022225A1/de not_active Ceased
- 2000-08-29 US US10/088,957 patent/US6901552B1/en not_active Expired - Fee Related