JP2004363966A - Signal switching device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To conduct signal switching without causing glitzy noise in a selection circuit selecting a signal complying with a switching signal from a plurality of input signals for outputting the signal. <P>SOLUTION: A switching signal decoding means 30 suspends the output except the signal selected by the switching signal 11. Thus, easy detection is available to the low level of the input signal developed when the switching signal 11 has fluctuation. Furthermore, when the switching signal has the fluctuation, a switching signal comparison means 40 adds a delay value to a control signal 41, outputting a suspension control signal 41a. Consequently, the glitzy noise in switching the signal is prevented from propagation to an output signal 63. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a signal switching device, and more particularly, to a circuit for performing signal switching without generating glitch noise in a signal switching device that selects and outputs a signal corresponding to a switching signal from a plurality of input signals. .
[0002]
[Prior art]
FIG. 5 shows a conventional selection circuit. In FIG. 5, reference numerals 60a and 60b denote input signals to be selected, 61 denotes a switching signal, and 62 denotes a clock for a control circuit. The flip-flop 12 for holding the switching signal samples the signal 65 that is the NOR result of the input signals 60a and 60b with the control circuit clock, and when the signal 65 is at a high level, that is, when the input signals 60a and 60b are When both are at the low level, the switching signal 61 is taken in. Therefore, since the select signal 65 of the selector 64 changes only when both the input signals 60a and 60b are at the low level, generation of glitch noise at the time of selector switching can be prevented (for example, described in Patent Document 1).
[0003]
[Patent Document 1]
JP-A-3-191611
[Problems to be solved by the invention]
In the circuit configuration of such a conventional selection circuit, as the number of input signals to be selected increases, the probability that all signals become low level decreases. Depending on the combination of input signals, there is no time at which all signals become low level, so that the flip-flop 12 cannot capture the switching signal 61.
[0005]
Furthermore, since the control circuit clock 63 and the switching signal 61 change in an asynchronous relationship, the switching signal 61 in a multi-bit configuration may take in a transient switching signal. There was sex.
[0006]
The present invention has been made in view of the above-described conventional problems, and makes it easy to detect the low level of the input signal when the switching signal changes, and also when the switching signal changes. It is another object of the present invention to provide a signal switching device that does not cause grid noise at the time of signal switching to propagate to an output signal and does not need to increase the speed of a control circuit clock.
[0007]
[Means for Solving the Problems]
In order to solve the above problem, a signal switching device according to claim 1 of the present invention is a signal switching device that selects and outputs a signal corresponding to a switching signal from a plurality of first to n-th input signals, A first-stage switching signal synchronization unit A and a second-stage switching signal synchronization unit B for synchronizing the switching signals, and a switching signal synchronized by the switching signal synchronization unit A, A switching signal decoding unit that decodes based on the change bit information, and one signal from the first to n-th input signals is synchronized by the decoding signal from the switching signal decoding unit and the switching signal synchronization unit A Input signal selecting means for selecting according to the converted switching signal, and the output of the first and second switching signal synchronizing means for detecting a change in the switching signal and having a width of a stop period. Switching signal comparing means for outputting a stop control signal, and output signal stopping means for stopping output of a signal from the input signal selecting means as a device output signal by a stop control signal output from the switching signal comparing means. It is characterized by having the following.
[0008]
A signal switching device according to a second aspect of the present invention is the signal switching device according to the first aspect, wherein the stop control signal output from the switching signal comparing means is not the same at both inputs by the switching signal comparing means. The comparison result at this time is characterized as having a required delay width.
[0009]
In the present invention, switching signal change bit information is decoded by the switching signal decoding means, and only one input signal is selected from the first to n-th input signals, and the state of all input signals is selected. The first synchronizing means A detects the time when all the signals become low level, and when the low level of all the input signals is detected, a switching signal is issued and the input signal is switched. The comparing means issues a stop control signal based on a change in the state of the switching signal of both outputs of the first-stage synchronization circuit A and the second-stage synchronization circuit B, and the selected signal is controlled by the stop control signal. The output signal of the signal switching device is output.
[0010]
According to the above configuration, since signals other than the selected signal are stopped, it is easy to detect the low level of the input signal when the switching signal changes. Further, when the switching signal changes, a stop control signal is output by the switching signal comparison means, so that no grid noise during signal switching propagates to the output signal. Therefore, it is easy to detect that the input signal is at the low level, and it is possible to obtain a signal switching device that does not need to increase the speed of the control circuit clock.
[0011]
BEST MODE FOR CARRYING OUT THE INVENTION
(Embodiment 1)
Hereinafter, a signal switching device according to a first embodiment of the present invention corresponding to claims 1 and 2 will be described.
FIG. 1 is a block diagram of a signal switching device according to Embodiment 1 of the present invention.
In FIG. 1, a first-stage synchronizing means A10 outputs a post-A synchronization switching signal 11 in which the switching signal 61 is synchronized with the control circuit clock CK. The switching signal 11 after the synchronization A is decoded by the switching signal decoding unit 30, and outputs the decoded signal 31 to the input signal selection unit 50. The decode signal 31 has a low level except for a signal selected from any of the input signals 60a, 60b, 60c, and 60d to be selected. The selected signal is output to the output signal stopping means 60 as the selected signal 52.
[0012]
The second-stage synchronizing means B20 outputs the post-Synchronization-B switching signal 21 synchronized with the falling edge of the post-selection signal 52. The switching signal comparing means 40 generates a control signal 41 from the state of the switching signal 11 after synchronization A and the state of the switching signal 21 after synchronization B, and further adds a delay value to the control signal 41 to generate a stop control signal 41a. Which is output to the output signal stopping means 60. The output signal stopping means 60 outputs the output signal 63 based on the post-selection signal 52 and the stop control signal 41a.
[0013]
FIG. 2 is a circuit diagram embodying Embodiment 1 of the present invention shown in FIG. 1, FIG. 3 is an output value 41 of each state of the comparison circuit 40 shown in FIG. 2, and FIG. 2 is a timing chart of the circuit shown in FIG. As shown in FIG.
[0014]
In FIG. 2, the flip-flop 12 of the synchronization means A10 receives the switching signal 61 as a data input and the switching control signal 65 as an enable control input, and outputs a switching signal 11 after synchronization A. The clock CK62 for the control circuit is connected to the clock input of the flip-flop 12, and operates in synchronization with the rising edge of the clock CK62 for the control circuit and when the switching control signal 65 as the enable control is at a low level.
[0015]
After the synchronization A, the switching signal 11 is decoded by the switching signal decoding unit 30, and the decoded signal 31 is controlled by the input signal selection unit 50 on the plurality of input signals 60 a to 60 d. That is, in the input signal selection means 50, the selectors 54, 55, and 56 are controlled by the post-A switching signal 11 generated from the switching signal 61 so that only the selected signal among the input signals 60a to 60d is output. The other input signals among the input signals that are output are all at the low level.
[0016]
The post-synchronization-A switching signal 11 is input as a data input to the flip-flop 22 constituting the synchronizing means B20, and the flip-flop 22 is synchronized with the falling edge of the post-selection signal 52 to perform synchronization. The switch signal 21 after B is output.
[0017]
The switching signal comparing means 40 outputs a high level as a control signal 41 if the value of the switching signal 11 after synchronization A and the value of the switching signal 21 after synchronization B match, and outputs a low level if the values are different. The control signal 41 detected by the switching signal comparison means 40, that is, the comparison result when both inputs are not the same is generated as the stop control signal 41 having a required delay width. The output signal stopping means 60 is constituted by an AND circuit 51, and the post-selection signal 52 selected by the input signal selecting means 50 is output from the signal switching apparatus by the stop control signal 41 from the switching signal comparing means 40. Stop being output as a signal. As a result, when the switching signal 61 (11) changes, the stop signal 41a is output by the switching signal comparing means 40, and the output of the post-selection signal 52 as the output signal of the apparatus is stopped. In addition, the grid noise at the time of signal switching does not propagate to the output signal. Therefore, it is easy to detect that the input signal is at the low level, and it is possible to obtain a signal switching device that does not need to speed up the control circuit clock.
[0018]
In the signal switching device according to the first embodiment, one signal from the plurality of input signals 60a to 60d is synchronized by the decoding signal 31 from the switching signal decoding unit 30 and the switching signal synchronization unit A10. A change in the switching signal is detected from the output of the input signal selecting means 50 for selecting according to the switching signal 11 and the output of the first and second switching signal synchronizing means 10 and 20, and the control signal 41 is further changed. A switch signal comparing means 40 for issuing a stop control signal 41a to which a delay value is added, and a stop control signal 41a from the switch signal comparing means 40, the output from the input signal selecting means 50 is switched to the main signal. Since output signal stopping means 60 for stopping output as an output signal of the apparatus is provided, output is stopped except for the selected signal. Therefore, it becomes possible to easily detect the low level of the input signal when the switching signal changes, and when the switching signal changes, a stop control signal is output by the switching signal comparison means. No grid noise propagates to the output signal. Therefore, it is easy to detect that the input signal is at a low level, and it is possible to obtain a signal switching device that does not need to increase the speed of the control circuit clock.
[0019]
It should be noted that the present invention is not limited to the configuration of the above embodiment, but can be adapted to any configuration of the multi-input multi-output selection circuit by changing the configuration of the selection circuit control means.
[0020]
【The invention's effect】
As described above, according to the signal switching circuit of the present invention, in a signal switching device that selects and outputs a signal corresponding to a switching signal from a plurality of first to n-th input signals, the switching signal is synchronized. A first-stage switching signal synchronization unit A, a second-stage switching signal synchronization unit B, and a switching signal synchronized by the switching signal synchronization unit A are decoded by switching signal change bit information. Switching signal decoding means, a signal from the first to n-th input signals, a decoding signal from the switching signal decoding means, and a switching signal synchronized by the switching signal synchronization means A. The change of the switching signal is detected from the output of the input signal selecting means for selecting the switching signal according to the first and second stages and the switching signal synchronizing means of the first and second stages, and the stop control signal having the width of the stop period is output. Switching signal comparing means, and output signal stopping means for stopping output of a signal from the input signal selecting means as a device output signal by a stop control signal output from the switching signal comparing means. Therefore, when only one input signal is selectively output from a plurality of input signals by the switching signal decoding means and the input signal selection means, the output of the signal other than the selected signal is stopped, It is possible to easily detect the low level of the input signal when the switching signal changes. In addition, when the switching signal changes, the output of the output signal is controlled to be stopped by the switching signal comparison means, so that it is possible to prevent the propagation of glitch noise to the output signal. As a result, it is possible to obtain a signal switching device that can easily detect that the input signal is at a low level and does not need to speed up the control circuit clock.
[Brief description of the drawings]
FIG. 1 is a block diagram of a signal switching device according to a first embodiment of the present invention; FIG. 2 is a circuit diagram of a circuit embodying the signal switching device of the first embodiment; FIG. FIG. 4 is a table showing an output value 41 in each state of the comparison circuit in the circuit. FIG. 4 is a timing chart of the embodied circuit shown in FIG. 2. FIG. 5 is a circuit diagram of a conventional signal switching device.
10 Synchronization means A,
11 Switching signal after synchronization A 20 Synchronization means B,
21 switching signal after synchronization B 30 switching signal decoding means,
31 decode signal 40 switching signal comparing means,
41 control signal (stop control signal)
50 input signal selection means,
52 Post-selection signal 60 Output signal stopping means 60a, 60b, 60c, 60d Input signal 61 Switching signal 63 Output signal 65 Switching control signal

Claims (2)

In a signal switching device for selecting and outputting a signal corresponding to a switching signal from a plurality of first to n-th input signals,
A first-stage switching signal synchronization unit A and a second-stage switching signal synchronization unit B for synchronizing the switching signals;
A switching signal decoding unit for decoding the switching signal synchronized by the switching signal synchronization unit A using switching signal change bit information;
An input for selecting one signal from the plurality of first to n-th input signals in accordance with the decoded signal from the switching signal decoding unit and the switching signal synchronized by the switching signal synchronization unit A; Signal selection means;
Switching signal comparing means for detecting a change in the switching signal from an output of the first and second switching signal synchronizing means and outputting a stop control signal having a width of a stop period;
A stop control signal output from the switching signal comparing means, the signal from the input signal selecting means, output signal stopping means for stopping output as a device output signal,
A signal switching device characterized by the above-mentioned. The signal switching device according to claim 1,
The stop control signal output from the switching signal comparison means is a comparison result obtained when the two inputs by the switching signal comparison means are not the same, and has a required delay width.
A signal switching device characterized by the above-mentioned.

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