JP2004363740A - Level shifter - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce current consumption by supplying no through current even if input of a circuit of a high-voltage source system becomes unstable when a low-voltage side power source is turned off while the high-voltage side power source is held ON. <P>SOLUTION: An input signal from a low-voltage power source system signal input terminal 100A is passed through a capacitor 102, passed through an inverting circuit 101, and passed through a capacitor 103 to generate spike waves with a trailing edge and a leading edge of the input signal, and a data latch circuit 109 is set and reset with those spike waves, and also pull up other-end sides of the capacitors 102 and 103 to the voltage of the high-voltage power source system by P channel MOS transistors 105 and 106 for pull-up. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a level shifter used as an interface between circuits having different power supply voltages in a semiconductor circuit device.
[0002]
[Prior art]
Conventionally, in a level shifter, a non-inverted signal and an inverted signal of an input signal on a low-voltage power supply side are respectively input to the gate of an N-channel MOS transistor on a high-voltage power supply side to control the voltage. Shift levels.
[0003]
Hereinafter, the operation of the conventional level shifter will be described in detail with reference to FIG.
[0004]
In FIG. 7, reference numeral 400 denotes a conventional level shifter. 400A is a low-voltage power supply signal input terminal to which an input signal whose level changes between a low-voltage power supply potential and a ground potential is supplied. 400B is a high-voltage power supply signal output terminal where an output signal whose level changes between the high-voltage power supply potential and the ground potential appears. S400A is an input signal of a level shifter having a low-voltage power supply amplitude. S400B is an output signal of a level shifter having a high-voltage power supply amplitude.
[0005]
404 is a high voltage power supply terminal. Reference numerals 401 and 402 denote inverting circuits of a low-voltage power supply system. S401 is a signal output from the inversion circuit 401. S402 is a signal output from the inversion circuit 402. 403 and 404 are N-channel MOS transistors. Reference numerals 405 and 406 denote P-channel MOS transistors whose sources are connected to the high-voltage power supply terminal 104. 408 is a ground terminal.
[0006]
S403 is a signal at a connection point between the drain of the P-channel MOS transistor 405 and the drain of the N-channel transistor 403. S404 is a signal at a connection point between the drain of the P-channel MOS transistor 406 and the drain of the N-channel transistor 404. Reference numeral 407 denotes an inverting circuit of a high voltage power supply system.
[0007]
The operation of the level shifter having the above configuration will be described with reference to the timing chart of FIG. Input signal S400A at timing T ₀ , The signal S401 goes low and the signal S402 goes high. Therefore, the N-channel MOS transistor 403 is turned on by the signal S402, and the N-channel MOS transistor 404 is turned off by the signal S401.
[0008]
When the N-channel MOS transistor 403 is turned on, the connection point between the N-channel MOS transistor 403 and the P-channel MOS transistor 405 becomes conductive with the ground terminal 408, and the voltage of the signal S403 gradually changes to a low level. Timing T ₁ When the signal S403 turns on the P-channel MOS transistor 406, the N-channel MOS transistor 404 is turned off by the signal S401 at this time, so that the signal S404 changes to high level.
[0009]
When the signal S404 changes to a high level, the P-channel MOS transistor 405 is turned off, and the signal S403 is fixed at a low level. Therefore, the output signal S400B is changed to a high level by the inversion circuit 407.
[0010]
Next, the input signal S400A is set at the timing T. ₂ , The signal S401 goes high and the signal S402 goes low. Therefore, the N-channel MOS transistor 403 is turned off by the signal S402, and the N-channel MOS transistor 404 is turned on by the signal S401.
[0011]
When the N-channel MOS transistor 404 is turned on, the connection point between the N-channel MOS transistor 404 and the P-channel MOS transistor 406 becomes conductive with the ground terminal 408, and the voltage of the signal S404 gradually changes to a low level. Timing T ₃ When the signal S404 turns on the P-channel MOS transistor 405, the signal S403 changes to a high level because the N-channel MOS transistor 403 is turned off by the signal S402 at this time.
[0012]
When the signal S403 changes to a high level, the P-channel MOS transistor 406 is turned off, and the signal S404 is fixed at a low level. Therefore, the output signal S400B is changed to a low level by the inversion circuit 407.
[0013]
With the above operation, the voltage level of the signal is shifted (for example, see Patent Document 1).
[0014]
[Patent Document 1]
JP-A-7-193488 (page 2, FIG. 2)
[0015]
[Problems to be solved by the invention]
However, in the conventional level shifter, if the power supply on the low voltage side is turned off while the power supply on the high voltage side is turned on, the input becomes unstable, and the N-channel MOS transistors 403 and 403 and the P-channel transistors 405 and 406 are turned on. Therefore, there is a problem that a through current always flows, and current consumption increases.
[0016]
The present invention has been made in view of this problem, and its purpose is to keep the power supply on the high voltage side turned on, and turn off the power supply on the low voltage side, without passing through current, An object of the present invention is to provide a level shifter capable of reducing current consumption.
[0017]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a level shifter including: a low-voltage power supply system signal input terminal to which an input signal whose level changes between a low-voltage power supply potential and a ground potential is supplied; , A first capacitor having one end connected to the low-voltage power supply system signal input terminal, a first capacitor having one end connected to the high-voltage power supply terminal and the other end connected to the first capacitor. A first pull-up resistor connected to one end, a second capacitor having one end connected to the output terminal of the inverting circuit, and one end connected to the high-voltage power supply terminal and the other end connected to the other end of the second capacitor. A connected second pull-up resistor and a data latch circuit that is reset when the signal at the other end of the first capacitor goes to a low voltage level and is set when the signal at the other end of the second capacitor goes to a low voltage level And the data Connected to the output terminal of the latch circuit and a high voltage power supply system signal output terminal.
[0018]
According to this configuration, the input signal from the low-voltage power supply system signal input terminal is passed through the first capacitor, and is passed through the second capacitor via the inverting circuit, so that the falling edge and the rising edge of the input signal are obtained. A spike wave is generated at each edge, the data latch circuit is set and reset by these spike waves, and the other ends of the first and second capacitors are connected to a high voltage power supply by first and second pull-up resistors. Since the voltage is pulled up to the system voltage, a through current can be prevented from flowing even when the low-voltage side power supply is turned off and the input becomes unstable. As a result, current consumption can be reduced.
[0019]
The level shifter according to a second aspect of the present invention is the level shifter according to the first aspect, wherein the first pull-up resistor is connected to the high voltage power supply terminal while the anode is connected to the other end of the first capacitor. A first diode is provided in parallel, and a second diode is provided in parallel with the second pull-up resistor in a state where the cathode is connected to the high voltage power supply terminal and the anode is connected to the other end of the second capacitor. .
[0020]
According to this configuration, since the first and second diodes are connected in anti-parallel to the first and second pull-up resistors, the voltage at the other ends of the first and second capacitors is equal to or higher than the high-voltage power supply. Voltage can be prevented. As a result, the semiconductor voltage can be suppressed within the guaranteed voltage range, and the semiconductor can be prevented from being broken.
[0021]
A level shifter according to a third aspect of the present invention is the level shifter according to the first or second aspect, in response to a reset control signal input between the low voltage power supply system signal input terminal and the inverting circuit and the first capacitor. A reset that inverts an input signal from the low-voltage power supply system signal input terminal and supplies it to the inverting circuit and one end of the first capacitor, and passes the input signal from the low-voltage power supply system signal input terminal as it is when no reset control signal is input A control circuit is provided.
[0022]
According to this configuration, even if the level of the input signal of the low-voltage power supply system signal input terminal does not match the level of the output signal of the high-voltage power supply system signal output terminal due to malfunction due to noise or the like, the reset control circuit resets the signal. By inputting a control signal, both signals can be matched.
[0023]
A level shifter according to a fourth aspect of the present invention is the level shifter according to the third aspect, wherein the level shifter detects a level mismatch between an input signal from a low voltage power supply system signal input terminal and an output signal from a high voltage power supply system signal output terminal. A reset control signal generation circuit for automatically generating a reset control signal is provided.
[0024]
According to this configuration, by providing the reset control signal generation circuit, the reset control is performed by detecting a mismatch between the level of the input signal from the low voltage power supply system signal input terminal and the level of the output signal from the high voltage power supply system signal output terminal. A signal can be generated automatically, and when the level of the input signal at the low voltage power system signal input terminal and the level of the output signal at the high voltage power system signal output terminal do not match, the two signals are matched. be able to.
[0025]
According to a fifth aspect of the present invention, there is provided a level shifter, comprising: a low voltage power supply system signal input terminal to which an input signal whose level changes between a low voltage power supply potential and a ground potential is supplied; and an input terminal connected to the low voltage power supply system signal input terminal. , A first capacitor having one end connected to the low-voltage power supply system signal input terminal, one end connected to the ground terminal, and the other end connected to the other end of the first capacitor. A first pull-down resistor connected thereto, a second capacitor having one end connected to the output terminal of the inverting circuit, and a second capacitor having one end connected to the ground terminal and the other end connected to the other end of the second capacitor. A data latch circuit that is set when a signal at the other end of the first capacitor goes to a high voltage level, and is reset when a signal at the other end of the second capacitor goes to a high voltage level; And a high voltage power supply system signal output terminal connected to the output terminal of the circuit.
[0026]
According to this configuration, the input signal from the low-voltage power supply system signal input terminal is passed through the first capacitor, and is passed through the second capacitor via the inverting circuit, so that the falling edge and the rising edge of the input signal are obtained. Each spike wave is generated at the edge, the data latch circuit is set and reset by these spike waves, and the other ends of the first and second capacitors are pulled down to ground potential by first and second pull-down resistors. Therefore, even if the low-voltage-side power supply is turned off and the input becomes unstable, it is possible to prevent a through current from flowing. As a result, current consumption can be reduced.
[0027]
The level shifter according to claim 6 of the present invention is the level shifter according to claim 5, wherein the anode is connected to the ground terminal and the cathode is connected to the other end of the first capacitor in parallel with the first pull-down resistor. One diode is provided, and a second diode is provided in parallel with the second pull-down resistor with the anode connected to the ground terminal and the cathode connected to the other end of the second capacitor.
[0028]
According to this configuration, since the first and second diodes are connected in anti-parallel to the first and second pull-down resistors, the voltage at the other ends of the first and second capacitors is equal to or higher than the high-voltage power supply. Can be prevented. As a result, the semiconductor voltage can be suppressed within the guaranteed voltage range, and the semiconductor can be prevented from being broken.
[0029]
A level shifter according to a seventh aspect of the present invention is the level shifter according to the fifth or sixth aspect, in response to the input of the reset control signal between the low voltage power supply system signal input terminal and the inverting circuit and the first capacitor. A reset that inverts an input signal from the low-voltage power supply system signal input terminal and supplies it to the inverting circuit and one end of the first capacitor, and passes the input signal from the low-voltage power supply system signal input terminal as it is when no reset control signal is input A control circuit is provided.
[0030]
According to this configuration, even if the level of the input signal of the low-voltage power supply system signal input terminal does not match the level of the output signal of the high-voltage power supply system signal output terminal due to malfunction due to noise or the like, the reset control circuit resets the signal. By inputting a control signal, both signals can be matched.
[0031]
The level shifter according to claim 8 of the present invention is the level shifter according to claim 7, which detects a mismatch between the level of the input signal from the low voltage power supply system signal input terminal and the level of the output signal from the high voltage power supply system signal output terminal. A reset control signal generation circuit for automatically generating a reset control signal is provided.
[0032]
According to this configuration, by providing the reset control signal generation circuit, the reset control is performed by detecting a mismatch between the level of the input signal from the low voltage power supply system signal input terminal and the level of the output signal from the high voltage power supply system signal output terminal. A signal can be generated automatically, and when the level of the input signal at the low voltage power system signal input terminal and the level of the output signal at the high voltage power system signal output terminal do not match, the two signals are matched. be able to.
[0033]
A level shifter according to a ninth aspect of the present invention has a low voltage power supply system signal input terminal to which an input signal whose level changes between a low voltage power supply potential and a ground potential is supplied, and one end connected to the low voltage power supply system signal input terminal. A connected capacitor, a first inverting circuit of a high voltage power supply system having an input terminal connected to the other end of the capacitor, and a second inverting circuit of a high voltage power supply system having an input terminal connected to an output terminal of the first inverting circuit. 2 inverting circuit, a P-channel MOS transistor having a source connected to the high-voltage power supply terminal, a gate connected to the output terminal of the first inverting circuit, a drain connected to the other end of the capacitor, and a source connected to the ground terminal An N-channel MOS transistor having a gate connected to the output terminal of the first inversion circuit and a drain connected to the other end of the capacitor; and a high-voltage transistor connected to the output terminal of the second inversion circuit. And a power supply system signal output terminal.
[0034]
According to this configuration, a positive feedback circuit is formed by the first inverting circuit, the P-channel MOS transistor, and the N-channel MOS transistor, and a change in an input signal from the low voltage power supply system signal input terminal is transmitted to the positive feedback circuit through the capacitor. Since the input is performed, the level of the input terminal of the positive feedback circuit is fixed by the N-channel MOS transistor, and even if the low-voltage side power supply is turned off and the input becomes unstable, a through current can be prevented from flowing. . As a result, current consumption can be reduced. Moreover, it can be realized with a small circuit configuration.
[0035]
A level shifter according to a tenth aspect of the present invention is the level shifter according to the ninth aspect, wherein a low voltage power supply system signal input terminal is provided between a low voltage power supply system signal input terminal and a capacitor in response to input of a reset control signal. Is provided to one end of the capacitor after inverting the input signal, and a reset control circuit that allows the input signal from the low-voltage power supply system signal input terminal to pass as it is when no reset control signal is input.
[0036]
According to this configuration, even if the level of the input signal of the low-voltage power supply system signal input terminal does not match the level of the output signal of the high-voltage power supply system signal output terminal due to malfunction due to noise or the like, the reset control circuit resets the signal. By inputting a control signal, both signals can be matched.
[0037]
A level shifter according to an eleventh aspect of the present invention is the level shifter according to the tenth aspect, wherein the level shifter detects an inconsistency between the level of the input signal from the low voltage power supply system signal input terminal and the level of the output signal from the high voltage power supply system signal output terminal. A reset control signal generation circuit for automatically generating a reset control signal is provided.
[0038]
According to this configuration, the reset control signal generation circuit is provided to detect a mismatch between the level of the input signal from the low-voltage power supply system signal input terminal and the level of the output signal from the high-voltage power supply system signal output terminal, thereby resetting the reset control signal. Can be automatically generated, and when the level of the input signal of the low-voltage power supply system signal input terminal and the level of the output signal of the high-voltage power supply system signal output terminal do not match, match both signals. Can be.
[0039]
Here, the reason for providing the reset control circuit and the reset control signal generation circuit will be described. The invention according to claims 1, 2, 5, 6 and 9 is a level shifter for transmitting a signal only when an input signal changes, and when a power supply is activated or noise occurs inside a circuit. Even if the difference between the input signal and the output signal occurs, it cannot be transmitted to the output signal until the input signal changes. As a means for solving this problem, when the input signal and the output signal of the level shifter are different from each other when the input signal is not changed, a reset control signal generating circuit for generating a reset control signal for changing the input signal, and a reset control signal are input. A reset control circuit for inverting an input signal is provided.
[0040]
In the above invention, the input signal is a digital signal, and it is assumed that the input signal is performed instantaneously when the level changes.
[0041]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a specific embodiment of the present invention will be described with reference to FIGS.
[0042]
(Embodiment 1)
Hereinafter, a first embodiment of the present invention will be described in detail with reference to a circuit diagram and a timing chart.
[0043]
FIG. 1 shows a circuit configuration of a level shifter 100 according to the first embodiment. In FIG. 1, reference numeral 100A denotes a low-voltage power supply system signal input terminal to which an input signal whose level changes between a low-voltage power supply potential and a ground potential is supplied. 100B is a high voltage power supply signal output terminal where an output signal whose level changes between the high voltage power supply potential and the ground potential appears. S100A is an input signal of the level shifter 100. S100B is an output signal of the level shifter 100.
[0044]
Reference numeral 101 denotes a low-voltage power supply system inverting circuit (inverter) having an input terminal connected to the low-voltage power supply signal input terminal 100A and having a function of inverting the logic of the input signal. S101 is a signal output from the inverting circuit 101. Note that a low-voltage power supply system means operating with a low-voltage power supply, and a high-voltage power supply system means operating with a high-voltage power supply.
[0045]
102 and 103 are capacitors between the low-voltage power supply side and the high-voltage power supply side. The capacitor 102 has one end (terminal on the low-voltage power supply side) connected to the low-voltage power supply system signal input terminal 100A. When the input signal from the voltage power supply system signal input terminal 100A changes from a high level to a low level, it has a function of generating a spike wave from a high level to a low level at a terminal (the other end) on the high voltage power supply side. One end (terminal on the low voltage power supply side) of the capacitor 103 is connected to the output terminal of the inverting circuit 101, and when the input signal from the low voltage power supply system signal input terminal 100A changes from low level to high level, the capacitor 103 goes high. It has a function of generating a spike wave from a high level to a low level at a terminal (the other end) on the voltage power supply side.
[0046]
S102 is a signal of the terminal of the capacitor 102 on the high voltage power supply side. S103 is a signal of a terminal on the high voltage power supply side of the capacitor 103. 104 is a high voltage power supply terminal.
[0047]
Reference numeral 105 denotes a P-channel MOS transistor having a gate connected to the ground terminal 110, that is, a gate potential fixed to the ground potential, a source connected to the high-voltage power supply terminal 104, and a drain connected to the other end of the capacitor 102. The other end of the capacitor 102 functions as a pull-up resistor that fixes the potential of the high-voltage power supply 104.
[0048]
Reference numeral 106 denotes a P-channel MOS transistor having a gate connected to the ground terminal 110, that is, a gate potential fixed to the ground potential, a source connected to the high-voltage power supply terminal 104, and a drain connected to the other end of the capacitor 103. The other end of the capacitor 103 functions as a pull-up resistor that fixes the potential of the high-voltage power supply 104.
[0049]
Reference numeral 107 denotes a diode provided in parallel with the P-channel MOS transistor 105 with the cathode connected to the high-voltage power supply terminal 104 and the anode connected to the other end of the capacitor 102. It has a function of preventing the voltage from becoming
[0050]
Reference numeral 108 denotes a diode provided in parallel with the P-channel MOS transistor 106 in a state where the cathode is connected to the high-voltage power supply terminal 104 and the anode is connected to the other end of the capacitor 103. It has a function of preventing the voltage from becoming
[0051]
A data latch circuit 109 having a set function and a reset function is reset when the signal at the other end of the capacitor 102 goes to a low voltage level, and is set when the signal at the other end of the capacitor 103 goes to a low voltage level. That is, the signal is reset by the low level reception of the spike wave signal generated by the capacitor 102, and is set by the low level reception of the spike wave signal generated by the capacitor 103.
[0052]
An example of the operation of the level shifter configured as described above will be described with reference to the timing chart of FIG.
[0053]
Timing T ₀ When the input signal S100A changes from a low level to a high level, the signal S101 changes from a high level to a low level.
[0054]
The signal S103 generates a spike wave which changes to a low level with the change of the signal S101 and thereafter returns to a high level by the action of the P-channel MOS transistor 106.
[0055]
The signal S102 tends to increase to a voltage higher than the high-voltage power supply voltage with the change of the input signal S100A, but the forward current flows through the diode 107, so that the high-voltage power supply voltage is maintained.
[0056]
The data latch circuit 109 receives the spike wave of the signal S103 and changes the output signal to a high register level, and thus changes the output signal S100B of the high voltage power supply system signal output terminal 100B to a high level.
[0057]
Timing T ₁ When the input signal S100A changes from the high level to the low level, the signal S101 changes from the low level to the high level. The signal S102 generates a spike wave which changes to a low level in accordance with the change of the input signal S100A, and thereafter returns to a high level by the action of the P-channel MOS transistor 106.
[0058]
The signal S103 tends to increase to a voltage higher than the high-voltage power supply voltage in accordance with the change in the signal S101. However, a forward current flows through the diode 108, and the high-voltage power supply voltage is maintained.
[0059]
The data latch circuit 109 receives the spike wave of the signal S102 and changes the output signal to a low level, and thus changes the output signal S100B of the high voltage power supply system signal output terminal 100B to a low level.
[0060]
Timing T ₃ In this case, even if the low-voltage power supply is turned off and the input signal S100A and the signal S101 enter a floating state, the gates of the MOS transistors of the data latch circuit 109 are fixed by the action of the P-channel MOS transistors 105 and 106, and the through current is reduced. Not flowing.
[0061]
With the above operation, the level shifter shifts the level of the signal from the low-voltage power supply to the high-voltage power supply and, even when the low-voltage power supply is turned off, does not pass through current to the high-voltage power supply circuit, thereby reducing the current consumption. Is realized.
[0062]
Although the pull-up resistors 105 and 106 are used in the level shifter of the first embodiment, as shown in FIG. 9, instead of the pull-up resistors 105 and 106, a pull-down resistor connected to the ground is used. A data latch circuit for connecting the cathodes of the diodes 107 and 108 to the high-voltage power supply side of the capacitor and reconnecting the anode to the ground, using the data latch circuit 109 as a negative logic input and outputting a negative logic. By setting it to 113, the same function as that of the level shifter of the first embodiment can be satisfied.
[0063]
(Embodiment 2)
Hereinafter, a second embodiment of the present invention will be described in detail with reference to a circuit diagram and a timing chart.
[0064]
FIG. 3 shows a circuit configuration of a level shifter 200 according to the second embodiment. In FIG. 3, reference numeral 200A denotes a low-voltage power supply system signal input terminal to which an input signal whose level changes between a low-voltage power supply potential and a ground potential is supplied. Reference numeral 200B denotes a high voltage power supply signal output terminal on which an output signal whose level changes between the high voltage power supply potential and the ground potential appears. S200A is an input signal of the level shifter 200. S200B is an output signal of the level shifter 200.
[0065]
Reference numeral 201 denotes a capacitor between the low-voltage power supply side and the high-voltage power supply side, one end of which is connected to the low-voltage power supply system signal input terminal 200A (terminal on the low-voltage power supply side). It has the function of transmitting from the power supply system circuit to the high-voltage power supply system circuit. S201 is a signal of a terminal (the other end) on the high voltage power supply side of the capacitor 201.
[0066]
Reference numeral 204 denotes a high-voltage power supply system inverting circuit (inverter) having an input terminal connected to the other end of the capacitor 201 (terminal on the high-voltage power supply side), and has a function of inverting the potential of the other end of the capacitor 201. Reference numeral 205 denotes an inversion circuit (inverter) of a high-voltage power supply system in which an input terminal is connected to an output terminal of the inversion circuit 204, and has a function of further inverting the output of the inversion circuit 204.
[0067]
S204 is a signal output from the inversion circuit 204. 206 is a high voltage power supply terminal.
[0068]
Reference numeral 202 denotes a P-channel MOS transistor having a source connected to the high-voltage power supply terminal 206, a gate connected to the output terminal of the inversion circuit 204, and a drain connected to the other end of the capacitor 201. When the input signal from the low voltage power supply system signal input terminal 200A changes from the low level to the high level, the signal on the high voltage power supply side (the other end) of the capacitor 201 is output from the inversion circuit 204. It has a function of fixing the high voltage power supply side of the capacitor 201 to a high level by the output control of the inversion circuit 204 when the voltage becomes higher than the threshold value.
[0069]
An N-channel transistor 203 has a source connected to the ground terminal 207, a gate connected to the output terminal of the inversion circuit 204, and a drain connected to the other end of the capacitor 201. When the input signal from the low voltage power supply system signal input terminal 200A changes from the high level to the low level, the N-channel MOS transistor 203 changes the signal on the high voltage power supply side (the other end) of the capacitor 201 to the inversion circuit 204. When the voltage becomes lower than the threshold value, the high-voltage power supply side of the capacitor 201 is fixed to a low level by the output control of the inverting circuit 204.
[0070]
An example of the operation of the level shifter configured as described above will be described with reference to the timing chart of FIG.
[0071]
Timing T ₀ , The input signal S200A changes from the low level to the high level. The signal S201 changes from a low level to a high level with a change in the input signal S100A. When the signal S201 exceeds the threshold voltage of the inverting circuit 204, the signal S204 changes to low level, turning off the N-channel MOS transistor 203, turning on the P-channel MOS transistor 202, and fixing the signal S201 to high level.
[0072]
When the signal S204 changes to a low level, the output signal S200B is changed to a high level by the inversion circuit 205.
[0073]
Timing T ₁ , The input signal S200A changes from the high level to the low level. When the signal S201 falls below the threshold voltage of the inverting circuit 204, the signal S204 changes to a high level, turning off the P-channel MOS transistor 202, turning on the N-channel MOS transistor 203, and fixing the signal S201 to a low level.
[0074]
When the signal S204 changes to a high level, the output signal S200B is changed to a low level by the inversion circuit 205.
[0075]
Timing T ₂ In this case, even if the low-voltage power supply is turned off and the input signal S200A floats, the gate of the MOS transistor of the inversion circuit 204 is fixed by the action of the N-channel MOS transistor 203, and no through current flows.
[0076]
With the above operation, the level shifter shifts the level of the signal from the low-voltage power supply to the high-voltage power supply and, even when the low-voltage power supply is turned off, does not pass through current to the high-voltage power supply circuit, thereby reducing the current consumption. Is realized by a small-scale circuit.
[0077]
(Embodiment 3)
Hereinafter, a third embodiment of the present invention will be described in detail with reference to a circuit diagram and a timing chart.
[0078]
This embodiment solves the following problems existing in the first embodiment. The first embodiment discloses a configuration of a level shifter that transmits a signal only when an input signal changes. When a power supply is started or when noise occurs inside a circuit, an input signal and an output signal are output. Levels may differ. In such a case, until the input signal changes, it cannot be transmitted to the output signal, and the level mismatch between the input signal and the output signal cannot be eliminated immediately. This problem also exists in the second embodiment.
[0079]
In order to solve this problem, when the input signal and the output signal of the level shifter are different from each other except when the input signal changes, a reset control signal generating circuit for generating a reset control signal for changing the input signal; Then, a reset control circuit for inverting the input signal is provided.
[0080]
Hereinafter, this embodiment will be described in detail.
[0081]
FIG. 5 shows a circuit configuration of a level shifter 300 according to the third embodiment. In FIG. 5, the following circuit is provided in addition to the circuit configuration of the first embodiment. Reference numeral 301 denotes a reset control circuit including a low-voltage power supply exclusive OR circuit provided between the low-voltage power supply signal input terminal 100A, the inverting circuit 101, and the capacitor 102, and responds to the input of the reset control signal S302. Then, the input signal from the low-voltage power supply system signal input terminal 100A is inverted and applied to the inverting circuit 101 and one end of the capacitor 102, and the input signal from the low-voltage power supply system signal input terminal 100A is directly used when no reset control signal is input. Let it pass. S301 is a signal output from the exclusive OR circuit 301.
[0082]
Reference numeral 302 denotes a low-voltage power supply reset control signal generation circuit that outputs an assert signal when the input signal S100A and the output signal S100B of the level shifter 300 do not match. That is, the reset control signal generation circuit 302 detects a mismatch between the level of the input signal from the low voltage power supply system signal input terminal 100A and the level of the output signal from the high voltage power supply system signal output terminal 100B, and automatically generates the reset control signal. Will occur. S302 is a signal output from the reset control signal generation circuit 302.
[0083]
302A is an exclusive OR circuit of a low voltage power supply system. S302A is a signal output from the exclusive OR circuit 302A. 302B and 302E are delay circuits of a low-voltage power supply system for delaying a signal for a certain period. S302B is a signal output from the delay circuit 302B. 302C is an exclusive NOR circuit of a low voltage power supply system. S302C is a signal output from the exclusive NOR circuit 302C. Reference numeral 302D denotes an AND circuit of a low-voltage power supply system. S302D is a signal output from the AND circuit.
[0084]
An example of the operation of the level shifter configured as described above will be described with reference to the timing chart of FIG.
[0085]
Timing T ₀ In, noise occurs in the signal S103, and the output signal S100B changes to a high level different from the input signal S100A. The difference between the input signal S100A and the output signal S100B causes the signal S302A of the reset control signal generation circuit 302 to be asserted, and the signal S302D to be transmitted through the AND circuit 302D. After that, at a certain time by the delay circuit 302E, the timing T ₁ Reset signal S302 is asserted.
[0086]
At the same time, the exclusive OR circuit 301 changes the signal S301 to a high level. When the signal S301 changes, the signal S301 and the signal S302B delayed by the delay circuit 302B have different levels during the delay time, and the exclusive NOR circuit 302C outputs the signal at the timing T. ₁ Output negation until. The assertion of the signal S302A is cut by the signal S302C, and the signal S302D is negated.
[0087]
After that, at a certain time by the delay circuit 302E, the timing T ₂ Reset signal S302 is negated. At the same time, the exclusive OR circuit 301 changes the signal S301 to a low level. The signal S102 generates a spike wave which changes to a low level with the change of the signal S301 and then returns to a high level by the action of the P-channel MOS transistor 106. The data latch circuit 109 receives the spike wave of the signal S102, and changes the output signal S100B to a low level.
[0088]
With the above operation, the signal is level-shifted from the low-voltage power supply to the high-voltage power supply, and even when the low-voltage power supply is turned off, a through current does not flow through the high-voltage power supply circuit. When the level of the input signal is different from the level of the output signal, a level shifter capable of automatically generating a reset control signal to have the same signal level is realized.
[0089]
Note that the configurations of the reset control circuit 301 and the reset control signal generation circuit 302 can be applied to the level shifter having a configuration having a pull-down resistor, and can also be applied to the configuration of the second embodiment. FIG. 10 shows a configuration in which a reset control circuit 301 and a reset control signal generation circuit 302 are applied to a level shifter having a pull-down resistor. FIG. 11 shows a configuration in which a reset control circuit 301 and a reset control signal generation circuit 302 are applied to the configuration of the second embodiment.
[0090]
【The invention's effect】
According to the present invention, a capacitor is provided between the low-voltage power supply side and the high-voltage power supply side, a signal is transmitted by the coupling operation of the capacitor, and fixed to the high-voltage side terminal of the capacitor with a pull-up resistor or a pull-down resistor. Even when the low-voltage power supply is off, the gate of the high-voltage power supply circuit is fixed, so that a through current does not flow and a level shifter that consumes less current can be provided.
[0091]
In addition, by controlling the on / off state of the pull-up P-channel MOS transistor and the pull-down N-channel MOS transistor that fix the input gate on the high-voltage power supply side according to the state of the input signal, the low-voltage power supply can be implemented in a small-scale circuit. The gate of the circuit of the high-voltage power supply system is fixed even when is turned off, so that a through current does not flow and a level shifter consuming less current can be provided.
[0092]
When the levels of the input signal and the output signal are different, the same signal state can be restored by inputting a reset control signal.
[0093]
In addition, by providing the reset control signal generation circuit, the reset control signal can be automatically asserted and returned to the same signal state, and even when the input signal and the output signal become different signal states due to noise or the like, It is possible to provide a level shifter that can automatically return to a normal state, and even when the voltage power supply is off, the gate of the high-voltage power supply system circuit is fixed and the through current does not flow, and the current consumption is small.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a first embodiment of the present invention.
FIG. 2 is a timing chart showing the first embodiment of the present invention.
FIG. 3 is a circuit diagram showing a second embodiment of the present invention.
FIG. 4 is a timing chart showing a second embodiment of the present invention.
FIG. 5 is a circuit diagram showing a third embodiment of the present invention.
FIG. 6 is a timing chart showing a third embodiment of the present invention.
FIG. 7 is a circuit diagram of a conventional level shifter.
FIG. 8 is a timing chart of a conventional level shifter.
FIG. 9 is a circuit diagram illustrating another circuit example according to the first embodiment;
FIG. 10 is a circuit diagram showing still another circuit example according to the first embodiment.
FIG. 11 is a circuit diagram showing another circuit example according to the second embodiment.
[Explanation of symbols]
100 level shifter
100A low voltage power supply signal input terminal
100B High voltage power system signal output terminal
S100A Level shifter input signal
S100B Level shifter output signal
101 Low voltage power supply inverting circuit
102,103 Capacitor
104 High voltage power supply
105,106 P-channel MOS transistor
107,108 Diode
109, 113 Data latch circuit
200 level shifter
200A low voltage power supply system signal input terminal
200B High voltage power system signal output terminal
201 Capacitor
202 P-channel MOS transistor
203 N-channel MOS transistor
204,205 High voltage power supply system inverting circuit
300 level shifter
301 Low voltage power supply reset control circuit
302 Low voltage power supply reset control signal generation circuit
400 level shifter
400A low voltage power supply signal input terminal
400B High voltage power system signal output terminal
401, 402 Inverting circuit of low voltage power supply system
403, 404 N-channel MOS transistor
405,406 P-channel MOS transistor
407 High voltage power supply system inversion circuit

Claims (11)

A low-voltage power supply system signal input terminal to which an input signal whose level changes between a low-voltage power supply potential and a ground potential is supplied;
An inverting circuit of a low-voltage power supply system having an input terminal connected to the low-voltage power supply system signal input terminal;
A first capacitor having one end connected to the low-voltage power supply system signal input terminal;
A first pull-up resistor having one end connected to the high-voltage power supply terminal and the other end connected to the other end of the first capacitor;
A second capacitor having one end connected to an output terminal of the inverting circuit;
A second pull-up resistor having one end connected to the high-voltage power supply terminal and the other end connected to the other end of the second capacitor;
A data latch circuit that is reset when a signal at the other end of the first capacitor goes to a low voltage level, and is set when a signal at the other end of the second capacitor goes to a low voltage level;
A level shifter including a high voltage power supply system signal output terminal connected to an output terminal of the data latch circuit. A first diode is provided in parallel with the first pull-up resistor in a state where the cathode is connected to the high voltage power supply terminal and the anode is connected to the other end of the first capacitor, and the cathode is connected to the high voltage power supply terminal. 2. The level shifter according to claim 1, wherein a second diode is provided in parallel with said second pull-up resistor with an anode connected to the other end of the second capacitor. Inverting an input signal from the low-voltage power supply system signal input terminal between a low-voltage power supply system signal input terminal and an inverting circuit and a first capacitor in response to input of a reset control signal, 3. The level shifter according to claim 1, further comprising a reset control circuit that is provided to one end of the first capacitor and passes an input signal from the low-voltage power supply system signal input terminal as it is when the reset control signal is not input. A reset control signal generation circuit for automatically generating a reset control signal by detecting a mismatch between the level of an input signal from a low voltage power supply system signal input terminal and a level of an output signal from a high voltage power supply system signal output terminal. 3. The level shifter according to 3. A low-voltage power supply system signal input terminal to which an input signal whose level changes between a low-voltage power supply potential and a ground potential is supplied;
An inverting circuit of a low-voltage power supply system having an input terminal connected to the low-voltage power supply system signal input terminal;
A first capacitor having one end connected to the low-voltage power supply system signal input terminal;
A first pull-down resistor having one end connected to the ground terminal and the other end connected to the other end of the first capacitor;
A second capacitor having one end connected to an output terminal of the inverting circuit;
A second pull-down resistor having one end connected to the ground terminal and the other end connected to the other end of the second capacitor;
A data latch circuit that is set when a signal at the other end of the first capacitor goes to a high voltage level and is reset when a signal at the other end of the second capacitor goes to a high voltage level;
A level shifter including a high voltage power supply system signal output terminal connected to an output terminal of the data latch circuit. A first diode is provided in parallel with the first pull-down resistor, with the anode connected to the ground terminal and the cathode connected to the other end of the first capacitor, the anode connected to the ground terminal, and the cathode connected to the second terminal. 6. The level shifter according to claim 5, wherein a second diode is provided in parallel with the second pull-down resistor so as to be connected to the other end of the capacitor. Inverting an input signal from the low-voltage power supply system signal input terminal between a low-voltage power supply system signal input terminal and an inverting circuit and a first capacitor in response to input of a reset control signal, 7. The level shifter according to claim 5, further comprising a reset control circuit that is provided to one end of the first capacitor and passes an input signal from the low-voltage power supply system signal input terminal as it is when the reset control signal is not input. A reset control signal generation circuit for automatically generating a reset control signal by detecting a mismatch between the level of an input signal from a low voltage power supply system signal input terminal and a level of an output signal from a high voltage power supply system signal output terminal. 7. The level shifter according to 7. A low-voltage power supply system signal input terminal to which an input signal whose level changes between a low-voltage power supply potential and a ground potential is supplied;
A capacitor having one end connected to the low-voltage power supply system signal input terminal;
A first inverting circuit of a high-voltage power supply system having an input terminal connected to the other end of the capacitor;
A second inverting circuit of a high-voltage power supply system having an input terminal connected to an output terminal of the first inverting circuit;
A P-channel MOS transistor having a source connected to the high-voltage power supply terminal, a gate connected to the output terminal of the first inverting circuit, and a drain connected to the other end of the capacitor;
An N-channel MOS transistor having a source connected to the ground terminal, a gate connected to the output terminal of the first inverting circuit, and a drain connected to the other end of the capacitor;
A high-voltage power supply system signal output terminal connected to an output terminal of the second inverting circuit. In response to a reset control signal input between a low-voltage power supply signal input terminal and the capacitor, inverting an input signal from the low-voltage power supply signal input terminal and applying the inverted signal to one end of the capacitor; 10. The level shifter according to claim 9, further comprising a reset control circuit for passing an input signal from the low-voltage power supply system signal input terminal as it is when no signal is input. A reset control signal generation circuit for automatically generating a reset control signal by detecting a mismatch between the level of an input signal from a low voltage power supply system signal input terminal and a level of an output signal from a high voltage power supply system signal output terminal. 10. The level shifter according to 10.

Images