JP2004363401A - Method for manufacturing semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve device performance (at input and output levels) by avoiding or relaxing deterioration in physicality of an active layer by decreasing a temperature of crystal growth of a p-type semiconductor layer lower than before. <P>SOLUTION: A p-type clad layer 6 doped by a magnesium (Mg) comprising a p-type Al<SB>0.15</SB>Ga<SB>0.85</SB>N having a film thickness of 200 Å and a concentration of 5×10<SP>19</SP>/cm<SP>3</SP>is formed by supplying N<SB>2</SB>at a rate of 10 liter/min., TMG at a rate of 1.6×10<SP>-5</SP>mol/min., TMA at a rate of 6×10<SP>-6</SP>mol/min., and CP<SB>2</SB>Mg at a rate of 4×10<SP>-7</SP>mol/min., by increasing a temperature of a substrate 1 up to 890°C. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a method for manufacturing a semiconductor device having an active layer formed by laminating a large number of semiconductor layers by crystal growth of a group III nitride compound semiconductor and having a semiconductor layer containing indium (In). About.
The concept of the “active layer” in this specification includes, of course, the light receiving layer of the semiconductor light receiving element in addition to the light emitting layer of the semiconductor light emitting element.
INDUSTRIAL APPLICABILITY The present invention can be applied to a manufacturing process of an LED, a semiconductor laser, and the like, and of course, can be similarly used for manufacturing a semiconductor light receiving element.
[0002]
[Prior art]
[Patent Document 1]
JP-A-6-177423 [Patent Document 2]
Japanese Patent No. 3198912 [Patent Document 3]
JP 2001-327663 A [Patent Document 4]
JP 2003-073197 A
For example, as described in detail in Patent Documents 1 and 2 described above, the crystal growth temperature of a conventional p-type cladding layer is set to any temperature within a range of approximately 950 ° C. to 1150 ° C. I have.
For example, as seen in these conventional techniques, a p-type doped GaN layer or a p-type doped AlGaN layer is generally used as a p-type semiconductor layer. The growth temperature is as high as around 1000 ° C.
In addition, hydrogen gas (H ₂ ) is often used as a carrier gas for carrying a source gas for a p-type semiconductor layer of a conventional semiconductor element.
[0004]
On the other hand, the active layer (light-emitting layer or light-receiving layer) of the semiconductor element is formed from a semiconductor layer containing indium (In) such as InGaN, and its crystal growth temperature is usually about 650 ° C. to 820 ° C. depending on the indium composition ratio and the like. Is set to any temperature within the range.
In general, the active layer of the semiconductor element is subjected to crystal growth before the p-type semiconductor layer, so that the active layer is exposed to the crystal growth temperature of the p-type semiconductor layer after its own layer is stacked. .
[0005]
[Problems to be solved by the invention]
However, since semiconductor crystals are generally sufficiently stable only at or below the crystal growth temperature of the self-layer, when the active layer is exposed to the high crystal growth temperature of the p-type semiconductor layer as described above, The crystallinity is deteriorated, and accordingly, the element performance (energy efficiency such as output level / input level) of the semiconductor element is not improved to an expected level.
Further, such a problem tends to be more remarkable as the difference between the crystal growth temperatures of the active layer and the p-type semiconductor layer is larger.
[0006]
The present invention has been made to solve the above problems, and an object of the present invention is to reduce the crystallinity of an active layer based on the crystal growth conditions of a p-type semiconductor layer in which the active layer is less likely to be thermally damaged. By maintaining high quality, it is to improve the element performance (input / output level) of the semiconductor element.
[0007]
Means for Solving the Problems, Functions and Effects of the Invention
In order to solve the above-mentioned problems, the following means are effective.
That is, a first means of the present invention is formed by laminating a large number of semiconductor layers formed by crystal growth of a group III nitride compound semiconductor, and includes a semiconductor layer containing indium (In). In a manufacturing process of a semiconductor device having an active layer, the crystal growth temperature of at least one p-type semiconductor layer laminated after the active layer is set to 820 ° C. to 910 ° C. A rare gas (He, Ne, Ar, Kr, Xe, Rn) or a nitrogen gas (N ₂ ) is used as a carrier gas for carrying the gas.
[0008]
However, the carrier gas may be a mixed gas in which a plurality of element gases are mixed. In addition, even if a slight amount of hydrogen gas (H ₂ ) is included, there is no particular problem.
In addition, here referred to the "Group III nitride compound semiconductor" generally, binary, ternary, or quaternary _{"Al 1-x-y Ga y} In x N; 0 ≦ x ≦ 1,0 ≦ y ≦ 1,0 ≦ 1-xy ≦ 1 ”, a semiconductor having an arbitrary mixed crystal ratio, and a semiconductor to which a p-type or n-type impurity is added, also include these semiconductors. Group III nitride compound semiconductor ".
[0009]
Further, at least a part of the group III elements (Al, Ga, In) is replaced with boron (B), thallium (Tl), or the like, or at least a part of nitrogen (N) is phosphorus (P). ), Arsenic (As), antimony (Sb), bismuth (Bi) and the like are also included in the category of these “III-nitride compound semiconductors”.
[0010]
As the p-type impurity (acceptor), a known p-type impurity such as magnesium (Mg) or calcium (Ca) can be added.
Examples of the n-type impurity (donor) include known n-type impurities such as silicon (Si), sulfur (S), selenium (Se), tellurium (Te), and germanium (Ge). Can be added.
Further, two or more elements may be added to these impurities (acceptor or donor) at the same time, or both types (p-type and n-type) may be added at the same time.
[0011]
Further, the stacked structure of the p-type semiconductor layers may be a single layer structure or a multilayer structure. That is, as the laminated structure of the p-type semiconductor layer, for example, those having the following structures are useful or usable.
(Structural example 1) A single-layer structure composed of an AlGaN layer.
(Configuration Example 2) A multilayer structure in which AlGaN layers and GaN layers are alternately and substantially periodically stacked.
(Configuration Example 3) A multilayer structure in which AlGaN layers and InGaN layers are alternately and substantially periodically stacked.
[0012]
Since the crystal growth temperature of the p-type semiconductor layer is much lower than that of the conventional one, thermal damage to the previously stacked active layer is greatly suppressed. Therefore, according to the above-described manufacturing method, deterioration of the active layer is suppressed, and the element performance (input / output level) of the semiconductor element is greatly improved.
[0013]
In addition, the above-described crystal growth condition of the p-type semiconductor layer may not only suppress the deterioration of the active layer, but also provide at least one of the following functions 1 to 3 assumed below. It is presumed that, for example, based on such an action, the resistance of the p-type layer can be more effectively reduced.
[0014]
(Action 1)
Since the use of hydrogen (H ₂ ) as a carrier gas has been abolished, the nitrogen desorption phenomenon of the group III element in the semiconductor crystal of the p-type semiconductor layer based on the following chemical formula (1) is relatively unlikely to occur. As a result, the crystallinity of the p-type semiconductor layer is easily maintained at a high quality.
(Equation 1)
2ΛN + 3H ₂ → 2Λ + 2NH ₃
(Λ represents an arbitrary Group III element such as Ga and Al in the crystal) (1)
[0015]
(Action 2)
When nitrogen (N ₂ ) is used as the carrier gas, for example, the following hole compensation action is relatively likely to occur, so that the acceptor atom (eg, Mg) can be activated more effectively than before.
(Equation 2)
_{6MgH + N 2 → 6Mg + 2NH} 3 ... (2)
[0016]
(Action 3)
If the concentration of the acceptor atoms (eg, Mg) in the semiconductor crystal of the p-type semiconductor layer is too high, the crystallinity of the semiconductor crystal will be degraded, and if the concentration is too low, the semiconductor crystal will become p-type. Insufficiently, electrical conductivity tends to be insufficient at the same time. However, as a result of the above-mentioned crystal growth conditions of the p-type semiconductor layer acting well in some way, the concentration of acceptor atoms in the semiconductor crystal of the p-type semiconductor layer could be set to an ideal value.
[0017]
Among the above-mentioned carrier gases (He, Ne, Ar, Kr, Xe, Rn, N ₂ ), in particular, with respect to nitrogen gas (N ₂ ), the possibility of leading the above-mentioned action 2 cannot be denied, and the cost is also low. It is advantageous.
[0018]
According to a second aspect of the present invention, in the first aspect, the crystal growth temperature of the p-type semiconductor layer is 850 ° C. or more and 890 ° C. or less.
That is, it is more desirable that the crystal growth temperature of the p-type semiconductor layer be set at 850 ° C. or more and 890 ° C. or less, among the above-mentioned temperatures (820 ° C. or more and 910 ° C. or less). With such a temperature setting, higher device performance can be obtained.
[0019]
A third means is that, in the first or second means, the p-type cladding layer is laminated so as to have a thickness of 50 ° or more and 400 ° or less.
More preferably, the thickness of the p-type cladding layer is preferably about 100 ° to 250 °. If the thickness is too small, the effect of confining carriers (electrons) becomes insufficient, which is not desirable. Alternatively, the acceptor atoms forming the p-type contact layer are thermally diffused during the crystal growth of the p-type contact layer or during the annealing process, and the acceptor atoms may be undesirably introduced into the active layer.
[0020]
If the film thickness is too large, the driving voltage required for high-brightness light emission cannot be sufficiently suppressed, or the crystal growth time of the p-type cladding layer takes longer than necessary. The active layer grown at a low temperature tends to be thermally damaged, or at least has poor productivity.
Under these circumstances, the p-type cladding layer is preferably stacked to a thickness of 50 to 400, more preferably 100 to 250. Thereby, higher device performance can be obtained effectively at a relatively low production cost.
[0021]
According to a fourth aspect of the present invention, the active layer of any one of the first to third aspects has an MQW structure in which a semiconductor layer containing indium (In) is a well layer. It is.
Furthermore, according to such a configuration, the device performance of the semiconductor device can be more effectively improved by the operation and effect of the well-known MQW structure.
By the means of the present invention described above, the above problems can be effectively or rationally solved.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the present invention will be described based on specific examples. However, the present invention is not limited to the embodiments described below.
(First embodiment)
FIG. 1 is a schematic cross-sectional configuration diagram of a light emitting device 10 formed of a group III nitride compound semiconductor formed on a sapphire substrate 1. A buffer layer 2 of aluminum nitride (AlN) having a thickness of about 25 nm is provided on a substrate 1, and an n-type contact layer of silicon (Si) doped GaN having a thickness of about 4.0 μm is provided thereon. 3 (n-type high carrier concentration layer) is formed.
[0023]
On the n-type contact layer 3, an n-type cladding layer 4 (low carrier concentration layer) made of non-doped GaN and having a thickness of 105 ° is formed. Further, an MQW structure in which a total of five well layers 51 of In _0.30 Ga _0.70 N having a thickness of about 35 ° and barrier layers 52 of GaN having a thickness of about 70 ° are alternately laminated thereon. Active layer 5 is formed. On this active layer 5, a p-type cladding layer 6 of Mg-doped p-type Al _0.15 Ga _0.85 N having a thickness of about 50 nm is formed. Further, on the p-type cladding layer 6, a p-type contact layer 7 of Mg-doped p-type GaN having a thickness of about 100 nm is formed.
[0024]
A translucent electrode 9 is formed on the p-type contact layer 7 by metal evaporation, and an electrode 8 is formed on the n-type contact layer 3. The translucent electrode 9 is composed of about 40 ° of cobalt (Co) bonded to the p-type contact layer 7 and about 60 ° of gold (Au) bonded to the Co. The electrode 8 is made of vanadium (V) having a thickness of about 200 ° and aluminum (Al) or an Al alloy having a thickness of about 1.8 μm.
[0025]
Next, a method for manufacturing the light emitting device 10 will be described.
The light emitting device 10 was manufactured by vapor phase growth by metal organic chemical vapor deposition (hereinafter abbreviated as “MOVPE”). The gases used were ammonia (NH ₃ ), carrier gas (H ₂ , N ₂ ), trimethylgallium (Ga (CH ₃ ) ₃ ) (hereinafter referred to as “TMG”), and trimethylaluminum (Al (CH ₃ ) ₃ ). (Hereinafter referred to as “TMA”), trimethylindium (In (CH ₃ ) ₃ ) (hereinafter referred to as “TMI”), silane (SiH ₄ ) and cyclopentadienyl magnesium (Mg (C ₅ H ₅ ) ₂ ) (Hereinafter referred to as “CP ₂ Mg”).
[0026]
First, the single crystal substrate 1 whose main surface is the a-plane cleaned by organic cleaning and heat treatment is mounted on a susceptor placed in a reaction chamber of a MOVPE apparatus. Next, the substrate 1 was baked at a temperature of 1100 ° C. while flowing H ₂ at a flow rate of 2 liters / minute for about 30 minutes at normal pressure.
[0027]
Next, the temperature was lowered to 400 ° C., and H ₂ was supplied at 20 liter / min, NH ₃ was supplied at 10 liter / min, and TMA was supplied at 1.8 × 10 ⁻⁵ mol / min. Was formed to a thickness of about 25 nm.
Next, the temperature of the substrate 1 was maintained at 1150 ° C., H ₂ was 20 l / min, NH ₃ was 10 l / min, TMG was 1.7 × 10 ⁻⁴ mol / min, and 0.86 ppm by H ₂ gas. Is supplied at a concentration of 2 × 10 ⁻⁷ mol / min, and an n-type GaN made of GaN having a thickness of about 4.0 μm, an electron concentration of 2 × 10 ¹⁸ / cm ³ , and a Si concentration of 4 × 10 ¹⁸ / cm ^3. The contact layer 3 was formed.
[0028]
Thereafter, the temperature of the substrate 1 was maintained at 1150 ° C., H ₂ was supplied at 20 liter / min, NH ₃ was supplied at 10 liter / min, and TMG was supplied at 1.7 × 10 ⁻⁴ mol / min. An n-type clad layer 4 (low carrier concentration layer) having a thickness of 105 ° was formed.
[0029]
After the formation of the n-type cladding layer 4, the active layer 5 having the MQW structure (FIG. 1) composed of a total of five layers was formed.
That is, first, the temperature of the substrate 1 is lowered to 730 ° C., and at the same time, the carrier gas is changed from H ₂ to N ₂ , and while the supply amounts of the carrier gas and NH ₃ are maintained, the TMG is set to 3.1. × ^{10 -6} mol / min, by supplying at 0.7 × ^{10 -6} mol / min TMI, a well layer 51 made of _in 0.30 _{Ga 0.70} n having a thickness of about 35 Å n-type clad layer 4.
[0030]
Next, the temperature of the substrate 1 was raised to 885 ° C., and N ₂ was added at 20 L / min, NH ₃ was added at 10 L / min, and TMG was added at 1.2 × 10 ⁻⁵ mol on the well layer 51. / Min to form a barrier layer 52 of GaN having a thickness of about 70 °.
Hereinafter, this is repeated, and the well layers 51 and the barrier layers 52 are alternately stacked, and the above-mentioned five layers (the well layer 51, the barrier layer 52, the well layer 51, the barrier layer 52, and the last well layer 51) are formed. Of the active layer 5 was formed.
[0031]
(Crystal growth of p-type cladding layer 6)
Thereafter, the temperature of the substrate 1 was raised to 890 ° C., N ₂ was 10 liter / min, TMG was 1.6 × 10 ⁻⁵ mol / min, TMA was 6 × 10 ⁻⁶ mol / min, and CP ₂ Mg was supplied. 4 is supplied with × ^{10 -7} mol / min, a film thickness of about 200 Å, a p-type cladding consisting concentration 5 × ¹⁰ 19 / doped with magnesium (Mg) in cm ³ was p-type _Al 0.15 _{Ga 0.85} N Layer 6 was formed.
[0032]
(Crystal growth of p-type contact layer 7)
Finally, the temperature of the substrate 1 is raised to 1000 ° C., and at the same time, the carrier gas is changed again to H ₂ , H ₂ is 20 l / min, NH ₃ is 10 l / min, and TMG is 1.2 × 10 ^{−. A} p-type contact layer 7 made of p-type GaN doped with Mg having a thickness of about 85 nm and a concentration of 5 × 10 ¹⁹ / cm ³ by supplying CP ₂ Mg at 2 × 10 ⁻⁵ mol / min at ⁴ mol / min. Was formed.
The steps described above are crystal growth steps of each semiconductor layer made of a group III nitride compound semiconductor.
[0033]
After the above crystal growth process, an etching mask is formed on the p-type contact layer 7, the etching mask in a predetermined region is removed, and a portion of the p-type contact layer 7 not covered with the etching mask and the p-type cladding are removed. The layer 6, the active layer 5, the n-type cladding layer 4, and a part of the n-type contact layer 3 were eroded by reactive ion etching using a gas containing chlorine, thereby exposing the surface of the n-type contact layer 3.
[0034]
Next, with the etching mask left, a photoresist is applied to the entire surface, a window is formed in a predetermined region on the exposed surface of the n-type contact layer 3 by photolithography, and a high vacuum of the order of 10 ⁻⁴ Pa or less is formed. After evacuation, vanadium (V) having a thickness of about 200 ° and Al having a thickness of about 1.8 μm are deposited. Thereafter, the photoresist and the etching mask are removed.
[0035]
Subsequently, a photoresist is applied on the surface, the phytoresist of the electrode formation portion on the p-type contact layer 7 is removed by photolithography to form a window, and the p-type contact layer 7 is exposed. After evacuating the exposed p-type contact layer 7 to a high vacuum of the order of 10 ⁻⁴ Pa or less, Co is deposited to a thickness of about 40 °, and Au is deposited to a thickness of about 60 ° on the Co. I do. Next, the sample is taken out of the vapor deposition apparatus, Co and Au deposited on the photoresist are removed by a lift-off method, and a light-transmitting electrode 9 for the p-type contact layer 7 is formed.
[0036]
Thereafter, the sample atmosphere is evacuated by a vacuum pump, and O ₂ gas is supplied to a pressure of 3 Pa. In this state, the atmosphere temperature is set to about 550 ° C., and the heating is performed for about 3 minutes, and the p-type contact layer 7 and the p-type The p-type contact resistance of the clad layer 6 was reduced, and the p-type contact layer 7 and the electrode 9 were alloyed, and the n-type contact layer 3 and the electrode 8 were alloyed. Thus, an electrode 8 for the n-type contact layer 3 and an electrode 9 for the p-type contact layer 7 were formed.
[0037]
(Effects of the present embodiment)
By changing only the crystal growth conditions of the p-type cladding layer 6 from the crystal growth conditions of the above example, a model experiment comparable to the above example was performed.
FIG. 2 is a table disclosing various implementation conditions and implementation results (LED brightness) of those comparative model experiments. From this table, it can be seen that in the above example according to the present invention, it was possible to achieve an element performance of about 1.2 times higher luminance than the LED manufactured by the conventional manufacturing method.
[0038]
From these experimental results, the following (1) and (2) can be concluded at least with respect to the crystal growth conditions of the p-type cladding layer 6 in improving the element performance (luminance) of the light emitting element (LED).
(1) As a carrier gas, it is better to use a nitrogen gas (N ₂ ) than a hydrogen gas (H ₂ ).
This is because the acceptor atom (Mg), which is a p-type impurity, is incorporated by the change of the carrier gas to such an extent that the crystallinity of the p-type layer is not deteriorated, and a high activation rate required for the p-type layer can be realized. Probably the result. In addition to a nitrogen gas (N ₂ ), a rare gas, a mixed gas of a rare gas and a nitrogen gas, or the like may be used.
[0039]
(2) The optimum crystal growth temperature is 850 ° C to 890 ° C.
Since the crystal growth temperature of the p-type cladding layer 6 is much lower than that of the conventional one, thermal damage to the previously stacked active layer is greatly suppressed. For this reason, according to the above manufacturing method, it is considered that the deterioration of the active layer was suppressed, and the element performance of the semiconductor light receiving element was greatly improved.
[0040]
(Other modifications)
The crystal growth temperature of at least one p-type semiconductor layer laminated after the active layer is set to 820 ° C. or more and 910 ° C. or less, and a rare gas ( When using He, Ne, Ar, Kr, Xe, Rn) or nitrogen gas (N ₂ ), the p-type semiconductor layer is not limited to a special p-type cladding layer. At this time, the p-type semiconductor layer may be only the p-type contact layer, or may be all the p-type semiconductor layers.
[0041]
However, usually, the p-type cladding layer is laminated thicker (that is, for a long time) than the p-type contact layer, and the p-type cladding layer is closer to the active layer. Therefore, the crystal growth conditions of the p-type cladding layer are more important for maintaining the quality of the active layer.
However, making the temperature of the active layer higher than the crystal growth temperature of the active layer even for a relatively short time is, of course, not desirable from the viewpoint of preventing deterioration of the active layer.
[0042]
Therefore, from the viewpoint of preventing deterioration of the active layer, it is preferable that the crystal growth condition of the p-type contact layer is set as low as possible or as short as possible.
These crystal growth conditions are, of course, not individually independent or individually uniform, but, for example, as in the above embodiment, the crystal growth temperature of the p-type contact layer is 1100 ° C., which is the conventional value. It is often the case that the temperature is more preferably 1000 ° C., and the p-type contact layer has a fragmentary tendency such that the thickness of the p-type contact layer is more preferably 85 nm than the conventional 100 nm. The device performance of the light emitting device can also be improved by setting crystal growth conditions (crystal growth temperature and crystal growth time) that suppress thermal damage to the light emitting device.
[0043]
Further, as other methods for protecting the crystal quality of the active layer from high temperatures, for example, the technique disclosed in Japanese Patent No. 3064891 or the aforementioned Patent Document 3 and the like are already known.
Since the present invention does not prevent any combination of these conventional techniques, it is desirable that these conventional techniques be performed simultaneously when necessary.
That is, in the above-described embodiment, well-known crystal growth techniques such as the following (1) to (4) can be used together.
[0044]
(1) There is provided an active layer capping step of laminating a residual type cap layer between the active layer and the p-type semiconductor layer, which is finally left as a semiconductor layer forming a part of the semiconductor element.
(2) All or almost all volatilize while the temperature of the crystal growth surface composed of the upper surface of the semiconductor layer containing indium (In) is raised to the crystal growth temperature of the next semiconductor layer to be laminated. A well layer covering step of laminating the annihilation type cap layer immediately above each well layer is provided.
(3) The annihilation-type cap layer is formed from a semiconductor layer containing indium (In).
(4) In the well layer covering step, a semiconductor having substantially the same composition as that of the well layer is crystal-grown to form an annihilation-type cap layer.
[0045]
For example, if a barrier layer is formed after forming the annihilation-type cap layer on each well layer as described above, the annihilation-type cap layer is thermally decomposed and removed in a temperature increasing process, but the well layer is damaged. Therefore, a uniform film thickness can be formed without deteriorating the crystallinity of each well layer.
That is, by using such known supplementary means in combination, damage to the active layer can be further reduced, and further, the energy efficiency of the element can be improved.
[0046]
In the above embodiment, the composition of the barrier layer 52 is GaN. However, more generally, the barrier layer 52 is formed of “Al _{(1-x1-y1) Gay1} In having a wider band gap than the well layer 51. _A binary, ternary, or quaternary Group III nitride-based compound semiconductor consisting of _x1 N (0 ≦ x1 <1, 0 ≦ y1 ≦ 1) ”can be used. In the above embodiment, the active layer 5 of the light emitting element 10 has the MQW structure (multiple quantum well structure). However, the active layer 5 may have a SQW structure (single quantum well structure).
Further, the present invention can be applied to a light emitting element such as an LED or an LD, or a semiconductor light receiving element.
[Brief description of the drawings]
FIG. 1 is a schematic view illustrating a configuration of a light emitting element obtained by using the manufacturing method of the present invention.
FIG. 2 is a table disclosing various implementation conditions and implementation results of a comparative model experiment.
[Explanation of symbols]
10 light emitting element 1 sapphire substrate 2 buffer layer 3 n-type contact layer (n-type high carrier concentration layer)
4... N-type cladding layer (non-doped low carrier concentration layer)
5 Active layer 51 Well layer 52 Barrier layer 6 P-type cladding layer 7 P-type contact layer 8 Electrode 9 Translucent electrode

Claims (4)

A method for manufacturing a semiconductor device, comprising: an active layer formed by laminating a large number of semiconductor layers generated by crystal growth of a group III nitride compound semiconductor and having a semiconductor layer containing indium (In). And
A crystal growth temperature of at least one p-type semiconductor layer stacked after the active layer is set to 820 ° C. or more and 910 ° C. or less;
The method of manufacturing a semiconductor device characterized as a carrier gas carrying the material gas of the p-type semiconductor layer, noble gases (He, Ne, Ar, Kr , Xe, Rn) for using or nitrogen gas _{(N 2).} 2. The method according to claim 1, wherein the crystal growth temperature of the p-type semiconductor layer is 850 ° C. or more and 890 ° C. or less. 3. 3. The method according to claim 1, wherein the p-type semiconductor layer has a thickness of not less than 50 ° and not more than 400 °. 4. 4. The method according to claim 1, wherein the active layer has an MQW structure using a semiconductor layer containing indium (In) as a well layer. 5.

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