JP2004362587A - メモリシステム - Google Patents
メモリシステム Download PDFInfo
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- JP2004362587A JP2004362587A JP2004166593A JP2004166593A JP2004362587A JP 2004362587 A JP2004362587 A JP 2004362587A JP 2004166593 A JP2004166593 A JP 2004166593A JP 2004166593 A JP2004166593 A JP 2004166593A JP 2004362587 A JP2004362587 A JP 2004362587A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/02—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements
- G11C11/14—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements
- G11C11/15—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using magnetic elements using thin-film elements using multiple magnetic layers
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- For Increasing The Reliability Of Semiconductor Memories (AREA)
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Abstract
【解決手段】 メモリセルのアレイ28と、メモリセルのアレイ28のメモリセル32に書き込むように構成された書込み回路30と、データを受信し、メモリセルのアレイ28の障害パターン110および132に一致するコード化された受信データ130を供給し、コード化された受信データ130をメモリセルのアレイ28の障害パターン110および132の障害アドレス108に書き込ませるために書込み回路30を制御するよう構成された制御回路24とを含んでなるメモリシステム20を提供する。
【選択図】 図1
Description
Claims (10)
- メモリセルのアレイと、
該メモリセルのアレイのメモリセルに書き込むように構成された書込み回路と、
データを受信し、前記メモリセルのアレイ中の障害パターンに一致するコード化された受信データを供給し、前記メモリセルのアレイの前記障害パターンの障害アドレスに前記コード化された受信データを書き込むために前記書込み回路を制御するよう構成された制御回路と
を含んでなるメモリシステム。 - 前記制御回路は、前記受信データと、再構成された受信データと、数学演算によりコード化された前記受信データと、反転された前記受信データと、畳み込み処理された前記受信データとを含むグループのうちの少なくとも1つを含む、コード化された受信データを提供するよう構成されている請求項1に記載のメモリシステム。
- 前記障害パターンは、前記メモリセルのアレイの障害マップに格納され、前記コード化された受信データが前記メモリセルのアレイの前記障害パターンの前記障害アドレスに書き込まれると、前記障害パターンは使用されたものとしてマークされるものである請求項1に記載のメモリシステム。
- 前記制御回路は、コード化情報を含む前記コード化された受信データを前記メモリセルのアレイの前記障害パターンの前記障害アドレスに書き込む前記書込み回路に、該コード化情報を提供するよう構成されている請求項1に記載のメモリシステム。
- 前記制御回路は、前記受信データを書き込むための書込みアドレスを受信し、前記コード化された受信データを前記障害アドレスに書き込むように前記書込み回路を制御し、前記書込みアドレスが前記障害アドレスに一致することを示すためにアドレスマップに書き込むように構成されている請求項1に記載のメモリシステム。
- 前記メモリセルのアレイの前記メモリセルを読み出すように構成された読出し回路を含んでおり、前記制御回路は、読出しアドレスを受信し、該読出しアドレスと対応する障害アドレスとを調べ、前記メモリセルのアレイの該対応する障害アドレスにおいて読み出すように前記読出し回路を制御し、前記メモリセルのアレイからコード化情報を含む前記コード化された受信データを受信し、該コード化情報を使用して前記コード化された受信データをデコードして前記受信データを取得するよう構成されている請求項1に記載のメモリシステム。
- データを受信するステップと、
該受信したデータを、前記メモリのあるセクションにあるハード障害に一致させるステップと、
一致した前記受信したデータを前記メモリの前記セクションに書き込むステップと
を含んでなる、メモリにデータを格納する方法。 - 前記受信データが前記ハード障害にどのように一致したかを示すコード化情報を提供するステップと、
該コード化情報を前記メモリへと書き込むステップと
を含む請求項7に記載の方法。 - 書込みアドレスを受信するステップと、
一致した前記受信データを、前記メモリにおける前記セクションの位置を示す障害アドレスに書き込むステップと、
前記書込みアドレスが前記障害アドレスに対応することを示すようにアドレスマップに書き込むステップと
を含む請求項7に記載の方法。 - 読出しアドレスを受信するステップと、
アドレスマップにおいて、該読出しアドレスと対応するアドレスとを調べるステップと、
一致した前記受信データを取得するために、前記対応するアドレスにおいて前記メモリを読み出すステップと、
コード化情報を読み出すステップと、
前記受信データを取得するために、該コード化情報を使用して、一致した前記受信データをデコードするステップと
を含む請求項7に記載の方法。
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/454,463 US6839275B2 (en) | 2003-06-04 | 2003-06-04 | Memory system having control circuit configured to receive data, provide encoded received data to match a fault pattern in the array of memory cells |
Publications (2)
Publication Number | Publication Date |
---|---|
JP2004362587A true JP2004362587A (ja) | 2004-12-24 |
JP4023811B2 JP4023811B2 (ja) | 2007-12-19 |
Family
ID=33489745
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2004166593A Expired - Lifetime JP4023811B2 (ja) | 2003-06-04 | 2004-06-04 | メモリシステム |
Country Status (2)
Country | Link |
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US (1) | US6839275B2 (ja) |
JP (1) | JP4023811B2 (ja) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010262730A (ja) * | 2009-04-30 | 2010-11-18 | Internatl Business Mach Corp <Ibm> | 異機種混合ストレージ要素の容量を増大させる方法及びシステム |
JP2012074094A (ja) * | 2010-09-28 | 2012-04-12 | Citizen Holdings Co Ltd | 不揮発性半導体記憶装置 |
KR20140046386A (ko) * | 2012-10-10 | 2014-04-18 | 에이취지에스티 네덜란드 비.브이. | 고착 고장을 갖는 메모리 셀들을 수용하기 위한 데이터의 부호화 및 복호화 |
KR101543081B1 (ko) | 2012-10-10 | 2015-08-07 | 에이취지에스티 네덜란드 비.브이. | 고착 고장을 갖는 메모리 셀을 수용하기 위한 리던던트 비트의 인코딩 및 디코딩 |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP1434232B1 (en) * | 2001-08-13 | 2007-09-19 | Advanced Micro Devices, Inc. | Memory cell |
US7050326B2 (en) * | 2003-10-07 | 2006-05-23 | Hewlett-Packard Development Company, L.P. | Magnetic memory device with current carrying reference layer |
US7472330B2 (en) * | 2003-11-26 | 2008-12-30 | Samsung Electronics Co., Ltd. | Magnetic memory which compares compressed fault maps |
US7076320B1 (en) | 2004-05-04 | 2006-07-11 | Advanced Micro Devices, Inc. | Scatterometry monitor in cluster process tool environment for advanced process control (APC) |
US7415644B2 (en) * | 2004-10-22 | 2008-08-19 | International Business Machines Corporation | Self-repairing of microprocessor array structures |
US7221599B1 (en) | 2004-11-01 | 2007-05-22 | Spansion, Llc | Polymer memory cell operation |
US7260004B2 (en) * | 2006-01-12 | 2007-08-21 | International Busniess Machines Corporation | Method and apparatus for increasing yield in a memory circuit |
US8028192B1 (en) * | 2006-04-28 | 2011-09-27 | Symantec Operating Corporation | Method and system for rapid failback of a computer system in a disaster recovery environment |
US7894250B2 (en) * | 2009-03-17 | 2011-02-22 | Seagate Technology Llc | Stuck-at defect condition repair for a non-volatile memory cell |
US8996955B2 (en) | 2011-11-16 | 2015-03-31 | HGST Netherlands B.V. | Techniques for storing data in stuck and unstable memory cells |
KR101983274B1 (ko) | 2012-05-18 | 2019-05-30 | 삼성전자주식회사 | 상변화 랜덤 액세스 메모리 장치 및 센싱 방법 |
US8812934B2 (en) | 2012-12-12 | 2014-08-19 | HGST Netherlands B.V. | Techniques for storing bits in memory cells having stuck-at faults |
US8943388B2 (en) | 2012-12-12 | 2015-01-27 | HGST Netherlands B.V. | Techniques for encoding and decoding using a combinatorial number system |
US10699796B2 (en) | 2014-05-27 | 2020-06-30 | Hewlett Packard Enterprise Development Lp | Validation of a repair to a selected row of data |
WO2017030564A1 (en) * | 2015-08-18 | 2017-02-23 | Hewlett Packard Enterprise Development Lp | Post package repair for mapping to a memory failure pattern |
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US4669082A (en) * | 1985-05-09 | 1987-05-26 | Halliburton Company | Method of testing and addressing a magnetic core memory |
US5343426A (en) | 1992-06-11 | 1994-08-30 | Digital Equipment Corporation | Data formater/converter for use with solid-state disk memory using storage devices with defects |
DE69426818T2 (de) | 1994-06-10 | 2001-10-18 | St Microelectronics Srl | Fehlertolerantes Speichergerät, insbesondere des Typs "flash EEPROM" |
US5870617A (en) * | 1994-12-22 | 1999-02-09 | Texas Instruments Incorporated | Systems, circuits and methods for mixed voltages and programmable voltage rails on integrated circuits |
GB9614551D0 (en) | 1996-07-11 | 1996-09-04 | Memory Corp Plc | Memory system |
US6223301B1 (en) | 1997-09-30 | 2001-04-24 | Compaq Computer Corporation | Fault tolerant memory |
US6505305B1 (en) | 1998-07-16 | 2003-01-07 | Compaq Information Technologies Group, L.P. | Fail-over of multiple memory blocks in multiple memory modules in computer system |
EP1130600A1 (en) * | 2000-03-01 | 2001-09-05 | Hewlett-Packard Company, A Delaware Corporation | Data balancing scheme in solid state storage devices |
US6418068B1 (en) | 2001-01-19 | 2002-07-09 | Hewlett-Packard Co. | Self-healing memory |
-
2003
- 2003-06-04 US US10/454,463 patent/US6839275B2/en not_active Expired - Lifetime
-
2004
- 2004-06-04 JP JP2004166593A patent/JP4023811B2/ja not_active Expired - Lifetime
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2010262730A (ja) * | 2009-04-30 | 2010-11-18 | Internatl Business Mach Corp <Ibm> | 異機種混合ストレージ要素の容量を増大させる方法及びシステム |
JP2012074094A (ja) * | 2010-09-28 | 2012-04-12 | Citizen Holdings Co Ltd | 不揮発性半導体記憶装置 |
KR20140046386A (ko) * | 2012-10-10 | 2014-04-18 | 에이취지에스티 네덜란드 비.브이. | 고착 고장을 갖는 메모리 셀들을 수용하기 위한 데이터의 부호화 및 복호화 |
KR101543081B1 (ko) | 2012-10-10 | 2015-08-07 | 에이취지에스티 네덜란드 비.브이. | 고착 고장을 갖는 메모리 셀을 수용하기 위한 리던던트 비트의 인코딩 및 디코딩 |
KR101637065B1 (ko) | 2012-10-10 | 2016-07-06 | 에이취지에스티 네덜란드 비.브이. | 고착 고장을 갖는 메모리 셀들을 수용하기 위한 데이터의 부호화 및 복호화 |
Also Published As
Publication number | Publication date |
---|---|
JP4023811B2 (ja) | 2007-12-19 |
US20040246774A1 (en) | 2004-12-09 |
US6839275B2 (en) | 2005-01-04 |
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