JP2004362368A - Processor and exception handling method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To accurately identify an occurrence state and increase overall processing speed when an exception or interrupt occurs. <P>SOLUTION: When an exception occurs in a computing unit or data transfer unit connected to an exception bus 33, an exception occurrence signal is output. An exception handling part 6, upon detecting the exception occurrence signal, identifies the exception cause and notifies the exception occurrence to a bus master 3. The bus master 3 stops a currently executed data transfer instruction, saves values of a program counter showing the addresses where the instruction and the instruction to be executed next to the former are stored, in an executed instruction saving register 3c and a program counter saving register 25 respectively, and writes a leading address of a program for exception handling into the program counter 21 to pass the control to exception handling. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a processor and an exception handling method that perform various processes such as arithmetic processing in accordance with a read instruction, and more particularly to a processor and an exception handling method that reduce the processing time when an exception or an interrupt occurs.
[0002]
[Prior art]
At present, microprocessors are used in all electronic devices as well as computers and portable terminals. In a conventional microprocessor, an operation code for designating a process such as an operation is provided, and the operation unit is controlled by decoding the operation code.
[0003]
FIG. 9 is a functional block diagram illustrating a configuration example of a conventional processor.
The processor illustrated in FIG. 9 includes an instruction control unit 110 that acquires an instruction and issues an instruction, a data path unit 120 that performs an operation or the like in accordance with the instruction, and a determination process that determines an execution result of a process performed by the data path unit 120. And a unit 130. The data path unit 120 includes, for example, an integer operation unit 121, a floating-point operation unit 122, a read / write unit 123, and the like.
[0004]
The instruction control unit 110 decodes an instruction read via an external bus (not shown) and generates an internal control signal for executing the instruction. The data path unit 120 performs various calculations and the like according to a control signal from the instruction control unit 110. For example, the integer calculator 121 performs calculations such as addition and multiplication on integers. Further, the floating-point arithmetic unit 122 performs operations such as addition and multiplication on floating-point numbers. The read / write unit 123 reads and writes data from and to an external memory (not shown). The confirmation processing unit 130 determines whether or not the processing result of the data path unit 120 may be used as the confirmation value.
[0005]
By the way, when an exception or an interrupt occurs in such a processor, the processing result in the data path unit 120 usually needs to be determined by the determination processing unit 130 in the order of the instructions issued by the instruction control unit 110. There is. As a result, the state of occurrence of an exception or an interrupt can be accurately specified, the register state at this time can be held, and the subsequent instruction can be stopped. On the other hand, if the order of determining the execution results of the instructions is not performed in the order of the description of the instructions, the specification of the state of occurrence of the exception or the interrupt will be inaccurate.
[0006]
Note that there has been the following exception processing device that inhibits the occurrence of multiple exceptions when an exception occurs and improves the consistency of processing when returning from an exception (see Patent Document 1). When an exception is detected in an arithmetic unit that can execute simultaneously in parallel, the exception processing unit interrupts the operation of the arithmetic unit that has not completed execution of the instruction, and executes an exception handler such as a program counter or the number of interrupted instructions. Saves exception information required by. When the cause of the exception is removed and the process returns from the exception handling handler, re-execution of the interrupted instruction is repeated based on the number of saved instructions whose execution has been interrupted, and the sequence returns to the sequence before the occurrence of the exception. .
[0007]
[Patent Document 1]
JP-A-5-20070
[0008]
[Problems to be solved by the invention]
As described above, in a conventional processor, in order to accurately specify the state of occurrence of an exception or an interrupt, it is necessary to control the order in which the execution results of instructions are determined in the order in which the instructions are written. For this reason, extra hardware such as the determination processing unit 130 that controls the determination order of the execution results is required, and such control processing is a factor that hinders an increase in processing speed.
[0009]
Further, the exception handling device disclosed in Patent Document 1 has a structure in which, when an exception occurs, all the operations that have not been completed are interrupted, so that it is necessary to execute the operations again when returning. Yes, it hinders an increase in processing speed.
[0010]
The present invention has been made in view of such a problem, and when an exception or an interrupt occurs, a processor and an exception processing method capable of accurately specifying the state of occurrence and improving the overall processing speed The purpose is to provide.
[0011]
[Means for Solving the Problems]
In the present invention, in order to solve the above problem, in a processor operating according to a read instruction, an inter-register transfer unit for transferring data between registers, and an operation data register to which data is input through the inter-register transfer unit, And a result storage register from which data is output.When data is input to all the operation data registers, a predetermined operation process is performed using the input data, and the operation result is stored in the result storage register. A plurality of arithmetic means, each having a single arithmetic function, for interrupting processing upon writing and generating an exception and outputting an exception generating signal, and an exception generating signal line for transmitting the exception generating signal, Is detected, the cause of the exception is identified, the exception receiving means for notifying of the exception occurrence, and the information at the time of the exception occurrence The data transfer operation through the inter-register transfer means is controlled by reading and decoding the instruction in which information specifying the data transfer destination and transfer source registers is normally read and stored. Stopping the instruction being transferred by the notification of the occurrence of the exception, storing a value of a program counter indicating an address where the instruction and an instruction to be executed next are stored in the save register, and executing the exception processing. Transfer control means for transferring the control to the exception processing by writing a head address storing a program for the exception processing to the program counter.
[0012]
In such a processor, normally, the transfer control means performs a data transfer operation between the operation data register of the operation means and the result storage register of the same or another operation means through the inter-register transfer means. Controlled. Each operation means starts its operation when data is input to all the operation data registers. Therefore, the operation of each operation means is controlled only by the data transfer control by the transfer control means. When an exception occurs, the arithmetic unit interrupts the process and outputs an exception occurrence signal. Upon detecting the exception occurrence signal, the exception accepting unit identifies the cause of the exception and notifies the transfer control unit of the exception occurrence. The transfer control means stops the data transfer instruction being executed at that time, and stores the instruction and the value of the program counter indicating the address where the instruction executed next to the instruction is stored in the save register, Control is transferred to exception processing by writing the start address of the program for exception processing to the program counter. Therefore, the operation means other than the operation means in which the exception has occurred are automatically stopped after completion of each operation processing.
[0013]
According to another aspect of the present invention, there is provided an exception handling method for a processor operating in accordance with a read instruction, wherein data is input to an arithmetic data register to which data is input through inter-register transfer means for transferring data between registers. Performs a predetermined operation using the input data, writes the operation result in a result storage register to which data is output through the inter-register transfer means, and interrupts the process when an exception occurs to generate an exception occurrence signal. A plurality of output means, each having a single operation function, decode the instruction in which information specifying a data transfer destination and a transfer source register is described, and perform data transfer through the inter-register transfer means. The operation is controlled by controlling, and when the exception occurrence signal output from the arithmetic unit is detected, The cause of the exception is detected based on the externally generated signal, the instruction being transferred is stopped when the exception occurs, and the value of the program counter indicating the address where the instruction and the next instruction to be executed are stored is stored in the save register. An exception processing method is provided, wherein the method transfers the control to the exception processing by writing a leading address storing a program for executing the exception processing according to the cause of the exception to the program counter. You.
[0014]
In such an exception processing method, the operation of the arithmetic unit is controlled by controlling the data transfer between the arithmetic data register provided in the arithmetic unit and the result storage register through the inter-register transfer unit. When an exception occurs and an exception occurrence signal is output, the cause of the exception is identified based on the exception occurrence signal, the data transfer instruction being executed at this time is stopped, and this instruction and the instruction following this instruction are executed. The value of the program counter indicating the address where the instruction to be executed is stored is stored in the save register, and control is transferred to the exception processing by writing the start address of the program for the exception processing in the program counter.
[0015]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
FIG. 1 is a functional block diagram illustrating a configuration example of a processor according to the present invention.
[0016]
A processor 1 shown in FIG. 1 includes an instruction fetch unit (indicated as Fetch in the figure) 2 for acquiring an instruction and issuing an instruction, and an address bus 31, a data bus 32, and an exception bus 33 according to the input instruction. A bus master 3 for controlling the operation of various data transfer units and arithmetic units connected to the internal bus, an instruction cache 4a for storing instructions read from outside, and a processing result and data read from outside. A data cache 4b, an external bus I / F (interface) 5 for reading data and the like from the outside, and outputting a processing result to the outside, an exception processing unit 6 for monitoring occurrence of an exception and an external interrupt, Is provided.
[0017]
Further, the internal address bus 31 and data bus 32 are connected to, for example, a data transfer unit for performing data transfer processing with the outside and an arithmetic unit for performing various arithmetic processing. The data transfer unit includes a read unit (indicated as “Load” in the figure) 61, a write unit (the store) 62, a memory transfer unit (the Move) 63, a stack processor (the Stack) 64, and a data exchanger (the same) Swp) 65 is connected. In addition, as a computing unit, a comparator (the same Cmp) 66, an integer adder (the same Add) 67, an integer subtracter (the same Sub) 68, an integer multiplier (the same Mul) 69, and an integer divider (the same Div) 70 AND operation unit (And) 71, OR operation unit (Or) 72, exclusive AND operation unit (Xand) 73, exclusive OR operation unit (Xor) 74, bit inversion operation unit ( Not) 75, floating-point adder (Fadd) 76, floating-point subtractor (Fsub) 77, floating-point multiplier (Fmul) 78, floating-point divider (Fdiv) 79, and multiply-accumulate unit (The same Muladd) 80 is connected. In addition, a general-purpose register 81 is connected to the address bus 31 and the data bus 32.
[0018]
Among these arithmetic units and data transfer units, those which may cause an exception are connected to the exception processing unit 6 via an exception generation signal line (hereinafter referred to as an exception bus) 33 for transmitting an exception generation signal. Connected. For example, when the data transfer unit performs data transfer processing with the outside via the data cache 4b, an exception such as a page fault may occur. Further, the arithmetic unit generates an exception when a data input or an operation result outside the effective range is obtained due to an overflow, underflow, division by zero, or the like.
[0019]
Outside the processor 1, an interrupt controller 8 and a rewritable memory 10 are connected from an external bus I / F 5 via an external address bus 51 and a data bus 52.
[0020]
The instruction fetch unit 2 reads an instruction from the external memory 10 via the instruction cache 4a and the external bus I / F 5, and outputs the instruction to the bus master 3. The bus master 3 analyzes the input instruction, outputs a select signal to the address bus 31 to specify the address of the register, and in some cases, transmits an immediate value through the data bus 32, thereby providing the address bus 31 and the data bus 32. To control the data transfer operation between the data transfer units connected to. If the read instruction includes information on the number of times the instruction has been executed, this instruction is repeatedly executed the specified number of times.
[0021]
The instruction cache 4a stores an instruction read from the memory 10 through the external bus I / F 5, and when an address on the memory 10 specified by the instruction fetch unit 2 is hit, the stored instruction is stored in the instruction cache 4a. Output to extractor 2. The data cache 4b stores data read from the memory 10 via the external bus I / F 5, and when an address on the memory 10 specified by the read unit 61 hits, reads the stored data. 61. The external bus I / F 5 converts a signal inside the processor 1 into an external bus signal, and reads / writes data from / to an external device such as the memory 10.
[0022]
A read unit 61, a write unit 62, a memory transfer unit 63, a stack processor 64, a data exchanger 65, a comparator 66, an integer adder 67, an integer subtractor 68, an integer multiply connected to the address bus 31 and the data bus 32. Unit 69, integer divider 70, AND operator 71, OR operator 72, exclusive AND operator 73, exclusive OR operator 74, bit inversion operator 75, floating point adder 76, floating point The subtracter 77, the floating-point multiplier 78, the floating-point divider 79, and the product-sum operation unit 80 have a register for input and a register for output when there is an output. These are both connected to an address bus 31 and a data bus 32. When data is input through the data bus 32 to the input register specified by the bus master 3 through the address bus 31, predetermined data processing is started. Each of the data transfer unit and the arithmetic unit has only one processing function. The data processing is completed, and the obtained processing result data is stored in an output register. The stored data is transferred to another data transfer unit, arithmetic unit, or the like based on the address designation by the bus master 3.
[0023]
The reader 61 has one address register and one data register. When data is stored in the address register, the readout unit 61 accesses the external memory 10 through the data cache 4b and the external bus I / F 5 using the stored data as a readout address. Then, data is read from the corresponding address on the memory 10 and stored in the data register. If the output read address hits in the data cache 4b, the corresponding data is read from the data cache 4b and stored in the data register.
[0024]
The writer 62 includes one address register and one data register. The address register stores the address of the data write destination on the memory 10, and the data register stores the data to be written to the memory 10. . When data is input to both the address register and the data register, the external memory 10 is accessed through the data cache 4b and the external bus I / F 5, and the data is written to a corresponding address on the memory 10.
[0025]
The memory transfer device 63 includes two address registers and one transfer amount register. One address register stores an address to be a transfer source on the memory 10 or another memory, and the other address register. The register stores the destination address. The transfer amount register stores the data size of data read from the specified address. When these data are input, the external memory 10 or another memory is accessed through the data cache 4b and the external bus I / F 5, and data transfer between corresponding addresses is instructed.
[0026]
The stack processor 64 has a pointer register and a data register. The pointer register stores a stack pointer for specifying an address on the memory 10, and the data register writes data to the memory 10. Target data is stored. When these data are input, each operation of reading and writing from the memory 10 is determined by reading and writing in the data register. In the case of the reading operation, when the data storing operation to the pointer register is completed, the memory 10 is accessed. Then, data is read from the corresponding address and stored in the data register. In the case of a write operation, when the data storage operation to both the pointer register and the data register is completed, data is written to the corresponding address in the memory 10.
[0027]
The data exchanger 65 includes an address register, an input data register, and an output data register. When data storage in the input data register and the address register is completed, the data in the memory 10 indicated by the address register becomes Access is made through the data cache 4b and the external bus I / F5. Then, data is read from the corresponding address on the memory 10 and stored in the output data register.
[0028]
The comparator 66 includes two data registers for data input and a status register for storing the operation result. When data input to both of the two data registers is completed, the comparator 66 compares the input data. , And store the comparison result in the status register.
[0029]
The integer adder 67 has two input registers and one output register. When a numerical value to be added and a numerical value to be added are input to the two input registers, an integer is calculated using each data. Addition processing is performed, and the addition result is stored in an output register.
[0030]
The integer subtracter 68, the integer multiplier 69, and the integer divider 70 have two input registers and one output register, similarly to the integer adder 67. Similarly to the integer adder 67, when the data to be operated is input to the two input registers, the integer subtractor 68 performs the integer subtraction processing, the integer multiplier 69 performs the integer multiplication processing, and the integer. The divider 70 starts the integer division process and stores the operation result in the output register.
[0031]
Similarly to the integer adder 67, the AND operator 71, the OR operator 72, the exclusive OR operator 73, and the exclusive OR operator 74 also have two input registers and one output register, respectively. I have it. When the data to be operated is stored in the two input registers, the AND operation unit 71 performs an AND operation using the data, and stores the operation result in the output register. Similarly, when the data to be operated on is stored in the two input registers, the OR operation unit 72 performs the OR operation, the exclusive AND operation unit 73 performs the exclusive AND operation, and the exclusive OR operation. The unit 74 performs an exclusive OR operation and stores the operation result in an output register.
[0032]
The bit inversion operation unit 75 includes one input / output data register capable of inputting / outputting data. When the operation of storing data in the input / output register is completed, the bit inversion processing based on the stored data is started, and the operation result is calculated. Write back to I / O register.
[0033]
The floating-point adder 76, floating-point subtractor 77, floating-point multiplier 78, and floating-point divider 79 also have two input registers and one output register similarly to the integer adder 67 and the like. . When the data to be operated is stored in the two input registers, the floating-point adder 76 starts a floating-point addition process using these data, and stores the operation result in the output register. Similarly, when the data to be operated is stored in the two input registers, the floating-point subtractor 77 performs floating-point subtraction, the floating-point multiplier 78 performs floating-point multiplication, and the floating-point divider 79 performs floating-point division. Processing is started and the result of this operation is stored in the output register.
[0034]
The product-sum operation unit 80 has three input registers and an output register. When a numerical value to be operated is input to the three input registers, the product-sum operation unit 80 performs a product-sum operation using the input numerical values. Is stored in the output register.
[0035]
Among these data transfer units and arithmetic units, those which may cause an exception are connected to the exception bus 33. In the example shown in the figure, a comparator 66 of an arithmetic unit, an integer adder 67, an integer subtractor 68, an integer multiplier 69, an integer divider 70, a floating-point adder 76, a floating-point subtractor 77, a floating-point multiplier 78, The floating-point divider 79 and the product-sum operation unit 80, the data transfer unit read unit 61, write unit 62, memory transfer unit 63, stack processor 64, and data exchange 65 are connected to the exception bus 33.
[0036]
The general-purpose register 81 temporarily stores the processing result of each data transfer unit and the arithmetic unit, and transfers the stored data to another data transfer unit or arithmetic unit based on the address designation by the bus master 3.
[0037]
The externally connected memory 10 stores an instruction and data, and supplies an instruction or data of an address requested by the external bus I / F 5 via the address bus 51 via the data bus 52. The external address bus 51 and the data bus 52 have, in addition to the memory 10, for example, an I / F of a ROM (Read Only Memory) or a HDD (Hard Disk Drive) for storing programs and various data, and a data input / output port. And an I / F (not shown) for connecting to a keyboard, a monitor, various communication networks, and the like, and constitute a computer system. The computer system operates by the processor 1 reading and executing a program from a ROM, an HDD, or the like via the data bus 52 and reading / writing data from / to each unit on the data bus 52.
[0038]
When detecting an external state change such as completion of data reception, for example, the interrupt controller 8 generates an interrupt signal and transmits the external state change to the exception processing unit 6.
In the processor 1, when instructions are read from the memory 10 and sequentially supplied to the bus master 3, the bus master 3 operates in accordance with the instructions between the data transfer unit and the arithmetic unit connected to the address bus 31 and the data bus 32. Controls data transfer operation. Each data transfer unit and arithmetic unit has a register for data input from the data bus 32, and some data transfer units and all arithmetic units have registers for data output.
[0039]
Each data transfer unit and each arithmetic unit have a single processing function, and automatically execute predetermined data processing when data input to the input register is completed. Those having an output register store the processing result in the register. Thus, it is possible to operate the data transfer units and the arithmetic units only by specifying the transfer source register and the transfer destination register by the bus master 3. Therefore, the bus master 3 basically has to decode only the information designating the source and destination registers based on the issued instruction, simplifying the instruction and speeding up the decoding process in the bus master 3. ing. When an exception occurs during the processing, each data transfer unit and each arithmetic unit interrupts the processing being performed and outputs an exception occurrence signal. The exception occurrence signal is held until the cause of the exception is removed. The output of the exception generation signal is transmitted to the exception processing unit 6 via the exception bus 33.
[0040]
Further, the interrupt controller 8 generates an interrupt signal according to a change in an external state specified in advance. The interrupt signal is transmitted to the exception processing unit 6 via an interrupt signal line (not shown).
[0041]
When detecting that an exception occurrence signal or an interrupt signal has been output, the exception processing unit 6 creates data indicating the cause of the exception from these signals, and notifies the bus master 3 of the occurrence of the exception or the interruption. The reception of an interrupt signal is performed only when no exception has occurred. The exception bus 33 is connected to each data transfer unit and the arithmetic unit, and the exception processing unit 6 can accurately specify the data transfer unit or the arithmetic unit that has output the exception occurrence signal.
[0042]
The bus master 3 stops the transfer instruction being executed at that time, and transfers control to exception processing. Therefore, the data transfer device or the operation device other than the data transfer device or the operation device interrupted due to the occurrence of the exception automatically stops after the processing is completed.
[0043]
In this way, by controlling the data transfer between the registers, the operation of each data transfer unit and each operation unit that executes a single process is controlled. The processing function in which the exception has occurred can be accurately specified without interrupting the processing of the data transfer unit and the arithmetic unit. Further, since it is not necessary to execute the determination processing unlike the related art, there is no need to provide extra hardware for performing the determination processing, and the exception processing time can be reduced. Further, the processing of the data transfer unit and the arithmetic unit other than the case where the exception has occurred is not interrupted, so that the time required for return can be shortened.
[0044]
Next, the instruction fetch unit 2, the bus master 3, and the exception processing unit 6 will be described in more detail with reference to FIG. In FIG. 2, only one set of the address bus 31 and the data bus 32 is provided to simplify the description, but a plurality of sets may be provided. Further, the exception bus 33 does not need to correspond one-to-one with the address bus 31 and the data bus 32, and one set may be provided for a plurality of sets of the address bus 31 and the data bus 32.
[0045]
FIG. 2 is a block diagram showing each internal configuration of the instruction fetch unit, the bus master, and the exception processing unit.
As shown in FIG. 2, the instruction fetch unit 2 includes a program counter 21, an address generator 22, an instruction issuer 23, an instruction storage register 24, and a program counter save register 25.
[0046]
The program counter 21 sequentially outputs a count value to the address generator 22 in synchronization with an input clock signal (not shown). Also, it is connected to the address bus 31 and the data bus 32, and when selected by the select signal through the address bus 31, the count value is rewritten by the data transferred through the data bus 32.
[0047]
The address generator 22 outputs the count value output from the program counter 21 to the instruction issuer 23 as a read address in the memory 10.
[0048]
The instruction issuer 23 transfers the read address output from the address generator 22 to the memory 10 through the instruction cache 4a and the external bus I / F5. Then, the instruction read from the memory 10 is transferred to the instruction storage register 24. If the output read address hits in the instruction cache 4a, the corresponding instruction is read from the instruction cache 4a and transferred to the instruction storage register 24. Further, it is possible to receive a status signal from the status register of the comparator 66 and operate according to the status signal.
[0049]
The instruction storage register 24 holds the instruction output from the instruction issuer 23 and transfers the instruction to the bus master 3 at a predetermined timing. Further, it is connected to the address bus 31 and the data bus 32 and functions as a register for inputting data from the data bus 32. When selected by the select signal through the address bus 31, the data transferred through the data bus 32 The output instruction is rewritten.
[0050]
The program counter save register 25 is a register for temporarily saving a program counter indicating an address at which an instruction stopped at the time of occurrence of an exception or an instruction executed next to an instruction terminated by occurrence of an interrupt is stored. It is connected to the address bus 31 and the data bus 32, and functions as a data input register and an output register from the data bus 32. When selected by the select signal through the address bus 31, if it functions as an input register, the value of the program counter transferred through the data bus 32 is written. When functioning as an output register, the value of the program counter held is transferred through the data bus 32.
[0051]
The bus master 3 includes a decoder 3a, a remaining execution count saving register 3b, and an executing instruction saving register 3c.
The decoder 3 a is connected to the address bus 31 and the data bus 32, analyzes the instruction output from the instruction storage register 24 of the instruction fetch unit 2, outputs a select signal to the address bus 31, and outputs the select signal to the address bus 31. A register of each connected data transfer unit or each arithmetic unit is selected. At this time, by selecting the data transfer source register and the data transfer destination register, data transfer via the data bus 32 is performed between the selected registers. The decoder 3a can also generate immediate data in accordance with the input instruction, select a data transfer destination register, and transfer the immediate data to this register via the data bus 32. Further, when the input instruction includes information for specifying the number of times of execution, the same transfer operation can be repeated for the specified number of times.
[0052]
When the decoder 3a receives the Wait signal through the data bus 32 after outputting the select signal, the decoder 3a changes the control state of the data bus 32 and the corresponding address bus 31 until the reception of the Wait signal is canceled. Then, the output of the select signal and the immediate value according to the decoding of the new instruction is stopped. When a plurality of sets of the address bus 31 and the data bus 32 are provided, it is possible to continue data transfer to another bus in which the Wait signal is not received.
[0053]
The remaining execution count save register 3b is connected to the decoder 3a, and writes the remaining execution count of the repetition processing transferred from the decoder 3a. If there is a read from the decoder 3a, the stored remaining number of executions is transferred to the decoder 3a.
[0054]
The executing instruction save register 3c is connected to the decoder 3a, and writes an address on the memory 10 in which the executing instruction transferred from the decoder 3a is stored. If there is a read from the decoder 3a, the address of the stored instruction in execution on the memory 10 is transferred to the decoder 3a.
[0055]
Upon receiving an exception signal from the exception processing unit 6, the decoder 3a stops the instruction being transferred and saves the address of the stopped instruction in the executing instruction save register 3c. If the instruction being transferred is an instruction with an execution count, the remaining execution count is saved in the remaining execution count save register 3b. If an instruction with no execution count is being executed, the remaining execution count is set to 1 and saved in the remaining execution count save register 3b. When an interrupt signal is input, the same saving is performed after the instruction being transferred is completed.
[0056]
The exception processing unit 6 is connected to an exception bus 33 from which an arithmetic unit or a data transfer unit which may generate an exception outputs an exception generation signal, and an interrupt controller which generates an external interrupt. Further, an exception cause register 6a connected to the address bus 31 and the data bus 32 is provided.
[0057]
The exception cause register 6a stores data indicating an arithmetic unit or a data transfer unit which caused the exception or data indicating a cause of the occurrence of the interrupt. The stored data is stored in the address bus 31 and the data bus. The data can be read from the bus master 3 or the instruction fetch unit 2 using the bus 32.
[0058]
Upon detecting an exception occurrence signal output from an arithmetic unit or a data transfer unit connected to the exception bus 33 via the exception bus 33, the exception processing unit 6 identifies an arithmetic unit or a data transfer unit that causes an exception based on the exception occurrence signal. The specified exception cause is stored in the exception cause register 6a. In the state where no exception has occurred, if an interrupt signal from the interrupt controller is detected, the interrupt signal is accepted and the interrupt cause is stored in the exception cause register 6a. Further, when an exception or an interrupt occurs, an exception signal is output to the bus master 3 to notify that the exception or the interrupt has occurred. This exception signal is held until the cause of the exception is removed by an exception handler that performs exception processing, or until the interrupt processing is terminated by the interrupt handler.
[0059]
In such a processor 1, in the instruction fetch unit 2, the instruction issuer 23 sequentially reads instructions from the memory 10 using the address generated by the address generator 22 according to the program counter 21 as a read address, and sends the read instruction via the instruction storage register 24. Transfer to bus master 3.
[0060]
In the bus master 3, the decoder 3a analyzes the instruction output from the instruction storage register 24 and selects a register of a data transfer unit or an arithmetic unit (not shown) connected to the address bus 31. At this time, the data transfer source register and the data transfer destination register are selected, so that data transfer between the selected registers via the data bus 32 is performed. The data transfer unit or the arithmetic unit has a single function. When data is stored in an input register by such data transfer, a predetermined process is started. Store the operation result in the register. If an exception occurs during the processing, the processing is interrupted and an exception output signal is output through the exception bus 33. Further, reading of the provided registers is permitted, so that the contents of the registers can be read from the exception processing unit 6 or the bus master 3.
[0061]
Upon detecting that the exception occurrence signal has been output through the exception bus 33, the exception processing unit 6 specifies the data transfer unit or the operation unit of the exception cause, stores it in the exception cause register 6a, and outputs the exception signal to the bus master 3. I do. For example, when an exception occurs, the register can be read, so that the determination may be made based on this.
[0062]
When receiving the exception signal, the bus master 3 stops the data transfer process, stores the address of the stopped instruction in the executing instruction save register 3c, and stores the remaining execution count in the remaining execution count save register 3b. Thereafter, the value of the program counter 21 is read and stored in the program counter save register 25, and the start address of the exception handler is transferred to the program counter 21.
[0063]
As described above, even if only the data transfer unit or the operation unit where the exception occurred is stopped and the operation shifts to the exception handler, the operation unit or the data transfer unit where the exception has occurred is not ready for output data. Even if the subsequent instruction attempts to access the register of the arithmetic unit or the data transfer unit in which the exception has occurred, it is kept waiting, and the execution result of the subsequent instruction is not affected by the occurrence of the exception. Similarly, the input register of the arithmetic unit or the data transfer unit in which the exception has occurred is also waited for to be written. Therefore, by analyzing the data of the input register, the cause of the exception can be specified.
[0064]
Here, the operation of each arithmetic unit or data transfer unit, the exception processing unit 6, and the bus master 3 will be specifically described with reference to FIGS. Here, a case where an exception has occurred will be described as an example. The contents of the processing when an interrupt occurs are the same as those of the exception processing unit 6 and the bus master 3 at the time of exception except that the processing is performed after termination without interrupting the instruction. However, the exception handler becomes an interrupt handler.
[0065]
FIG. 3, FIG. 4, and FIG. 5 are diagrams illustrating an example of a sequence between each arithmetic unit or data transfer unit, the exception processing unit, and the bus master.
FIG. 3 is a sequence example from the occurrence of an exception to the output of an exception signal.
[0066]
At timing T101, an exception occurs in the arithmetic unit or the data transfer unit 9. Subsequently, at timing T102, the processing of the arithmetic unit or the data transfer unit 9 in which the exception has occurred is stopped. Further, at timing T103, an exception occurrence signal is output through the exception bus 33. Thereafter, at timing T104, register reading is permitted so that the input register and the output register can be read through the address bus 31 and the data bus 32. Thereafter, the arithmetic unit or data transfer unit 9 in which the exception has occurred waits for the cause of the exception to be removed.
[0067]
On the other hand, at timing T105, the exception processing unit 6 connected to the exception bus 33 detects the exception occurrence signal output from the arithmetic unit or the data transfer unit 9, and identifies the arithmetic unit or the data transfer unit 9 that has generated the exception. It is stored in the exception cause register 6a. Subsequently, an exception signal is output to the bus master 3.
[0068]
Next, a description will be given with reference to FIG. FIG. 4 is a sequence example from the output of the exception signal to the execution of the handler.
At timing T107, the exception signal output by the exception processing unit 6 is input to the bus master 3, and the execution of the data transfer instruction is stopped. Subsequently, at a timing T108, the address of the stopped data transfer instruction is saved in the executing instruction saving register 3c, and the remaining number of executions of the instruction with the number of executions is saved in the remaining execution number saving register 3b. At the subsequent timing T109, the program counter 21 of the instruction fetch unit 2 is saved in the program counter save register 25, and the address of the first instruction after returning from the exception processing is saved. Thereafter, at timing T110, the address of the exception handler is transferred to the program counter 21, and the control shifts to the exception handler. The exception handler performs different processing depending on the cause of the exception. The processing branches when the exception handler refers to the contents of the exception cause register 6a and confirms the contents of the register of the target arithmetic unit or the data transfer unit 9. Identify the cause and perform. The branch may be performed by the bus master 3 with reference to the exception cause register 6a. As described above, the contents of the program counter 21 are rewritten to the address of the exception handler, and the execution of the handler routine is started at the timing T111.
[0069]
Next, a description will be given with reference to FIG. FIG. 5 is an example of a sequence from execution of a handler to return to an exception.
When the handler routine is started at timing T111 in FIG. 4, the handler routine reads the register of the arithmetic unit or the data transfer unit 9 in which the exception has occurred, and performs processing for removing the cause of the exception. For example, when a page fault occurs in the data transfer device, paging is performed. When the exception is removed by the handler routine of the exception handler, the exception processing unit 6 and the arithmetic unit or the data transfer unit 9 detect that the cause of the exception has been removed.
[0070]
At timing T112, the cause of the exception of the arithmetic unit or the data transfer unit 9 in which the exception has occurred has been removed, and the output of the exception occurrence signal is stopped. Subsequently, at a timing T113, the arithmetic unit or the data transfer unit 9 is initialized and enters an initial state. On the other hand, at the timing T112, it is detected that the exception cause is also removed by the exception processing unit 6, and the exception cause is deleted from the exception cause register 6a. Subsequently, the output of the exception signal is stopped. In FIG. 4, the exception occurrence signal is stopped and the exception cause is deleted at the same timing. However, since these processes are performed individually, the timing may be shifted. Further, the exception processing unit 6 may delete the cause of the exception in response to the fact that the arithmetic unit or the data transfer unit 9 stops outputting the exception occurrence signal at the timing T112.
[0071]
By the above processing, the arithmetic unit or the data transfer unit 9 is initialized, and can be restored. The stop of the exception signal is notified to the bus master 3. At the next timing T114, the bus master 3 that has detected that the exception signal has been stopped returns the program counter. Subsequently, at timing T115, the remaining number of execution instructions and repetition instructions is restored. At this time, if necessary, data is transferred to the arithmetic unit or the data transfer unit 9 in which the exception has occurred, and the instruction in which the exception has occurred is re-executed. In this case, the address indicated by the executing instruction save register 3c is transferred to the program counter 21. After this processing is executed, the program counter stored in the program counter save register 25 is transferred to the program counter 21. Then, the process exits from the exception handler.
[0072]
Through the above processing, the processor 1 returns to the state before the occurrence of the exception. Then, at timing T116, the interrupted processing is resumed, and the reception of a new instruction is started.
[0073]
In the above description, the case where the address bus 31 and the data bus 32 are a single set has been described. However, when there are a plurality of these buses, the exception processing unit 6 determines whether the exception unit generates the arithmetic unit or the data transfer. The bus master to which the device 9 belongs is specified, and an exception signal is output only to the specified bus master. Other bus masters continue to execute the process. Further, the arithmetic unit or the data transfer unit 9 permits reading of all registers only for the bus master specified by the exception processing unit 6, and outputs a wait signal for selection from other bus masters.
[0074]
Next, an exception handling method using the processor of the present invention will be described. Here, as an example, the operation of the data reader 61 when an exception occurs in the data reader 61 shown in FIG. 1 and an exception handling method therefor will be described.
[0075]
FIG. 6 is a flowchart showing the flow of processing in the reader.
In step S01, the reading device 61 checks whether or not the data storage of the input register has been completed. If the data storage in the input register has not been completed, the wait state in step S01 is continued until the data storage is completed. If the data storage of the input register has been completed, the process proceeds to the next step S02.
[0076]
In step S02, the power save function is released. The power saving function is a function of suppressing a current supply amount to the processing circuit in a processing standby state in which data input necessary to start each processing is not performed in a data input register provided in each of the power saving functions. It is.
[0077]
In step S03, the data reading process starts. After the processing is started, when a select signal is received in the input register or the output register, a wait signal is output on the data bus 32 until the data reading processing is completed.
[0078]
In step S04, the external memory 10 is accessed through the data cache 4b and the external bus I / F 5 using the data stored in the input register as a read address to read data.
[0079]
In step S05, it is confirmed whether or not an exception has occurred during data reading. If no exception has occurred, the process proceeds to step S06. If an exception has occurred, the process from step S11 to step S15 when an exception has occurred is performed.
[0080]
In step S06, the read data is transferred to the output result storage register.
In step S07, the output of the Wait signal output in step S03 is stopped, and the data in the result storage register stored in step S06 can be read.
[0081]
In step S08, a power save function is set to reduce power consumption until the start of the next process.
Data reading is performed by the above procedure.
[0082]
Here, the processing when an exception occurs will be described.
In step S11, since an exception has occurred, the data reading process is stopped.
[0083]
In step S12, an exception occurrence signal is output to the exception bus 33 to notify the exception processing unit 6 that an exception has occurred.
In step S13, the reading of all registers is permitted to the specific bus master that has performed data transfer of the instruction in which the exception has occurred.
[0084]
In step S14, it is confirmed whether or not the cause of the exception has been removed. If the cause of the exception has not been eliminated, the standby state is continued in step S14. If the exception cause has been removed, the process proceeds to step S15.
[0085]
In step S15, the output of the exception occurrence signal is stopped, initialization is performed if necessary, and the process returns to a processable state. After the return, the process returns to step S07.
Through the above processing procedure, the occurrence of the exception is notified of the exception processing, and the exception handler removes the cause of the exception. When the cause of the exception has been removed and the state is ready for processing, the process returns to step S07 to resume the operation for the next instruction processing.
[0086]
Next, an exception handling method will be described.
FIG. 7 is a flowchart showing the flow of processing until the exception processing is activated.
[0087]
In step S21, an instruction specifying the data transfer source register and the data transfer destination register is received from the instruction fetching unit 2.
In step S22, the received instruction is decoded.
[0088]
In step S23, a select signal is output to the transfer source register and the transfer destination register via the address bus 31 according to the decoding result of the instruction. If the instruction includes an immediate value, the instruction signal is output to the transfer destination register via the address bus 31, and the immediate data is generated and output to the data bus 32.
[0089]
In step S24, it is confirmed whether or not an exception signal output by the exception processing unit 6 has been received. If an exception signal has been received, exception processing of step S25 is performed. If no exception signal has been received, the process proceeds to step S26.
[0090]
In step S25, an exception handler is started by executing exception processing described later, and the cause of the exception is removed. After the cause of the exception is removed, the process returns to step S21 to resume execution of the next instruction processing.
[0091]
In step S26, it is determined whether a Wait signal has been received from the data bus 32. If a Wait signal has been received, the process proceeds to step S27; otherwise, the process proceeds to step S28. In step S27, the current output state of the select signal is held. Therefore, the output state of the select signal in step S27 is held until the reception of the Wait signal is stopped by the determination in step S26.
[0092]
In step S28, when the number of executions is specified in the received instruction, it is determined whether or not the remaining number of executions is "0". Receive instructions. If it is not "0", the process proceeds to step S29. In step S29, the value of the remaining number of executions is reduced by "1", and the process returns to step S23. Therefore, the processes of steps S23 to S28 are repeated for the designated number of executions.
[0093]
Here, the exception processing will be described.
FIG. 8 is a flowchart showing the flow of exception processing.
In step S31, the data transfer processing is stopped. That is, the output of the select signal via the address bus 31 is stopped, and the output of the immediate data via the data bus 32 is stopped if the instruction includes an immediate value.
[0094]
In step S32, the address of the execution instruction whose data transfer process has been stopped and the remaining number of executions for the instruction whose execution number is specified are saved in the executing instruction saving register 3c and the remaining execution number saving register 3b, respectively. .
[0095]
In step S33, the contents of the program counter 21 are read out via the address bus 31 and the data bus 32 and written into the program counter save register 25.
[0096]
By the above processing, the data transfer instruction being executed is stopped, and the address of the instruction, the remaining execution count, and the program counter are saved in the respective save registers.
[0097]
In step S34, the head address of the exception handler that handles the exception is transferred to the program counter 21 via the address bus 31 and the data bus 32. By setting the program counter 21 to the top address of the exception handler, the next instruction to be executed becomes the top instruction of the exception handler, and the control is transferred to the exception handler.
[0098]
In step S35, instructions of the exception handler are sequentially executed by the processing of step S34. In the exception handler, a process for identifying the cause of the exception and removing the cause of the exception is performed. As a result, the cause of the exception is deleted, and accordingly, the output of the exception signal by the exception processing unit 6 is stopped, the data reader returns to the initial state, and the output of the exception occurrence signal is stopped. Thereafter, if necessary, data transfer is performed to the data reader that has generated the exception, and the instruction in which the exception has occurred is executed again. Finally, the program counter, execution instruction address, and remaining execution count stored in each save register are restored, and the process exits from the exception handler.
[0099]
In step S36, the exception removal processing by the exception handler is completed, and the execution is resumed.
Even if an exception occurs, the processing is stopped only in the arithmetic unit or data transfer unit that generated the exception, and the other operation units or data transfer units that were operating at that time performed the processing normally. After, it is stopped. Even if an attempt is made to access the register of the arithmetic unit or data transfer unit in which the exception has occurred, the state kept waiting by the Wait signal is continued. Therefore, the execution result of another arithmetic unit or data transfer unit is not affected by the occurrence of the exception. Therefore, if the cause of the exception of the arithmetic unit or the data transfer unit in which the exception has occurred is removed by the exception processing, and the instruction in which the exception has occurred is executed again and completed normally, the processing can be resumed as it is. As described above, there is no need to cause the arithmetic unit or the data transfer unit to execute the operation again except for the case where the exception has occurred when returning from the exception, and the time required for returning from the exception can be reduced. As a result, the overall processing speed can be improved.
[0100]
【The invention's effect】
As described above, in the processor of the present invention, the operation of each arithmetic unit is controlled only by the data transfer control by the transfer control unit. Therefore, when an exception occurs, the transfer control unit saves the execution instruction and the program counter in the save register and stops the processing when the exception occurs. At this time, the exception accepting means correctly specifies the arithmetic means in which the exception has occurred by the exception occurrence signal output from the arithmetic means. Furthermore, for example, by reading the register of the arithmetic means, the occurrence state of the exception can be specified more accurately. Also, since the operation means other than the one where the exception has occurred is automatically stopped after the processing is completed, there is no need to perform the operation again when the exception is returned. As a result, the time required for returning from the exception can be reduced, and the overall processing speed can be improved.
[0101]
Further, in the exception handling method of the present invention, when an exception occurs in a processor in which the operation of each arithmetic unit is controlled only by data transfer control between registers, an execution instruction and a program counter at the time of occurrence of the exception are saved in a save register. By reading the register of the arithmetic means in which the occurrence of the exception has been specified, the state of occurrence of the exception can be accurately specified.
[Brief description of the drawings]
FIG. 1 is a functional block diagram illustrating a configuration example of a processor according to the present invention.
FIG. 2 is a block diagram showing internal configurations of an instruction fetch unit, a bus master, and an exception processing unit.
FIG. 3 is a sequence example from the occurrence of an exception to the output of an exception signal.
FIG. 4 is an example of a sequence from output of an exception signal to execution of a handler.
FIG. 5 is a sequence example from execution of a handler to return from an exception.
FIG. 6 is a flowchart showing a flow of processing in a data reader.
FIG. 7 is a flowchart showing a flow of processing until exception processing is started.
FIG. 8 is a flowchart illustrating a flow of exception processing.
FIG. 9 is a functional block diagram illustrating a configuration example of a conventional processor.
[Explanation of symbols]
1 Processor 2 Instruction fetching device 3 Bus master 3a Decoder 3b Remaining execution count saving register .., 3c... Executing instruction save register, 4a... Instruction cache, 4b... Data cache, 5... External bus I / F, 6. ····· Exception processing unit, 6a ····· Exception cause register, 10 ···· Memory, 21 ···· Program counter, 22 ···· Address generator, 23 ... Instruction issuer, 24... Instruction storage register, 25... Program counter save register, 31... Address bus, 32. Data bus 33 ... Exception bus 61 ... Reader 62 ... ... Writer, 63 ... Memory transferer, 64 ... Stack processor, 65 ... Data exchanger, 67 ... Integer adder, 68: an integer subtracter, 69: an integer multiplier, 70: an integer divider, 71: an AND operator, 72: an logic Sum operator 73 ... Exclusive AND operator 74 ... Exclusive OR operator 75 ... Bit inversion operator 76 ... Floating point adder, 77 Floating point subtractor, 78 Floating point multiplier, 79 Floating point divider, 80 Product Sum operator, 81 ... General purpose register

Claims (10)

In a processor that operates according to the read instruction,
Inter-register transfer means for transferring data between registers;
An operation data register to which data is input through the inter-register transfer means; and a result storage register to which data is output. When data is input to all of the operation data registers, a predetermined value is set using the input data. A plurality of arithmetic means, each having a single arithmetic function, each of which has a single arithmetic function, performs an arithmetic processing of the arithmetic operation, writes the arithmetic result to the result storage register, interrupts the processing when an exception occurs, and outputs an exception occurrence signal,
Connected to an exception occurrence signal line for transmitting the exception occurrence signal, and detecting that the exception occurrence signal has been output, identifying the cause of the exception, and receiving an exception occurrence,
A save register for storing information at the time of occurrence of an exception; normally, by reading and decoding the instruction in which information designating a data transfer destination and a transfer source register is described, the data transmitted through the inter-register transfer means is read. Controlling a transfer operation, stopping the instruction being transferred by the notification of the occurrence of the exception, storing a value of a program counter indicating an address at which the instruction and an instruction to be executed next are stored in the save register, Transfer control means for transferring control to the exception processing by writing a start address in which a program for executing the exception processing is stored in the program counter;
A processor comprising: The exception accepting unit is further connected to an interrupt control unit for generating an external interrupt, and when detecting an external interrupt signal generated by the interrupt control unit, notifies the occurrence of an interrupt.
The transfer control means stores the instruction and the value of the program counter in the save register when the instruction being transferred is completed by the notification of the occurrence of the interrupt, and stores a program for executing the interrupt processing. 2. The processor according to claim 1, wherein control is transferred to said interrupt processing by writing a start address to said program counter. The transfer control means, when control is returned from the exception processing or the interrupt processing, returns the stopped instruction being transferred and stored in the save register and transfers the next instruction address to the program counter; 3. The processor according to claim 1, wherein the processing is returned. 2. The processor according to claim 1, further comprising input data transfer means for reading data input to said operation data register of said operation means and transferring it to a request source at least when said exception occurs. The exception accepting means includes an exception cause register that stores the exception cause and that can read the exception cause through data transfer means that transfers data in a register to a request source. The processor according to claim 1, wherein the data is stored in a register. The transfer control means selects a start address of the exception processing prepared for each exception cause according to the exception cause stored in the exception cause register and transfers the start address to the program counter. Item 6. The processor according to item 5. A data cache for temporarily storing data read from an external memory, and data to be written to the memory;
A first address register for inputting and outputting data through the inter-register transfer means; and a first data register. When data is input to the first address register, the first address is transmitted through the data cache. Data reading means for reading data from the memory indicated by data in a register and transferring the data to the first data register;
A second address register for inputting and outputting data through the inter-register transfer means; and a second data register, wherein data is input to both the second address register and the second data register. Data transfer means for transferring the data of the second data register to the memory indicated by the data of the second address register through the data cache;
A third address register and a fourth address register for inputting and outputting data through the inter-register transfer means, wherein data is input to both the third address register and the fourth address register; A memory transfer unit that performs data transfer on the memory through the data cache, using input data as a transfer source address and a transfer destination address, respectively;
Further having
2. The processor according to claim 1, wherein the data reading unit, the data transfer unit, and the memory transfer unit interrupt processing when an exception occurs and output the exception occurrence signal. At least upon occurrence of the exception, input data transfer means for reading data input to the address register or the data register of the data read means, the data transfer means and the memory transfer means and transferring the read data to a request source. The processor according to claim 7, wherein The instruction further includes information specifying the number of times of execution.
2. The transfer register according to claim 1, wherein the transfer control unit stores, in the save register, a remaining execution count at the time when the instruction whose execution count is specified is being executed when the exception occurs. Processor. In the exception handling method of the processor operating according to the read instruction,
When data is input to an arithmetic data register to which data is input through inter-register transfer means for transferring data between registers, a predetermined arithmetic process is performed using the input data, and the data is transferred through the inter-register transfer means. A plurality of arithmetic means, each having a single arithmetic function, for writing the arithmetic result to the output result storage register, interrupting the processing when an exception occurs, and outputting an exception occurrence signal, respectively, Controlling the operation by decoding the instruction in which information specifying the original register is described and controlling data transfer through the inter-register transfer means;
Upon detecting the exception occurrence signal output by the arithmetic unit, detecting the exception cause based on the exception occurrence signal,
When an exception occurs, the instruction being transferred is stopped, and the value of the program counter indicating the address where the instruction and the next instruction to be executed are stored is saved in a save register.
An exception processing method, wherein a control is transferred to the exception processing by writing a leading address at which a program for executing the exception processing according to the exception cause is stored in the program counter.

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