JP2004358976A - Printer, and device and method for generating driving waveform - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To prevent a deviation from a desired driving waveform from being caused by a cumulative error of driving waveform data, in the generation of a driving waveform for driving a driver element of a print head. <P>SOLUTION: The result of accumulation of a plurality of bits in an accumulation part of a driving waveform generating circuit is set at such a prescribed set value that a value, which is expressed by a specific higher-order bit in prescribed setting timing through the use of a floor signal, is not zero and that all lower-order bits except the specific higher-order bit are zero. In this case, the lower-order bits except the specific higher-order bit can also be cleared. Additionally, the prescribed setting timing can also be set as timing corresponding to starting and terminal ends of one cycle of the driving waveform. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a technique for generating a drive waveform for operating a drive element.

  2. Description of the Related Art In recent years, color printers that eject several colors of ink from an ink head have become widespread as output devices of computers, and are widely used for printing images processed by computers and the like in multiple colors and multiple gradations. In order to realize multi-tone printing, the weight of ink droplets ejected from nozzles of a recording head is controlled, and the size of ink dots formed on a print medium is controlled. .

  2. Description of the Related Art Conventionally, in an ink jet printer, it is common to perform binarization of whether or not to form an ink dot and express a halftone of a printed image by determining how many pixels in a certain area have an ink dot. Met. However, recently, by forming a plurality of ink dots of different sizes in one pixel using dark and light inks, it has become possible to express a halftone of a printed image with more gradations.

  For example, in an ink jet printer using a piezo element, in order to form ink dots having different sizes, it is necessary to control the meniscus (the surface shape of the ink at the nozzle opening) at the nozzle opening of the recording head and to control the ejection of ink droplets. Control of timing is important. Therefore, in order to form a desired ink dot, a drive waveform for operating the piezo element of the recording head is changed according to the size of the ink dot to be formed.

  The driving waveform for operating the piezo element is to store in advance the absolute value of the driving voltage at an arbitrary time in a memory, or to use a piezo element to form a capacitor to make a resistor having a different resistance value. It has been controlled by switching between devices. However, in the former case, a large amount of memory is required to store the driving waveform, and in the latter case, there is a problem that a pulse signal with complicated timing is required.

  In order to solve these problems, there has been proposed a method of obtaining a drive waveform in a programmable manner by determining the amount of change in voltage of the drive waveform at an arbitrary time and sequentially adding the values by an adder. I have.

  FIG. 8 is a block diagram showing an internal configuration of a conventional drive waveform generation circuit 100 for generating a drive waveform. FIG. 9 is an explanatory diagram showing a process of generating a drive waveform in the drive waveform generation circuit 100 shown in FIG. The drive waveform generation circuit 100 shown in FIG. 8 includes a memory 102, an accumulator 104, and a digital / analog converter 104. The drive waveform data indicating the waveform of the drive signal COM is stored in the memory 102. As shown in FIG. 9A, the drive waveform data ΔV1, ΔV2, and ΔV3 read from the memory 102 are sequentially accumulated in the accumulator 104 in synchronization with the clock signal CLK. Here, the drive waveform data is data representing a change amount of the drive voltage per one cycle t of the clock signal CLK. The high-order 10 bits of the 18-bit accumulation result are subjected to digital / analog conversion by the digital / analog converter 106 to generate the drive signal COM.

  In the method of FIG. 9, if the value obtained by accumulating the drive waveform data ΔV1, ΔV2, ΔV3,... Over one pixel section becomes zero, the start and end levels of the drive waveform completely match. However, in practice, the accumulated value of the drive waveform data over one pixel section often does not become zero. This is because a calculation error occurs when setting the drive waveform data. For example, the first drive waveform data ΔV1 is determined by dividing the design value δ1 of the voltage change in the accumulation period 8t by the number of accumulation periods (that is, 8) in the period 8t. When this division is not divisible, the drive waveform data ΔV1 includes a rounding error. This rounding error is the cause of the accumulated value error at the end of one pixel section. Such an error can be reduced by increasing the number of lower bits that are not subject to digital / analog conversion, and the error can be set to 0 for the upper bits. However, it is difficult to reduce the accumulation error to zero for the lower bits.

  In the conventional drive waveform generation device, there is a problem that such errors are sequentially accumulated for each pixel section, and a waveform deviated from a desired drive waveform is generated. That is, for example, when trying to obtain a drive waveform having a period T shown in FIG. 10A, as shown in FIG. 10B, the error e1 is accumulated for each period, and There is a problem that the starting end potential shifts and shifts from a desired driving waveform.

  SUMMARY An advantage of some aspects of the invention is to solve the above problems and to prevent errors from being accumulated when accumulating drive waveform data in a process of generating a drive waveform. .

  In order to solve at least a part of the above-described problem, the present invention sequentially accumulates a plurality of drive waveform data for generating a drive waveform, and sets a specific higher order among the accumulated results of the accumulated plurality of bits. The bits are converted from digital to analog and output as analog signals. At this time, the accumulation result of the plurality of bits is converted to a predetermined setting value such that the value represented by the specific upper bit is not zero at a predetermined setting timing, and all lower bits other than the specific upper bit become zero. Set. This eliminates the accumulation of errors in the drive waveform data, and can generate a desired drive waveform.

  Note that the accumulation result may be set to a predetermined setting value by clearing lower bits other than a specific upper bit.

  The predetermined setting timing is a timing corresponding to the start and end of one cycle of the drive waveform, and the drive waveform may be a periodic waveform in which the potentials at the start and end of one cycle match. By doing so, it is possible to clear the error of the driving voltage for each operation of the series of driving elements, and it is possible to generate a continuous periodic desired driving waveform.

  Note that the present invention can be realized in various forms such as a printing apparatus, a driving waveform generating apparatus, and a driving waveform generating method.

Embodiments of the present invention will be described in the following order based on examples.
A. Overall configuration of printing device:
B. Configuration and operation of drive waveform generator:
B-1. Internal configuration of drive waveform generator:
B-2. Drive waveform generation method:
B-3. Modification:

A. Overall configuration of printing device:
FIG. 1 is a block diagram showing the overall configuration of the printing apparatus of the present invention. As shown in FIG. 1, the printing apparatus includes a computer 90, a control circuit 40, a paper feed motor 23, a carriage motor 24 for performing main scanning, and a recording head 50.

  In the computer 90, application programs operate under a predetermined operating system. The operating system incorporates a video driver and a printer driver, and displays an image on a display and performs various image processing.

  The control circuit 40 includes an interface 41 for receiving a print signal and the like from the computer 90, a RAM 42 for storing various data, a ROM 43 for storing routines for various data processing, an oscillation circuit 44, a CPU, and the like. The control unit 45 includes a control unit 45, a drive waveform generation circuit 46, and an interface 47 for sending a print signal and a drive signal to the paper feed motor 23, the carriage motor 24, and the recording head 50.

  The RAM 42 is used as a reception buffer 42A, an intermediate buffer 42B, or an output buffer 42C. The print signal from the computer 90 is stored in the reception buffer 42A via the interface 41. This data is converted into an intermediate code and stored in the intermediate buffer 42B. Then, necessary processing is performed by the control unit 45 with reference to font data, graphic functions, and the like in the ROM 43, dot pattern data is developed, and stored in the output buffer 42C. The dot pattern data is sent to the recording head 50 via the interface 47.

  FIG. 2 is a block diagram showing an electrical configuration of the recording head 50. The recording head 50 includes a plurality of shift registers 51A to 51N corresponding to the number of nozzles, a plurality of latch circuits 52A to 52N, a plurality of level shifters 53A to 53N, a plurality of switch circuits 54A to 54N, and a plurality of piezo elements. 55A to 55N. The print signal SI is input to the shift registers 51A to 51N in synchronization with the clock signal CLK from the oscillation circuit 44. Then, the signals are latched by the latch circuits 52A to 52N in synchronization with the latch signal LAT. The latched print signal SI is amplified by the level shifters 53A to 53N to a voltage that can drive the switch circuits 54A to 54N, and is supplied to the switch circuits 54A to 54N. The drive signals COM from the drive waveform generation circuit 46 are input to the input sides of the switch circuits 54A to 54N, and the piezo elements 55A to 55N are connected to the output sides.

  For example, when the print signal SI is “1”, the switch circuits 54A to 54N supply the drive signal COM to the piezo elements 55A to 55N to operate them. As is well known, a piezo element is an element that distorts the crystal structure due to application of a voltage and converts electric-mechanical energy at an extremely high speed. Although not shown, when the drive signal COM is supplied to the piezo elements 55A to 55N, the piezo elements 55A to 55N are deformed accordingly, and the wall of the ink chamber is also deformed. This controls the ejection of ink droplets from the nozzles. Printing is performed by the ejected ink droplets adhering to the print medium.

B. Configuration and operation of drive waveform generator:
B-1. Internal configuration of drive waveform generator:
FIG. 3 is a block diagram showing the internal configuration of the drive waveform generation circuit 46. The drive waveform generation circuit 46 includes a memory 60 for storing drive waveform data supplied from the control unit 45, a first latch 62 for temporarily holding drive waveform data read from the memory 60, and a first latch 62 An adder 64 adds the output and an output of a second latch 66 described later, a second latch 66, and a digital / analog converter 70 that converts the output of the second latch 66 into an analog signal. Also provided are a voltage amplifying unit 72 for amplifying the converted analog signal to a voltage at which the piezo element operates, and a current amplifying unit 74 for supplying a current corresponding to the amplified voltage signal. The adder 64 and the second latch 66 constitute an accumulator 68 for accumulating the drive waveform data. Various signals are supplied from the control unit 45 to the drive waveform generation circuit 46. That is, the memory 60 is supplied with a first clock signal CLK1, a data signal representing drive waveform data, address signals A0 to A3, and an enable signal. The first latch 62 is supplied with a second clock signal CLK2 and a reset signal RESET. The second latch 66 is supplied with a third clock signal CLK3, a reset signal RESET, and a floor signal FLOOR described later. The reset signal RESET supplied to the first and second latches 62 and 66 is the same. The drive waveform generation circuit 46 functions as a drive waveform generation device together with the control unit 45, the RAM 42, and the ROM 43 shown in FIG.

B-2. Drive waveform generation method:
FIG. 4 is a timing chart showing the timing of writing drive waveform data in the memory 60. Prior to generation of the drive waveform COM, a data signal indicating the drive waveform data and an address of the data signal are supplied from the control unit 45 to the memory 60 in synchronization with the first clock signal CLK1. Although the data signal is one bit, as shown in FIG. 4, the drive waveform data is transferred one bit at a time by serial transfer using the first clock signal CLK1 as a synchronization signal. That is, when the drive waveform data is transferred from the control unit 45 to the memory 60, first, a plurality of data signals are supplied in synchronization with the first clock signal CLK1. Thereafter, address signals A0 to A3 indicating a write address for storing the data and an enable signal are supplied. The memory 60 reads the address signal at the timing when the enable signal is supplied, and writes the received drive waveform data to the address. Since the address signals A0 to A3 are 4 bits, a maximum of 16 types of drive waveform data can be stored in the memory 60.

  FIG. 5 is an explanatory diagram showing a process of generating a drive waveform in the drive waveform generation circuit 46. When the read address B is output as the address signals A0 to A3 after the writing of the drive waveform data into the memory 60 is completed, the first drive waveform data ΔV1 is output from the memory 60. Thereafter, when a pulse of the second clock signal CLK2 is generated, the drive waveform data ΔV1 is held in the first latch 62. In this state, when the pulse of the third clock signal CLK3 is generated next, the 18-bit output of the second latch 66 and the 16-bit output of the first latch 62 are added by the adder 64, and the addition result is obtained. Are held by the second latch 66. That is, as shown in FIG. 5, once the drive waveform data corresponding to the address signal is selected, every time the third clock signal CLK3 is received, the output of the second latch 66 is set to the drive signal. The values of the waveform data are accumulated.

  In the example shown in FIG. 5, the drive waveform data indicating that the voltage per one cycle t of the third clock signal CLK3 is increased by ΔV1 is stored in the address B. Therefore, when the address B becomes valid by the second clock signal CLK2, the voltage increases by ΔV1. Further, the address A stores ΔV2 = 0 as the drive waveform data, that is, a value indicating that the voltage is held. Therefore, when the address A becomes valid by the second clock signal CLK2, the waveform of the drive signal is maintained in a flat state with no increase or decrease. Further, the drive waveform data indicating that the voltage per one cycle t of the third clock signal CLK3 is reduced by ΔV3 is stored in the address C. Therefore, after the address C becomes valid by the second clock signal CLK2, the voltage decreases by ΔV3. The increase or decrease is determined by the sign of the data stored at each address.

Thus, of the 18-bit addition result added by the adder 64, the upper 10 bits of the voltage level data D ₀ are input to the digital / analog converter 70. The entire 18-bit addition result is re-input to the adder 64. As a result, the voltage level data D ₀ output from the second latch 66 changes stepwise as shown in FIG. This voltage level data D ₀ is converted by the digital / analog converter 70 to form the drive waveform shown in FIG.

FIG. 6 is a timing chart showing the timing at which the lower 8 bits of the second latch 66 are cleared. Here, it is assumed that the same drive waveform is repeated for each cycle T of one pixel section. The value VM of the voltage level data D ₀ at the start and end of one pixel section (hereinafter, referred to as “start end level”) has a predetermined value other than zero. The start and end of one pixel section are defined by a print timing signal PTS generated in the control unit 45. The print timing signal PTS is a signal for instructing to start outputting a drive waveform when forming an ink dot at each pixel position. The floor signal FLOOR is a signal indicating a timing t0 at which the lower 8 bits of the second latch 66 are cleared. When the floor signal FLOOR is input from the control unit 45 to the second latch 66, only the lower 8 bits of the second latch 66 are cleared, and the upper 10 bits are maintained at the start level VM. In the present embodiment, the floor signal FLOOR is input at the same timing as the print timing signal PTS, that is, for each cycle of the drive waveform. In this case, the print timing signal PTS may be used as the floor signal FLOOR. Further, this timing is not limited thereto, for example, the timing t0, t1, etc. that voltage level data D ₀ output from the second latch 66 becomes VM, floor signal at a timing previously known output value The lower 8 bits may be cleared by inputting FLOOR.

  According to this embodiment, since the error of the drive waveform data is cleared at a predetermined timing, accumulation of the error of the drive waveform data can be prevented, and a drive waveform having a desired complicated profile can be easily obtained.

B-3. Modification:
FIG. 7 is a block diagram illustrating a modification (accumulation unit 68a) of the accumulation unit 68 of the drive waveform generation circuit 46 in FIG. The former stage of the adder 64 and the latter stage of the second latch 66 are the same as those of the drive waveform generating circuit of the above-described embodiment, and therefore the description is omitted. In this modification, a selector 67 is provided between the adder 64 and the second latch 66. The data register 65 is connected to the selector 67.

  Of the 18 bits set in the data register 65, the upper 10 bits are equal to the start level VM of the drive waveform, and the lower 8 bits are zero. When the floor signal FLOOR is input to the second latch 66 and the selector 67, the selector 67 selects and outputs the 18-bit data of the data register 65, and the second latch 66 holds this data. As a result, the 18-bit data stored in the second latch 66 is forcibly rewritten to a set value in which the upper 10 bits are equal to the start level VM and the lower 8 bits are zero.

  As described above, by resetting the accumulation result in the accumulation unit 68a to a predetermined set value at a predetermined timing, it is possible to prevent the error of the drive waveform data from being accumulated, and to easily obtain a desired complicated data. The driving waveform of the profile can be obtained.

  In the above-described circuit of the first embodiment, it is considered that the accumulation result is set to a predetermined set value, that is, the starting end level VM by clearing the lower bits according to the floor signal FLOOR. be able to. As described above, in the present specification, the phrase “set the accumulation result to the predetermined set value” is not limited to the case where the accumulation result is forcibly set to the predetermined set value, but is used in the first embodiment. As described above, this has a wide meaning including a case where the accumulation result is substantially set to a predetermined set value by clearing only the lower bits.

  As described above, several embodiments of the present invention have been described. However, the present invention is not limited to such embodiments at all, and can be implemented in various modes without departing from the gist thereof. It is. The drive waveform generation device and the drive waveform generation method of the present invention can be applied not only to the printing apparatus described in the embodiment but also to a drive waveform generation device and a drive waveform generation method for driving other actuators and the like.

FIG. 1 is a block diagram illustrating an overall configuration of a printing apparatus according to the present invention. FIG. 2 is a block diagram illustrating an electrical configuration of a recording head. FIG. 3 is a block diagram illustrating an internal configuration of a drive waveform generation circuit according to the present invention. 5 is a timing chart showing timing for writing drive waveform data in a memory. FIG. 4 is an explanatory diagram illustrating a process of generating a drive waveform. FIG. 4 is an explanatory diagram for explaining a timing of inputting a floor signal in the driving waveform generation method of the present invention. FIG. 9 is a block diagram illustrating a modification of the accumulator of the drive waveform generation circuit according to the present invention. FIG. 10 is a block diagram illustrating an internal configuration of a conventional drive waveform generation circuit. FIG. 4 is an explanatory diagram illustrating a process of generating a drive waveform. FIG. 9 is an explanatory diagram illustrating accumulation of errors in a process of generating a drive waveform.

Explanation of reference numerals

23 ... Paper feed motor 24 ... Carriage motor 40 ... Control circuit 41 ... Interface 42 ... RAM
42A ... Reception buffer 42B ... Intermediate buffer 42C ... Output buffer 43 ... ROM
44 ... Oscillation circuit 45 ... Control unit 46 ... Drive waveform generation circuit 50 ... Recording head 51A-51N ... Shift register 52A-52N ... Latch circuit 53A-53N ... Level shifter 54A ~ 54N ... switch circuit 55A ~ 55N ... piezo element 60 ... memory 62 ... first latch 64 ... adder 65 ... data register 66 ... second latch 67 ... Selector 68 ... Accumulation unit 68a ... Accumulation unit 70 ... D / A converter 72 ... Voltage amplification unit 74 ... Current amplification unit 90 ... Computer 100 ... Drive waveform generation Circuit 102 ... Memory 104 ... Accumulation unit 106 ... D / A converter

Claims (9)

A printing apparatus that records an image on a recording medium based on a print signal of an image to be printed,
A print head having a plurality of nozzles and a plurality of drive elements for driving the plurality of nozzles to eject ink droplets,
A drive waveform generation circuit that generates a drive waveform transmitted to the plurality of drive elements;
With
The drive waveform generation circuit includes:
A memory for storing a plurality of drive waveform data for generating the drive waveform,
An accumulating unit for sequentially accumulating the drive waveform data sequentially read one by one at a predetermined read timing from the memory for each predetermined accumulation cycle;
A digital-to-analog converter for digital-to-analog conversion of a specific higher-order bit of the multi-bit accumulation result obtained by the accumulation unit and outputting it as an analog signal;
The accumulation result of the plurality of bits in the accumulation unit is such that the value represented by the specific upper bit is not zero at a predetermined setting timing, and all lower bits other than the specific upper bit become zero. A control unit for setting to a predetermined set value,
A printing device comprising: The printing device according to claim 1,
The printing device, wherein the control unit sets the accumulation result to the predetermined set value by clearing lower bits other than the specific upper bit. The printing device according to claim 1 or 2,
The predetermined setting timing is a timing corresponding to a start end and an end of one cycle of the driving waveform,
The printing apparatus according to claim 1, wherein the driving waveform is a periodic waveform in which the potential at the beginning and the end of one cycle match. A drive waveform generation device that generates a drive waveform for driving a drive element,
A memory for storing a plurality of drive waveform data for generating the drive waveform,
An accumulating unit that sequentially accumulates the drive waveform data one by one at a predetermined timing from the memory, one by one at regular intervals.
A digital-to-analog converter for digital-to-analog conversion of a specific higher-order bit of the multi-bit accumulation result obtained by the accumulation unit and outputting it as an analog signal;
The accumulation result of the plurality of bits in the accumulation unit is such that the value represented by the specific upper bit is not zero at a predetermined setting timing, and all lower bits other than the specific upper bit become zero. A control unit for setting to a predetermined set value,
A drive waveform generation device comprising: The drive waveform generation device according to claim 4, wherein
The drive waveform generating device, wherein the control unit sets the accumulation result to the predetermined set value by clearing lower bits other than the specific upper bit. The driving waveform generating device according to claim 4 or 5,
The predetermined setting timing is a timing corresponding to a start end and an end of one cycle of the driving waveform,
The drive waveform generation device is a drive waveform generation device, wherein the drive waveform is a periodic waveform in which the potential at the beginning and the end of one cycle match. A driving waveform generation method for driving a driving element,
(A) a step of sequentially selecting a plurality of drive waveform data for generating the drive waveform one by one at a predetermined timing;
(B) sequentially accumulating the selected drive waveform data at a constant accumulation cycle;
(C) digital-to-analog conversion of a specific higher-order bit of the accumulation result of the plurality of bits;
(D) determining the accumulation result of the plurality of bits such that at a predetermined setting timing, the value represented by the specific upper bit is not zero, and all lower bits other than the specific upper bit become zero. Setting a set value;
A driving waveform generation method comprising: The driving waveform generating method according to claim 7, wherein
The step (d) includes a step of setting the accumulation result to the predetermined set value by clearing lower bits other than the specific upper bit. The driving waveform generating method according to claim 7, wherein:
The predetermined setting timing is a timing corresponding to a start end and an end of one cycle of the driving waveform,
The driving waveform is a periodic waveform in which the potentials at the beginning and end of one cycle match.

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