JP2001121697A - Generation of waveform for driving drive element - Google Patents

Generation of waveform for driving drive element

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Publication number
JP2001121697A
JP2001121697A JP30736099A JP30736099A JP2001121697A JP 2001121697 A JP2001121697 A JP 2001121697A JP 30736099 A JP30736099 A JP 30736099A JP 30736099 A JP30736099 A JP 30736099A JP 2001121697 A JP2001121697 A JP 2001121697A
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JP
Japan
Prior art keywords
drive waveform
accumulation
frequency
waveform data
drive
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP30736099A
Other languages
Japanese (ja)
Inventor
Yuichi Nishihara
雄一 西原
Original Assignee
Seiko Epson Corp
セイコーエプソン株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Seiko Epson Corp, セイコーエプソン株式会社 filed Critical Seiko Epson Corp
Priority to JP30736099A priority Critical patent/JP2001121697A/en
Publication of JP2001121697A publication Critical patent/JP2001121697A/en
Application status is Pending legal-status Critical

Links

Abstract

(57) [Summary] To alleviate restrictions on a drive waveform in generation of a drive waveform [Solution] A plurality of drive waveform data for generating a drive waveform are sequentially accumulated at an accumulation frequency that can be changed as needed. Then, the accumulated multi-bit accumulation result is converted from digital to analog and output as an analog signal. Since the accumulation frequency of the drive waveform data can be changed at any time, even if the same drive waveform data is used, the inclination of the drive waveform can be changed by changing the accumulation frequency.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a technique for generating a driving waveform for operating a driving element.

[0002]

2. Description of the Related Art In recent years, as an output device of a computer,
2. Description of the Related Art A color printer that discharges several colors of ink from an ink head has become widespread, and is widely used for printing an image processed by a computer or the like in multiple colors and multiple gradations. In order to realize multi-gradation printing, the weight of ink droplets ejected from the nozzles of a recording head is controlled, and the size of ink dots formed on a print medium is controlled. .

Conventionally, an ink-jet printer binarizes whether or not to form an ink dot, and expresses a halftone of a printed image by determining how many pixels in a given area have an ink dot. Was common.
However, recently, by forming a plurality of differently sized ink dots in one pixel using light and dark inks,
It is possible to express a halftone of a print image with more gradations.

For example, in an ink jet printer using a piezo element, in order to form ink dots of different sizes, it is necessary to control the meniscus (the surface shape of the ink at the nozzle opening) at the nozzle opening of the recording head and to form the ink droplets. It is important to control the timing of the discharge. Therefore, in order to form a desired ink dot, a drive waveform for operating the piezo element of the recording head is changed according to the size of the ink dot to be formed.

The driving waveform for operating the piezo element has a different resistance value by using a method in which the absolute value of the driving voltage at an arbitrary time is previously stored in a memory or by utilizing the fact that the piezo element forms a capacitor. It has been controlled by switching the resistance between the piezo elements. However, in the former case, there is a problem that a large amount of memory is required to store the driving waveform, and in the latter case, a pulse signal with complicated timing is required.

In order to solve these problems, there is a method of obtaining a drive waveform in a programmable manner by determining the amount of change in voltage of the drive waveform at an arbitrary time and sequentially adding the values by an adder. Proposed.

FIG. 12 is a block diagram showing an internal configuration of a conventional drive waveform generation circuit 100 for generating a drive waveform. The drive waveform generation circuit 100 includes a memory 102
, Accumulator 104, digital / analog converter 106
And The drive waveform data indicating the waveform of the drive signal COM is stored in the memory 102.

FIG. 13 is an explanatory diagram showing a process of generating a drive waveform in the drive waveform generation circuit 100. As shown in FIG. 13A, the drive waveform data ΔV1, ΔV2, ΔV3 read from the memory 102 are sequentially accumulated in the accumulator 104 in synchronization with the clock signal CLK. Here, the drive waveform data is data representing a change amount of the drive voltage per one cycle t of the clock signal CLK. This accumulation result is digital-to-analog converted by the digital-to-analog converter 106,
The drive signal COM is generated.

[0009]

However, the number of drive waveform data that can be stored in the memory 102 is limited. Therefore, the types of the drive waveform COM that can be generated are also limited. Further, conventionally, in order to generate a more complicated drive waveform, it has been necessary to frequently rewrite the drive waveform data in the memory 102. However, it has sometimes been difficult in terms of time to generate a drive waveform.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-described problem, and has as its object to alleviate restrictions on a drive waveform in generating a drive waveform.

[0011]

Means for Solving the Problems and Their Functions / Effects To solve at least a part of the above-mentioned problems, the present invention provides:
A plurality of drive waveform data for generating a drive waveform are sequentially accumulated at an accumulation frequency that can be changed as needed, and the accumulated result of the accumulated plurality of bits is converted from digital to analog and output as an analog signal. Since the accumulation frequency of the drive waveform data can be changed at any time, even if the same drive waveform data is used, the inclination of the drive waveform can be changed by changing the accumulation frequency. As a result, restrictions on the drive waveform supplied to the drive element can be relaxed.

The accumulation frequency can be changed by controlling the on / off control of the pulse of the clock signal for setting the accumulation timing in the accumulation section.
By doing so, the accumulation frequency of the drive waveform data can be changed, so that the restriction on the type of inclination of the drive waveform supplied to the drive element can be relaxed.

Further, the change of the accumulation frequency is performed by accumulating the first drive waveform data which is not 0 at a constant first accumulation frequency and a first drive waveform portion which is substantially horizontal. The accumulation frequency may be changed so as to accumulate the first drive waveform data at a second accumulation frequency lower than the first accumulation frequency between the second drive waveform portion and the second drive waveform portion. This makes it possible to smoothly connect the first drive waveform portion and the second drive waveform portion.

The present invention can be realized in various forms such as a printing apparatus, a driving waveform generating apparatus, and a driving waveform generating method.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in the following order based on examples. A. Overall configuration of printing apparatus: Internal configuration of drive waveform generation device: D. Method of Generating Drive Waveform First embodiment of accumulation frequency changing unit: Second embodiment of the accumulation frequency changing unit:

A. FIG. 1 is a block diagram showing the overall configuration of a printing apparatus according to an embodiment of the present invention. This printing apparatus includes a computer 90 and a printer 99. The printer 99 includes the control circuit 4
0, a paper feed motor 23, a carriage motor 24 for performing main scanning, and a recording head 50.

In the computer 90, an application program operates under a predetermined operating system. A printer driver for generating print data to be supplied to the printer 99 is incorporated in the operating system.

The control circuit 40 includes an interface 41 for receiving print data and the like from the computer 90, a RAM 42 for storing various data, a ROM 43 for storing various data processing routines and the like, and an oscillation circuit 44.
And a control unit 45 including a CPU and the like, a drive waveform generation circuit 46, and an interface 47 for sending print data and drive signals to the paper feed motor 23, the carriage motor 24, and the recording head 50.

The RAM 42 is used as a receiving buffer 42A, an intermediate buffer 42B or an output buffer 42C. Print data from the computer 90 is stored in the reception buffer 42A via the interface 41. This data is converted into an intermediate code and stored in the intermediate buffer 42B. Then, necessary processing is performed by the control unit 45 with reference to font data, graphic functions, and the like in the ROM 43, dot pattern data is developed, and stored in the output buffer 42C. The dot pattern data is transmitted to the recording head 5 via the interface 47.
Sent to 0.

FIG. 2 is a block diagram showing the electrical configuration of the recording head 50. The recording head 50 includes a plurality of shift registers 51A to 51N corresponding to the number of nozzles, a plurality of latch circuits 52A to 52N, a plurality of level shifters 53A to 53N, and a plurality of switch circuits 54A to 54N.
And a plurality of piezo elements 55A to 55N. The print signal SI is input to the shift registers 51A to 51N in synchronization with the clock signal CLK from the oscillation circuit 44. Then, the signals are latched by the latch circuits 52A to 52N in synchronization with the latch signal LAT. The latched print signal SI is amplified by the level shifters 53A to 53N to a voltage that can drive the switch circuits 54A to 54N, and is supplied to the switch circuits 54A to 54N. The drive signals COM from the drive waveform generation circuit 46 are input to the input sides of the switch circuits 54A to 54N, and the piezo elements 55A to 55N are connected to the output sides.

The switch circuits 54A to 54N are, for example,
When the print signal SI is “1”, the drive signal COM is supplied to the piezo elements 55A to 55N to be operated, and when the print signal SI is “0”, it is shut off and not operated. As is well known, a piezo element is an element that distorts the crystal structure due to application of a voltage and converts electric-mechanical energy at an extremely high speed. Although not shown, when the drive signal COM is supplied to the piezo elements 55A to 55N, the piezo elements 55A to 55N deform accordingly, and the walls of the ink chambers also deform. This controls the ejection of ink droplets from the nozzles. Printing is performed by the ejected ink droplets adhering to the print medium.

B. Internal configuration of drive waveform generator: FIG.
5 is a block diagram showing an internal configuration of the drive waveform generation circuit 46. The drive waveform generation circuit 46 stores the drive waveform data supplied from the control unit 45 (see FIG. 1) in the memory 6.
0, a first latch 62 for temporarily holding the drive waveform data read from the memory 60, an adder 64 for adding an output of the first latch 62 and an output of a second latch 66 described later, 2 latch 66 and a digital / analog converter 70 for converting the output of the second latch 66 into an analog signal
And an accumulation frequency changing unit 80 that generates a timing signal Q80 indicating the timing at which the adder 64 performs accumulation and transmits the signal to the second latch 66. Further, a voltage amplifying unit 72 for amplifying the converted analog signal to a voltage at which the piezo element operates and a current amplifying unit 74 for supplying a current corresponding to the amplified voltage signal are provided. The adder 64 and the second latch 66 constitute an accumulator 68 for accumulating the driving waveform data.

Various signals are supplied from the control unit 45 to the drive waveform generation circuit 46. That is, the memory 60 is supplied with a first clock signal CLK1, a data signal representing drive waveform data, address signals A0 to A3, and an enable signal EN1. Further, the first latch 62 has a second clock signal CLK2 and a reset signal RE.
SET is supplied. The second latch 66 includes a timing signal Q80 generated by the accumulation frequency changing unit 80,
A reset signal RESET is supplied. A reset signal RESE supplied to the first and second latches 62 and 66
T is the same. Note that this drive waveform generation circuit 4
Reference numeral 6 denotes the control unit 45, the RAM 42, and the RO shown in FIG.
It functions as a drive waveform generator together with M43.

C. Driving Waveform Generation Method: FIG. 4 is a timing chart showing the timing of writing driving waveform data in the memory 60. Prior to generation of the drive waveform COM, a data signal indicating drive waveform data and an address of the data signal are supplied from the control unit 45 to the memory 60 in synchronization with the first clock signal CLK1. Although the data signal is one bit, as shown in FIG.
The drive waveform data is transferred bit by bit by serial transfer using the clock signal CLK1 as a synchronization signal.
That is, when the drive waveform data is transferred from the control unit 45 to the memory 60, first, a data signal for a plurality of bits is supplied in synchronization with the first clock signal CLK1. afterwards,
An address signal A0 to A3 representing a write address for storing this data and an enable signal EN1 are supplied. The memory 60 reads the address signal at the timing when the enable signal EN1 is supplied, and writes the received drive waveform data at the address. Since the address signals A0 to A3 are 4 bits, a maximum of 16 types of drive waveform data can be stored in the memory 60.

FIG. 5 is an explanatory diagram showing a basic process of generating a drive waveform in the drive waveform generation circuit 46.
When the read address B is output as the address signals A0 to A3 after the writing of the drive waveform data into the memory 60 is completed, the first drive waveform data Δ
V1 is output. Thereafter, the second clock signal CLK
When the second pulse is generated, the driving waveform data ΔV1 is held in the first latch 62. In this state, when the next pulse of the timing signal Q80 occurs, the second latch 66
And the 16-bit output of the first latch 62 are added by the adder 64, and the addition result is held in the second latch 66. That is, as shown in FIG. 5, once the drive waveform data corresponding to the address signal is selected, every time the timing signal Q80 is received thereafter, the output of the second latch 66 includes the drive waveform data of the drive signal. Values are accumulated. In the example of FIG. 5, the pulses of the timing signal Q80 are generated regularly at a constant period. However, as described later, the generation timing of these pulses can be arbitrarily changed at any time.

In the example shown in FIG. 5, the address B stores drive waveform data indicating that the voltage per pulse of the timing signal Q80 is increased by ΔV1. Therefore, when the address B is made valid by the second clock signal CLK2, the voltage increases by ΔV1. Further, the address A stores ΔV2 = 0 as the drive waveform data, that is, a value indicating that the voltage is held. Therefore, when the address A becomes valid by the second clock signal CLK2, the waveform of the drive signal is maintained in a flat state with no increase or decrease. Address C
Stores drive waveform data indicating that the voltage per pulse of the timing signal Q80 is reduced by ΔV3. Therefore, after the address C becomes valid by the second clock signal CLK2, the voltage decreases by ΔV3. The increase or decrease is determined by the sign of the data stored at each address.

In this way, the 1 added by the adder 64
Of the 8-bit addition result, the upper 10 bits of the voltage level data D 0 are input to the digital / analog converter 70. The entire 18-bit addition result is added to the adder 6
4 is input again. As a result, the voltage level data D 0 output from the second latch 66 changes stepwise as shown in FIG. This voltage level data D 0 is
5 is converted by the digital / analog converter 70.
The drive waveform shown in (b) is formed.

D. First Embodiment of Cumulative Frequency Changing Unit: FIG.
5 is a block diagram illustrating a configuration of a first embodiment of an accumulation frequency changing unit 80. FIG. The accumulation frequency changing unit 80 includes a clock signal generator 81 that generates a third clock signal CLK3.
, A selector control signal generation circuit 82, a plurality of counters 84A to 84N, a selector 86, and an inverter 87.
And an AND gate 88. Counter 84A
To 84N count the number of pulses of the third clock signal CLK3, and generate pulse signals Q84A to Q84 each time the counted number reaches a different predetermined value.
Generate N. The selector 86 outputs the outputs Q84A to Q84N from the counters 84A to 84N according to the signal from the selector control signal generation circuit 82 and the signal Q at a constant H level.
One is selected from H and a signal QL having a constant L level and output. The output of the selector is inverted by the inverter 87 and input to the AND gate 88 as the second enable signal EN2. AND gate 88 has a third
Clock signal CLK3 and the second enable signal EN2
Of the second latch 6 as a timing signal Q80.
6 (see FIG. 3). Note that the selector control signal generation circuit 82, the plurality of counters 84A to 84N, the selector 86, the inverter 87, and the AND gate 88 are turned on / off for turning on / off the pulse of the third clock signal CLK3. Functions as an off control unit.

FIG. 7 is an explanatory diagram showing a process of adjusting the inclination of the drive waveform by changing the frequency of occurrence of the pulse of the timing signal Q80. Third clock signal CL
The pulse of K3 is generated at a constant period t. During the period from time t1 to t2, the second enable signal EN2 is at H level.
The drive waveform data ΔV is kept at the level, and is accumulated every period t. On the other hand, in a period after the time t2, the second enable signal EN2 goes to the L level once for every two pulses of the third clock signal CLK3. The timing signal Q80 is the third clock signal CL
Since it is generated by taking the logical product of K3 and the second enable signal EN2, the signal has a period twice as long as the third clock signal CLK3 after time t2.
Therefore, after time t2, the accumulation cycle of the drive waveform data ΔV in the accumulator 68 is twice as long as the period from time t1 to t2, and a drive waveform having a 傾 き slope is generated.

FIG. 8 shows the type of the drive waveform data and the second enable signal E with respect to the third clock signal CLK3.
FIG. 7 is an explanatory diagram illustrating a relationship between a frequency of setting N2 to an L level and a gradient of a generated drive waveform. As described above, the memory 60 can store a maximum of 16 types of 16-bit drive waveform data. Most significant bit MS
Drive waveform data in which B is “0” (0000h to 7FFF
h) indicates a positive slope, and the drive waveform data whose MSB is “1” (8000h to FFFFh) indicates a negative slope. Here, h at the end of the drive waveform data in parentheses indicates that the data is represented in hexadecimal. In the first embodiment, the memory 60
Stores seven types of drive waveform data with positive and negative slopes and one type of drive waveform data (flat portion) with zero slope, and sets the remainder as one type. It is not always necessary to store the drive waveform data having a slope of 0. When a drive waveform having a slope of 0 is required, accumulation is not performed in the accumulation section 68 during that time, that is, the second enable signal EN2 may be set to L level during that time.

FIG. 8 shows the case where the slope of the drive waveform is 0 and positive. The drive waveform data is from 0000h
It takes a 16-bit value of 1FFFh. The memory 60 divides the value during this period into seven equal parts, and 0492h, 0
924h, 0DB6h, 1248h, 16DAh, 1B
The drive waveform data having seven types of positive slopes of 6Ch and 1FFFh is stored. When the second enable signal EN2 is always at the H level, the timing signal Q80 becomes the same as the third clock signal CLK3, and it is possible to generate a drive waveform having seven types of gradients as in the related art. The lowermost drive waveform data “0492h” is transferred to the third clock signal CLK.
It is assumed that a driving waveform having a slope of k can be obtained by accumulating in a cycle of 3. At this time, the other drive waveform data “09
24h ”to“ 1FFFh ”are slopes 2 k to 7 k, respectively.
Can be realized.

Although not shown, the memory 60 includes:
As drive waveform data having a negative slope, E000h, E493h, E925h, and EDB7, as in the case of the positive slope.
h, F248h, F6DBh, and FB6Dh are stored as 16-bit values of seven types.

By the way, as described with reference to FIG.
The timing signal Q80 is the second enable signal EN2
Are set to L level by a plurality of counters 84A to 84N.
It can be changed by setting. For example, for the third clock signal CLK3, the second enable signal E
Assuming that the frequency of setting N2 to the L level is one out of four times, the accumulator 68 performs accumulation three times during this time. At this time, if the drive waveform data “0492h” is used, 3
A drive waveform having a slope of / 4 (0.75 k) is obtained. Similarly, the frequency at which the second enable signal EN2 is set to the L level with respect to the third clock signal CLK3 is three times for four times.
In this case, the accumulator 68 performs one accumulation. At this time, if the drive waveform data “0492h” is used, a drive waveform having a 4 slope (0.25 k) is obtained. FIG. 8 shows each drive waveform data (“0000h”).
To “1FFFh”), the frequency of setting the second enable signal EN2 to the L level to obtain a drive waveform having a slope obtained by substantially equally dividing each of the slopes (k to 7k) of the drive waveform generated by “1FFFh”). ing.

As described above, the third clock signal CLK3
By changing the frequency at which the second enable signal EN2 is set to the L level, it is possible to realize more types of gradients than the type of each drive waveform data stored in the memory 60.

FIG. 9 is an explanatory diagram showing an example of a process of generating a drive waveform according to the first embodiment. As shown in FIG. 9 (a1), when the drive waveform COM in which the positive slope portion and the zero slope portion are continuous is generated, the drive waveform COM is actually transmitted to the piezo elements 55A to 55N (see FIG. 2). Drive waveform CO
For M, as shown in FIG. 9A2, overshoot may occur. This is considered to be due to the influence of the inductance component of the signal line between the drive waveform generation circuit 46 and the piezo elements 55A to 55N. Therefore, FIG.
As shown in (b1), the accumulation frequency is reduced by using the drive waveform data ΔV for generating the drive waveform portion having the positive slope between the portion having the positive slope and the portion having the zero slope. The generated drive waveform portion is generated. Such an operation can be realized by controlling the selector control signal generation circuit 82 (see FIG. 6). In this case, FIG.
As shown in 2), a portion having a positive slope and a portion having a slope of 0 can be smoothly connected, and overshoot can be reduced. Similarly, undershoot can be reduced.

As described above, according to the first embodiment, the memory 6
More types of gradients than the types of drive waveform data that can be stored in 0 can be easily obtained. Also, the memory 60
Without rewriting the driving waveform data in the
, A drive waveform having a desired complicated profile can be obtained only by changing the accumulation frequency.

E. Second Embodiment of Cumulative Frequency Changing Unit: FIG.
FIG. 9 is a block diagram illustrating a configuration of a second embodiment of the accumulation frequency changing unit 80. This accumulation frequency changing unit 80 is a so-called P
A frequency synthesizer 89 composed of an LL (phase locked loop) circuit is used. This frequency synthesizer 89
Is composed of a first frequency dividing circuit 91 having a frequency dividing ratio of n and a phase comparator 9
2, a low-pass filter 93, an amplifier 94, a voltage controlled oscillation circuit 95, and a second frequency dividing circuit 96 having a frequency dividing ratio of m. The clock signal generator 81 has a frequency f CLK3
The third clock signal CLK3 is generated. When the third clock signal CLK3 is input to the frequency synthesizer 89, the oscillation frequency (m) corresponding to the frequency division ratio n of the first frequency divider 91 and the frequency division ratio m of the second frequency divider 96 is determined. / N) ・
The timing signal of fCLK3 is obtained. That is, the cycle is the third
, A timing signal Q80 which is n / m of the cycle of the clock signal CLK3.

FIG. 11 is an explanatory diagram showing a process of accumulating drive waveform data in the second embodiment. In this example, the dividing ratios of the two dividing circuits 91 and 96 are 5 and 8, respectively. The generated timing signal Q80 is / of the cycle of the third clock signal CLK3.
The signal has a double cycle. Therefore, the accumulation period of the drive waveform data ΔV in the accumulation unit 68 is 8/5 times, and is 5/8.
A drive waveform having a double gradient is generated.

As described above, according to the second embodiment, the accumulation frequency of the driving waveform data can be easily changed by changing the frequency division ratio of the two frequency dividing circuits 91 and 96, so that the frequency can be easily changed. It becomes possible to obtain a drive waveform having a desired complicated profile.

Although some embodiments of the present invention have been described above, the present invention is not limited to such embodiments at all, and various embodiments may be made without departing from the scope of the present invention. Implementation is possible. The drive waveform generation device and the drive waveform generation method of the present invention can be applied not only to the printing apparatus described in the embodiment but also to a drive waveform generation device and a drive waveform generation method for driving other actuators and the like.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating an overall configuration of a printing apparatus as one embodiment of the present invention.

FIG. 2 is a block diagram illustrating an electrical configuration of a recording head.

FIG. 3 is a block diagram illustrating an internal configuration of a drive waveform generation circuit.

FIG. 4 is a timing chart showing the timing of writing drive waveform data in a memory.

FIG. 5 is an explanatory diagram illustrating a basic process of generating a drive waveform in a drive waveform generation circuit.

FIG. 6 is a block diagram showing a configuration of a first embodiment of an accumulation frequency changing unit 80;

FIG. 7 is an explanatory diagram showing a process of adjusting the inclination of a drive waveform by changing the frequency of occurrence of a pulse of a timing signal.

FIG. 8 is an explanatory diagram illustrating the relationship between the type of drive waveform data, the frequency of setting a second enable signal EN2 to L level with respect to a third clock signal CLK3, and the slope of a generated drive waveform. It is.

FIG. 9 is an explanatory diagram showing an example of a process of generating a drive waveform according to the first embodiment.

FIG. 10 is a block diagram showing a configuration of a second embodiment of the accumulation frequency changing unit 80;

FIG. 11 is an explanatory diagram showing a process of accumulating drive waveform data in the second embodiment.

FIG. 12 is a block diagram showing an internal configuration of a conventional drive waveform generation circuit.

FIG. 13 is an explanatory diagram illustrating a process of generating a drive waveform in a conventional drive waveform generation circuit.

[Explanation of symbols]

 23 ... Paper feed motor 24 ... Carriage motor 40 ... Control circuit 41 ... Interface 42 ... RAM 42A ... Reception buffer 42B ... Intermediate buffer 42C ... Output buffer 43 ... ROM 44 ... Oscillation circuit 45 ... Control unit 46 ... Drive waveform generation circuit 50 ... Recording heads 51A to 51N Shift registers 52A to 52N Latch circuits 53A to 53N Level shifters 54A to 54N Switch circuits 55A to 55N Piezo elements 60 Memory 62 First latch 64 Adder 66 Second latch 68 Accumulation section 70 D / A converter 72 Voltage amplification section 74 Current amplification section 80 Accumulation frequency change section 81 Clock signal generator 82 Selector control signal generation circuits 84A to 84N Counter 86 Selector 87 Inverter 88 ... AND gate 89 ... Frequency synthesizer The 90: Computer 91: First frequency divider 92: Phase comparator 93: Low-pass filter 94: Amplifier 95: Voltage controlled oscillator 96: Second frequency divider 99: Printer 100: Drive waveform generator 102: Memory 104: accumulation unit 106: D / A converter

Claims (5)

[Claims]
1. A drive waveform generator for generating a drive waveform for operating a drive element, comprising: a memory for storing a plurality of drive waveform data for generating the drive waveform; An accumulator that sequentially accumulates the drive waveform data sequentially read one by one at a predetermined read timing at an accumulable frequency that can be changed at any time; and an accumulative frequency per unit time in the accumulator. A drive frequency generator, comprising: an accumulation frequency change unit that changes the accumulation time at any time; and a digital / analog converter that performs digital / analog conversion of the multi-bit accumulation result obtained by the accumulation unit and outputs the result as an analog signal. apparatus.
2. The driving waveform generator according to claim 1, wherein the accumulation frequency changing unit generates a clock signal for setting an accumulation timing in the accumulation unit; An on / off control unit for controlling on / off of the pulse of the clock signal.
3. The driving waveform device according to claim 1, wherein the accumulation frequency changing unit converts the first driving waveform data that is not 0 at a constant first accumulation frequency in the accumulation unit. The first driving waveform portion generated by the accumulation and the second driving waveform portion that is substantially horizontal have a second accumulation frequency lower than the first accumulation frequency. A driving waveform generator that changes the accumulation frequency so as to accumulate the driving waveform data of the driving waveform data.
4. A method for generating a drive waveform for operating a drive element, comprising: (a) sequentially selecting a plurality of drive waveform data for generating the drive waveform one by one at a predetermined read timing. (B) sequentially accumulating the selected drive waveform data at an accumulative frequency that can be changed as needed; and (c) digital / analog converting the accumulation result of the plurality of bits. Drive waveform generation method provided.
5. A printing apparatus for performing printing by discharging ink droplets onto a print medium to form dots, comprising: a plurality of nozzles and a plurality of nozzles for driving the plurality of nozzles to discharge ink droplets. A printing apparatus, comprising: a print head having the driving element described above; and the drive waveform generating apparatus according to claim 1.
JP30736099A 1999-10-28 1999-10-28 Generation of waveform for driving drive element Pending JP2001121697A (en)

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