JP2004356212A - Ferroelectric thin film device, its manufacturing method, and ferroelectric memory - Google Patents

Ferroelectric thin film device, its manufacturing method, and ferroelectric memory Download PDF

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Publication number
JP2004356212A
JP2004356212A JP2003149440A JP2003149440A JP2004356212A JP 2004356212 A JP2004356212 A JP 2004356212A JP 2003149440 A JP2003149440 A JP 2003149440A JP 2003149440 A JP2003149440 A JP 2003149440A JP 2004356212 A JP2004356212 A JP 2004356212A
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ferroelectric thin
thin film
layer
ferroelectric
crystal
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JP2003149440A
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Japanese (ja)
Inventor
Masabumi Ofune
正文 小舟
Shuichi Fukuoka
修一 福岡
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Kyocera Corp
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Kyocera Corp
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Abstract

<P>PROBLEM TO BE SOLVED: To provide a ferroelectric thin film device which is capable of improving the degree of crystal orientation of an unpolarized ferroelectric thin film, and to provide its manufacturing method and a ferroelectric memory. <P>SOLUTION: A lower electrode layer 2, an oxide crystalline nucleus layer 3, a ferroelectric thin film layer 4, and an upper electrode layer 5, are successively laminated on a base substrate 1 for the formation of the ferroelectric thin film device. The ferroelectric thin film layer 4 has a crystal orientation rate of 60% or above when it is unpolarized. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

【0001】
【発明の属する技術分野】
本発明は、強誘電体薄膜素子及びその製法並びに強誘電体メモリーに関し、特に、ベース基板上に下部電極層、酸化物からなる結晶核層、強誘電体薄膜層、上部電極層を順次積層してなり、メモリー等に好適に使用される強誘電体薄膜素子及びその製法並びに強誘電体メモリーに関するものである。
【0002】
【従来技術】
従来より、メモリー用部品として、DRAM、SRAM、フラッシュメモリー、EEROM等の半導体メモリーが数多く使用されている。
【0003】
しかしながら、DRAMではメモリーセルの臨界電荷量の下限値から低電圧化が制限され、またフラッシュメモリーでは高電圧発生回路が必要であり、デイスターブ防止のために本質的に低電圧化が困難である。
【0004】
これに対し強誘電体メモリー(FeRAM)は、強誘電体特有の自発分極を利用した不揮発性メモリーであって、その高速書込み読出しや、強誘電体薄膜の薄層化に対応して低電圧動作が可能となり、低消費電力化に大きく寄与できる等の特徴から、従来の不揮発性メモリーのみならず、SRAMやDRAM等の殆どのメモリーに置き換わる可能性を有している。
【0005】
強誘電体メモリー(FeRAM)は、個々の電極セルが形成された強誘電体薄膜素子に、スイッチングトランジスタによって選択的に電圧が印加され、強誘電体の自発分極の向きを電界の方向によって変化させる。これが記憶情報の「1」あるいは「0」の書込みに相当するものである。電界を取り去っても自発分極自体は消滅しないので、この分極に応じた電荷が電極上に残ることになる。
【0006】
この保存された記憶情報を読み出す際には、再び強誘電体薄膜上に形成された電極に電圧を印加させると、電極上の電荷量に依存して配線に流出する電荷量が異なってくる。その結果生じる配線の電位差によって、記憶情報の内容、即ち「1」あるいは「0」を判定することになる。このようにして、強誘電体薄膜素子にメモリーとしての機能が付与されることになる。
【0007】
このような特徴を有する強誘電体薄膜素子は、従来、例えば、シリコン基板上に下部電極の金属膜が形成され、その上部に強誘電体薄膜層、上部電極の金属膜を順次積層して形成される。強誘電体薄膜層の成膜方法は、ゾルゲル法、MOD法、MOCVD法、レーザアブレーション法、CVD法、スパッタ法等があり、製造方法の簡易化の点から、ゾルゲル法やMOD法が好適に用いられている。
【0008】
例えば、ゾルゲル法の場合、強誘電性結晶に相当するように金属元素比を調整したゾル液を作製し、この溶液をスピンコートなどの方法によって、ベース基板上に設けた下部電極上に塗布後、基板加熱をおこないゲル化した膜を作製する。その後、酸素含有雰囲気でアニール処理を行い結晶性の強誘電体薄膜を得る。その後、強誘電体薄膜上に上部電極を形成することで強誘電体薄膜素子を得ることができる(例えば、特許文献1参照)。
【0009】
【特許文献1】
特開平11−318514号公報
【0010】
【発明が解決しようとする課題】
しかしながら、上記のようなゾルゲル法により作製された従来の強誘電体薄膜層では、通常、強誘電体薄膜層形成直後は分極方向がランダムであり、DC電圧を印加する分極処理によって分極方向を揃え配向させることから、強誘電体薄膜層内部に残留応力が生じ、読込みや書込みのために電圧を繰り返し印加したときの繰り返し疲労により、分極が劣化するという問題があった。
【0011】
また、ゾルゲル法で作製された強誘電体薄膜層では結晶粒が粗大となることから、強誘電体薄膜層の結晶粒子毎の配向性にばらつきが生じ、強誘電体薄膜層上に形成された電極セル毎の電気特性に大きなばらつきが生じ誤動作の原因となっていた。
【0012】
さらに、ゾルゲル法で作製された強誘電体薄膜層は結晶粒が粗大であるため、表面の凹凸が大きく、強誘電体薄膜層上に形成する電極の配線の微細化ができず、強誘電体メモリー(FeRAM)として用いる場合、FeRAMの高集積化が困難であった。
【0013】
また、ゾルゲル法で作製された強誘電体薄膜層では結晶粒が粗大であるためボイドが存在し、これにより絶縁劣化が生じ、信頼性が低くなるという問題があった。さらには、強誘電体薄膜素子の製造時の再現性が低いという問題もあった。
【0014】
本発明は、強誘電体薄膜を結晶化するアニール処理直後、即ち未分極状態における強誘電体薄膜の結晶の配向性を高めることができる強誘電体薄膜素子及びその製法並びに強誘電体メモリーを提供することを目的とする。
【0015】
さらには、結晶粒子毎の配向性の均一性を高め、微結晶からなる強誘電体薄膜とすることでメモリー機能の高集積化と高信頼性化を達成でき、さらに強誘電体薄膜素子の製造時の再現性を高められる強誘電体薄膜素子及びその製法並びに強誘電体メモリーを提供することをも目的とする。
【0016】
【課題を解決するための手段】
本発明の強誘電体薄膜素子は、ベース基板上に下部電極層、酸化物からなる結晶核層、強誘電体薄膜層、上部電極層を順次積層してなる強誘電体薄膜素子であって、前記強誘電体薄膜層の未分極時における結晶の配向率が60%以上であることを特徴とする。
【0017】
本発明の強誘電体薄膜素子では、強誘電体薄膜層の未分極時における結晶の配向率が60%以上であるため、DC電圧を印加する分極処理によって強誘電体薄膜層内部に発生する残留応力を小さくでき、連続電圧印加時の繰り返し疲労による分極劣化を著しく少なくすることができる。
【0018】
また、本発明の強誘電体薄膜素子は、ベース基板と下部電極層との間に、SiOからなる絶縁膜が形成されていることを特徴とする。このような強誘電体薄膜素子では、SiOからなる絶縁膜を、Si単結晶基板上に作製されたスイッチング用トランジスタ等の集積回路の保護膜とすることができる。
【0019】
さらに、本発明の強誘電体薄膜素子は、ベース基板が、Si単結晶、サファイア単結晶、MgO、SrTiOのいずれかであることを特徴とする。このような強誘電体薄膜素子では、Si単結晶やサファイヤ単結晶、MgO、SrTiOを適用することで強誘電体メモリーとして、機能させることができるとともに、強誘電体薄膜を用いたBAWフイルターやSAWレゾネータあるいはSAWフイルタを作製することができる。
【0020】
本発明の強誘電体薄膜素子の製法は、ベース基板上に下部電極層、酸化物からなる結晶核層、強誘電体薄膜層、上部電極層を順次積層してなる強誘電体薄膜素子の製法であって、ベース基板上に、下部電極層、結晶核層を順次形成した後、該結晶核層上にアモルファス状の強誘電体薄膜層を形成し、圧力1.4〜180MPaの酸素を含有する不活性ガス中において400〜600℃の温度範囲で等方加圧アニール(HIP)処理して、前記強誘電体薄膜層を結晶化した後、該強誘電体薄膜層上に上部電極層を形成することを特徴とする。
【0021】
本発明の強誘電体薄膜素子の製法では、アモルファス状の強誘電体薄膜層が結晶化するときに、酸化物からなる結晶核層の結晶格子に沿って成長することから配向性が高くなる。さらには、HIP処理により低温で焼結することから、微粒で均一性の高い粒子が得られ、凹凸が少なくなって表面平坦性が高くなり、製造時の再現性が高い強誘電体薄膜素子を得ることができる。
【0022】
【発明の実施の形態】
図1は、本発明の強誘電体薄膜素子の断面模式図である。符号1はベース基板、2は下部電極層、3は酸化物からなる結晶核層、4は強誘電体薄膜層、4aは強誘電体薄膜層4を構成する結晶粒子、5は上部電極層、6はベース基板1と下部電極2との間に形成された絶縁膜である。
【0023】
ベース基板1はSi単結晶、サファイア単結晶、MgO、SrTiOからなるもので、下部電極2は、界面層に格子歪を残留させにくく、連続動作における信頼性を高めるという理由から、Si単結晶の(110)面上に形成されていることが望ましい。
【0024】
下部電極層2はPt、Ir、Pd等の貴金属をスパッタ法や蒸着法で成膜することにより形成されている。さらに、下部電極層2の上面には、PbTiO、LiTaO、LiNbO等のペロブスカイト構造や、SrBiTa等のビスマス層状構造からなる酸化物の結晶核層3が高温スパッタ法等で成膜されている。酸化物からなる結晶核層3の上面には強誘電体薄膜層4がスパッタ法、ゾルゲル法等により形成され、強誘電体薄膜層4は、未分極時における結晶の配向率が60%以上とされている。配向率は、特には70%以上とされていることが望ましい。
【0025】
また、強誘電体薄膜層4は、0.01〜0.1μmの微細な結晶粒子4aから構成されている。電極層2、5は膜厚100〜300nm、強誘電体薄膜層4は膜厚50〜400nm、絶縁膜6は膜厚50〜500nmとされている。
【0026】
本発明の強誘電体薄膜素子の製法について説明する。先ず、Si単結晶等のベース基板1に、スパッタ法や蒸着法で絶縁膜6を形成し、この絶縁膜6上に、スパッタ法や蒸着法で下部電極層2を形成し、この下部電極層2上に、結晶核層3を高温スパッタ法等で形成し、この結晶核層3上に、所望の組成となるように、スパッタ法等によりアモルファスの状態で強誘電薄膜層4を成膜する。
【0027】
この後、例えば、約1〜20%の酸素を含有した不活性ガス、例えばArガスやNガスであって、圧力1.4〜180MPaとされている雰囲気中で、強誘電薄膜層4を等方加圧しながら、400〜600℃の温度範囲で等方加圧アニール(HIP)処理する。
【0028】
これにより、アモルファス状の強誘電薄膜層が結晶化することになるが、結晶核層3の結晶格子に沿って成長することから、配向した膜が形成されることになる。ここで、強誘電薄膜層4には、分極モーメントPrが大きく、且つ低電圧で分極反転をさせる必要があるために抗電界Ecの低い材料、例えばPb(Zr,Ti)Oを主成分としたペロブスカイト型強誘電体や、SrBiTa等を主成分としたビスマス層状構造等で構成されている。
【0029】
また、等方加圧アニール(HIP)の条件において、加圧力を1.4〜180MPaの範囲に設定した理由は、1.4MPaより小さい加圧の場合、結晶の配向が進まず配向率αが60%以上とならないからである。さらに180MPaより高加圧を加えた場合、一旦結晶化した強誘電体薄膜と、結晶核として成膜した酸化物からなる結晶核層との界面において、再びアモルファス層が生成され、結晶の配向性を低下させるとともに、強誘電体としての機能喪失領域が大きくなることから、メモリー等への適用ができなくなるからである。加圧力は、特には、1.7〜20MPaであることが望ましい。
【0030】
また、アニール温度を400〜600℃としたのは、400℃よりも低い場合には結晶化は図れるものの緻密な薄膜が得られず、600℃よりも高い場合には結晶粒子が粗大となるからである。特には、450〜520℃であることが望ましい。
【0031】
その後、強誘電体薄膜層4の上面に、上部電極層5がスパッタや蒸着により成膜され、電極の一部をエッチングなどにより除去して配線パターンが形成されメモリーとての機能が付与されるのである。
【0032】
このような強誘電体薄膜素子の製法によれば、HIP処理するため低温で結晶化でき、これにより微粒子且つ均一で緻密な結晶が得られ、強誘電体薄膜4の表面粗さRmsが約十nm以下と表面の凹凸を著しく小さくでき、表面平坦性の高い強誘電体薄膜を得ることができる。そのため、強誘電体薄膜4上に形成される配線パターンの微細化とともに、高集積化が可能になる。
【0033】
以上のように構成された強誘電体薄膜素子では、未分極時の状態で強誘電体薄膜のC軸方向へ結晶が高い配向度で配向していることから、連続電圧印加時の繰り返し疲労による分極劣化を著しく少なくすることが可能になる。さらには、緻密な強誘電体薄膜層となるため、ボイドが連続的に存在することが無くなり、これにより、絶縁性向上ととも信頼性を高めた強誘電体薄膜素子を得ることができる。さらには、低温かつ等方加圧アニール処理することから、高い結晶性が微粒子で得られるため、製造時の繰り返し再現性が高く、基板毎のばらつきを抑えた安定した強誘電体薄膜素子を得ることができる。
【0034】
強誘電体薄膜素子を用いた強誘電体メモリーは、Si単結晶からなるベース基板にトランジスタ等の回路を集積化させ、その上部にSiOからなる絶縁膜が形成された後、下部電極層、酸化物からなる結晶核層、強誘電体薄膜層、上部電極層を順次積層して作製される。
【0035】
【実施例】
Si単結晶からなるベース基板のSi(100)面上に、SiO膜をスパッタ法で400nm成膜し、その上面にPtをスパッタ法で200nm成膜し、さらにその上面に結晶核となるPbTiOの層を500℃の高温スパッタ法で30nm成膜した。
【0036】
その後、rfマグネトロンスパッタリング法によって、セラミックターゲットを用いて、組成が0.384PbZrO−0.376PbTiO−0.24Pb(Zn1/3Nb2/3)Oのアモルファス状の厚さ270nmからなる正方晶からなる強誘電体薄膜層を形成した。
【0037】
その後、20%の酸素を含有したAr混合不活性ガスを用いて、1〜180MPaの加圧力で、且つ、500℃の温度範囲で等方加圧アニール(HIP)処理を行い、結晶化と磁器の緻密化を行った。ここで、強誘電体薄膜層は正方晶であることから(001)面の配向性αを求めた。
【0038】
図2に、等方加圧アニール(HIP)において、処理温度を500℃に固定させ、20%の酸素を含有したAr混合不活性ガスによる加圧条件を変化させた時の、結晶性と配向性を示すX線回折図を記載する。
【0039】
この図2から、(a)は加圧条件が1MPaである時のX線回折図であり、配向性αは2%と無配向であり、(b)は加圧条件が1.3MPaである時のX線回折図であり、配向性αは51%と配向性が未だ不充分である。
【0040】
これに対して図2(c)は、加圧条件が1.8MPaである時のX線回折図であり、配向性αは95%と著しく高い配向性を示した。図2(d)は、加圧条件が8.8MPaである時のX線回折図であり、配向性αは78%と高い配向性を示した。図2(e)は、加圧条件が17.7MPaである時のX線回折図であり、配向性αは77%と高い配向性を示した。図2(f)は、加圧条件が176.5MPaである時のX線回折図であり、配向性αは60%と配向性は加圧が高まると徐々に低下するものの、比較的高い配向性を示した。
【0041】
尚、図2に記載された以外に圧力1.4MPaで加圧したところ、配向性αは85%であり、圧力180MPaで加圧したところ配向性αは60%であった。
【0042】
図2(g)に、等方加圧アニール(HIP)する前のX線回折図を示す。この図2(g)から、等方加圧アニール(HIP)する前では結晶性が確認されないことがわかる。
【0043】
また、圧力1.8MPaとして温度を400℃にしてアニールしたところ、配向性αは93%であり、600℃でアニールしたところ配向性αは98%であった。
【0044】
さらに、等方加圧アニール(HIP)の加圧条件を17.7MPaより高くしていくと、Pb(Zr,Ti)Oを主成分とした結晶層の配向性は高い状態で維持されているが、ペロブスカイト結晶相のX線強度が低下してくる。これは透過電子顕微鏡による断面観察と電子線回折により、結晶核として成膜したPbTiOと、強誘電層薄膜層との界面にアモルファス層が再び生成したことと残留応力によるものと考えられる。ここで、アモルファスとして生成された厚みは、透過電子顕微鏡による観察において、176.5MPaの時、約10nmであった。
【0045】
尚、図2において、Peroはペロブスカイトのピークを意味し、Ptはプラチナ電極のピークを示し、さらにPero及びPtに付記された括弧内の数字は結晶の面指数を示す。
【0046】
図3(a)に、等方加圧アニール(HIP)において、処理温度を500℃に固定させ、20%の酸素を含有したAr混合不活性ガスの加圧条件を変化させた時の、分極モーメントPと電界Eの関係を示す。図3(a)には加圧条件で1.8MPaから176.5MPaと変化させた時のP−Eヒステリシスループであり、いずれの条件においても強誘電性を示すループが得られている。
【0047】
一方、比較例として示した図3(b)は、従来技術である酸化性雰囲気下で700℃、2時間アニールして結晶化させたときのP−Eヒステリシスループである。通常、分極モーメントPr(電界0における分極Pの値)は約10μC/cm以上が求められるが、図3(a)で示した条件で等方加圧アニール(HIP)処理した場合、約11〜14μC/cmと所望の特性が得られているのに対して、比較例で示した図3(b)の大気圧焼成では約4μC/cmと低くメモリー用途としては適さない。
【0048】
さらに、低電圧で分極反転を行わせるためには抗電界Ec(分極モーメント0における電界Eの値)の値が小さい方が良いが、図3(a)で示した実施例においては、分極モーメントPrの値が高いにもかかわらず、抗電界Ecは75〜90kV/cmであり、低電圧での動作が可能な120kV/cmより充分小さくメモリー用途に適した特性を有している。
【0049】
さらに、等方加圧アニール(HIP)の条件を1.8MPa、500℃に設定して、20%の酸素を含有したAr混合不活性ガス中で1時間処理を行った結果、平均結晶粒子は80nmと微小結晶であり、強誘電体薄膜層の表面粗さRmsは3nmと優れた表面平坦性を有しており、強誘電体薄膜上面に形成される電極配線の微細化と密着性が大幅に向上することが判る。
【0050】
さらに、本発明の実施例に示した強誘電体薄膜素子の上下電極間の絶縁性においても100kV/cmにおける漏れ電流は1×10−7A/cm以下であり、充分な絶縁性が保たれていることがわかった。さらに、連続的に電圧を印加する繰り返し疲労試験を行ったところ、1×1010回後においても分極の劣化は見とめられなかった。
【0051】
さらに、等方加圧アニール(HIP)処理時間を、1分から3時間の間で変化させた結果、いずれの場合においても所望の強誘電体薄膜素子を得る事が出来た。
【0052】
一方、酸化性雰囲気下で700℃、2時間アニールして結晶化させた従来の場合には、平均結晶粒子は3μm、強誘電体薄膜層の表面粗さRmsは約200nm、強誘電体薄膜素子の上下電極間の100kV/cmにおける漏れ電流は3×10−5A/cmであり、連続的に電圧を印加する繰り返し疲労試験を行ったところ、1×1010回後において分極が劣化した。
【0053】
また、ベース基板をサファイヤ単結晶においても同様な効果を得ることができた。このように、本発明に依れば、特にメモリー用途に適した強誘電体薄膜素子とその製造方法を得ることができる。また、強誘電体薄膜を用いたBAWフイルターやSAWレゾネータあるいはSAWフイルタをも得ることができる。
【0054】
【発明の効果】
本発明の強誘電体薄膜素子によれば、アモルファスの強誘電薄膜層を結晶化するときに等方加圧アニール(HIP)処理することで、未分極時の状態で強誘電体薄膜の結晶の配向率が高くなるため、連続電圧印加時の繰り返し疲労による分極劣化を著しく少なくすることができる。また、緻密な強誘電体薄膜層となるためボイドが連続的に存在することが無くなり、絶縁性向上ととも信頼性を高めた強誘電体薄膜素子を得ることができる。さらには、製造時の繰り返し再現性が高く、基板毎のばらつきを抑えた安定した強誘電体薄膜素子を得ることができる。
【図面の簡単な説明】
【図1】本発明の強誘電体薄膜素子の断面模式図である。
【図2】等方加圧アニールにおけるX線回折図である。
【図3】(a)は本発明の強誘電体薄膜の分極Pと電界Eのヒステリシスループを示し、(b)は従来の酸化雰囲気で結晶化させた強誘電体薄膜の分極Pと電界Eのヒステリシスループを示す図である。
【符号の説明】
1・・・ベース基板
2・・・下部電極層
3・・・酸化物からなる結晶核層
4・・・強誘電体薄膜層
5・・・上部電極層
6・・・ベース基板と下部電極との間に形成された絶縁膜
[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a ferroelectric thin film element, a method for producing the same, and a ferroelectric memory, and in particular, a lower electrode layer, a crystal nucleus layer made of an oxide, a ferroelectric thin film layer, and an upper electrode layer sequentially laminated on a base substrate. The present invention relates to a ferroelectric thin film element suitably used for a memory or the like, a method of manufacturing the same, and a ferroelectric memory.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, many semiconductor memories such as DRAM, SRAM, flash memory, and EEROM have been used as memory components.
[0003]
However, in the DRAM, the lowering of the voltage is limited from the lower limit of the critical charge of the memory cell, and in the flash memory, a high voltage generating circuit is required, and it is essentially difficult to lower the voltage in order to prevent disturbance.
[0004]
On the other hand, a ferroelectric memory (FeRAM) is a nonvolatile memory using spontaneous polarization peculiar to a ferroelectric, and operates at a low voltage in response to high-speed writing / reading and thinning of a ferroelectric thin film. It is possible to replace not only the conventional nonvolatile memory but also almost all memories such as SRAM and DRAM because of the feature that it can greatly contribute to lower power consumption.
[0005]
In a ferroelectric memory (FeRAM), a voltage is selectively applied by a switching transistor to a ferroelectric thin film element on which individual electrode cells are formed, and the direction of spontaneous polarization of the ferroelectric is changed according to the direction of an electric field. . This corresponds to writing "1" or "0" of the stored information. Even when the electric field is removed, the spontaneous polarization itself does not disappear, so that a charge corresponding to the polarization remains on the electrode.
[0006]
When reading out the stored information, if a voltage is applied again to the electrode formed on the ferroelectric thin film, the amount of charge flowing out to the wiring differs depending on the amount of charge on the electrode. The content of the stored information, that is, “1” or “0” is determined based on the resulting potential difference of the wiring. In this way, a function as a memory is given to the ferroelectric thin film element.
[0007]
Conventionally, a ferroelectric thin film element having such characteristics is formed by, for example, forming a metal film of a lower electrode on a silicon substrate, and sequentially stacking a ferroelectric thin film layer and a metal film of an upper electrode thereon. Is done. The method of forming the ferroelectric thin film layer includes a sol-gel method, a MOD method, a MOCVD method, a laser ablation method, a CVD method, a sputtering method, and the like. Used.
[0008]
For example, in the case of the sol-gel method, a sol liquid in which the metal element ratio is adjusted so as to correspond to a ferroelectric crystal is prepared, and this solution is applied onto a lower electrode provided on a base substrate by a method such as spin coating. Then, the substrate is heated to produce a gelled film. Thereafter, annealing is performed in an oxygen-containing atmosphere to obtain a crystalline ferroelectric thin film. Thereafter, a ferroelectric thin film element can be obtained by forming an upper electrode on the ferroelectric thin film (for example, see Patent Document 1).
[0009]
[Patent Document 1]
JP-A-11-318514
[Problems to be solved by the invention]
However, in the conventional ferroelectric thin film layer manufactured by the sol-gel method as described above, the polarization direction is usually random immediately after the formation of the ferroelectric thin film layer, and the polarization direction is aligned by a polarization process of applying a DC voltage. Due to the orientation, a residual stress is generated inside the ferroelectric thin film layer, and there is a problem that polarization is deteriorated due to repeated fatigue when a voltage is repeatedly applied for reading or writing.
[0011]
In addition, since the crystal grains are coarse in the ferroelectric thin film layer manufactured by the sol-gel method, the orientation of each crystal grain of the ferroelectric thin film layer varies, and the ferroelectric thin film layer is formed on the ferroelectric thin film layer. A large variation occurs in the electrical characteristics of each electrode cell, causing a malfunction.
[0012]
Furthermore, since the ferroelectric thin film layer produced by the sol-gel method has coarse crystal grains, the surface of the ferroelectric thin film has large irregularities, making it impossible to miniaturize the wiring of electrodes formed on the ferroelectric thin film layer. When used as a memory (FeRAM), it has been difficult to achieve high integration of the FeRAM.
[0013]
Further, the ferroelectric thin film layer manufactured by the sol-gel method has a problem that voids exist due to coarse crystal grains, which causes insulation deterioration and lowers reliability. Further, there is a problem that reproducibility at the time of manufacturing the ferroelectric thin film element is low.
[0014]
The present invention provides a ferroelectric thin film element capable of improving the crystal orientation of a ferroelectric thin film immediately after an annealing treatment for crystallizing a ferroelectric thin film, that is, in an unpolarized state, a method for producing the same, and a ferroelectric memory. The purpose is to do.
[0015]
Furthermore, by increasing the uniformity of the orientation of each crystal grain and forming a ferroelectric thin film composed of microcrystals, high integration and high reliability of the memory function can be achieved. It is another object of the present invention to provide a ferroelectric thin film element capable of improving reproducibility at the time, a method of manufacturing the same, and a ferroelectric memory.
[0016]
[Means for Solving the Problems]
The ferroelectric thin film element of the present invention is a ferroelectric thin film element in which a lower electrode layer, a crystal nucleus layer made of an oxide, a ferroelectric thin film layer, and an upper electrode layer are sequentially stacked on a base substrate, The ferroelectric thin film layer has a crystal orientation ratio of 60% or more when not polarized.
[0017]
In the ferroelectric thin film element of the present invention, since the crystal orientation ratio when the ferroelectric thin film layer is not polarized is 60% or more, the residual generated inside the ferroelectric thin film layer by the polarization process of applying a DC voltage. Stress can be reduced, and polarization degradation due to repeated fatigue when a continuous voltage is applied can be significantly reduced.
[0018]
The ferroelectric thin film element of the present invention is characterized in that an insulating film made of SiO 2 is formed between the base substrate and the lower electrode layer. In such a ferroelectric thin film element, the insulating film made of SiO 2 can be used as a protective film for an integrated circuit such as a switching transistor formed on a Si single crystal substrate.
[0019]
Furthermore, the ferroelectric thin film element of the present invention is characterized in that the base substrate is any one of Si single crystal, sapphire single crystal, MgO, and SrTiO 3 . Such a ferroelectric thin film element can function as a ferroelectric memory by applying a single crystal of Si or a single crystal of sapphire, MgO, or SrTiO 3, and can be used as a BAW filter using a ferroelectric thin film. A SAW resonator or a SAW filter can be manufactured.
[0020]
The method for producing a ferroelectric thin-film element of the present invention is a method for producing a ferroelectric thin-film element in which a lower electrode layer, a crystal nucleus layer composed of an oxide, a ferroelectric thin film layer, and an upper electrode layer are sequentially laminated on a base substrate. A lower electrode layer and a crystal nucleus layer are sequentially formed on a base substrate, and then an amorphous ferroelectric thin film layer is formed on the crystal nucleus layer, containing oxygen at a pressure of 1.4 to 180 MPa. After performing isotropic pressure annealing (HIP) treatment in a temperature range of 400 to 600 ° C. in an inert gas to crystallize the ferroelectric thin film layer, an upper electrode layer is formed on the ferroelectric thin film layer. It is characterized by forming.
[0021]
In the method of manufacturing a ferroelectric thin film element of the present invention, when the amorphous ferroelectric thin film layer is crystallized, it grows along the crystal lattice of the crystal nucleus layer made of oxide, so that the orientation becomes high. Furthermore, since the sintering is performed at a low temperature by the HIP process, fine and highly uniform particles can be obtained, the unevenness is reduced, the surface flatness is increased, and the ferroelectric thin film element having high reproducibility during manufacturing is manufactured. Obtainable.
[0022]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is a schematic cross-sectional view of a ferroelectric thin film element of the present invention. Reference numeral 1 denotes a base substrate, 2 denotes a lower electrode layer, 3 denotes a crystal nucleus layer made of oxide, 4 denotes a ferroelectric thin film layer, 4a denotes crystal grains constituting the ferroelectric thin film layer 4, 5 denotes an upper electrode layer, Reference numeral 6 denotes an insulating film formed between the base substrate 1 and the lower electrode 2.
[0023]
The base substrate 1 is made of a single crystal of Si, a single crystal of sapphire, MgO, or SrTiO 3 , and the lower electrode 2 is made of a single crystal of Si because it is difficult for lattice distortion to remain in the interface layer and reliability in continuous operation is improved. Is desirably formed on the (110) plane.
[0024]
The lower electrode layer 2 is formed by depositing a noble metal such as Pt, Ir, and Pd by a sputtering method or an evaporation method. Further, on the upper surface of the lower electrode layer 2, a crystal nucleation layer 3 of an oxide having a perovskite structure such as PbTiO 3 , LiTaO 3 , LiNbO 3 or a bismuth layer structure such as SrBi 2 Ta 2 O 9 is formed by a high-temperature sputtering method or the like. Is formed. A ferroelectric thin film layer 4 is formed on the upper surface of the crystal nucleus layer 3 made of an oxide by a sputtering method, a sol-gel method, or the like. The ferroelectric thin film layer 4 has a crystal orientation ratio of 60% or more when not polarized. Have been. It is particularly desirable that the orientation ratio is 70% or more.
[0025]
The ferroelectric thin film layer 4 is composed of fine crystal grains 4a of 0.01 to 0.1 μm. The electrode layers 2 and 5 have a thickness of 100 to 300 nm, the ferroelectric thin film layer 4 has a thickness of 50 to 400 nm, and the insulating film 6 has a thickness of 50 to 500 nm.
[0026]
A method for producing the ferroelectric thin film element of the present invention will be described. First, an insulating film 6 is formed on a base substrate 1 of Si single crystal or the like by a sputtering method or an evaporation method, and a lower electrode layer 2 is formed on the insulating film 6 by a sputtering method or an evaporation method. A crystal nucleus layer 3 is formed on the crystal nucleus 2 by a high temperature sputtering method or the like, and a ferroelectric thin film layer 4 is formed on the crystal nucleus layer 3 in an amorphous state by a sputtering method or the like so as to have a desired composition. .
[0027]
Thereafter, the ferroelectric thin film layer 4 is formed in an atmosphere of, for example, an inert gas containing about 1 to 20% oxygen, such as Ar gas or N 2 gas, at a pressure of 1.4 to 180 MPa. The isotropic pressure annealing (HIP) treatment is performed in the temperature range of 400 to 600 ° C. while the isotropic pressure is applied.
[0028]
As a result, the amorphous ferroelectric thin film layer is crystallized, but grows along the crystal lattice of the crystal nucleus layer 3, so that an oriented film is formed. Here, since the ferroelectric thin film layer 4 has a large polarization moment Pr and needs to invert the polarization at a low voltage, a material having a low coercive electric field Ec, for example, Pb (Zr, Ti) O 3 is used as a main component. And a bismuth layered structure containing SrBi 2 Ta 2 O 9 or the like as a main component.
[0029]
In addition, the reason why the pressing force was set in the range of 1.4 to 180 MPa under the condition of isotropic pressure annealing (HIP) is that when the pressure is smaller than 1.4 MPa, the crystal orientation does not progress and the orientation ratio α is increased. This is because it does not exceed 60%. When a pressure higher than 180 MPa is further applied, an amorphous layer is again formed at the interface between the ferroelectric thin film once crystallized and the crystal nucleus layer formed of oxide as a crystal nucleus, and the crystal orientation This is because, as well as the area of loss of function as a ferroelectric substance becomes large, the application to a memory or the like becomes impossible. It is particularly desirable that the applied pressure is 1.7 to 20 MPa.
[0030]
The reason why the annealing temperature is set to 400 to 600 ° C. is that when the temperature is lower than 400 ° C., crystallization can be achieved, but a dense thin film cannot be obtained, and when the temperature is higher than 600 ° C., crystal grains become coarse. It is. In particular, the temperature is desirably 450 to 520 ° C.
[0031]
Thereafter, an upper electrode layer 5 is formed on the upper surface of the ferroelectric thin film layer 4 by sputtering or vapor deposition, and a part of the electrode is removed by etching or the like to form a wiring pattern, thereby giving a function as a memory. It is.
[0032]
According to such a method of manufacturing a ferroelectric thin film element, crystallization can be performed at a low temperature due to the HIP treatment, whereby fine particles and uniform and dense crystals can be obtained, and the surface roughness Rms of the ferroelectric thin film 4 can be reduced to about 10%. The surface irregularities can be extremely reduced to less than nm, and a ferroelectric thin film having high surface flatness can be obtained. For this reason, it is possible to miniaturize the wiring pattern formed on the ferroelectric thin film 4 and to achieve high integration.
[0033]
In the ferroelectric thin film element configured as described above, the crystal is oriented with a high degree of orientation in the C-axis direction of the ferroelectric thin film in a non-polarized state. Polarization degradation can be significantly reduced. Furthermore, since the ferroelectric thin film layer is formed densely, voids are not continuously present, so that a ferroelectric thin film element having improved insulation and improved reliability can be obtained. Furthermore, since the low-temperature and isotropic pressure annealing treatment enables high crystallinity to be obtained in the form of fine particles, a stable ferroelectric thin-film element having high repetition reproducibility at the time of production and suppressing variations among substrates is obtained. be able to.
[0034]
In a ferroelectric memory using a ferroelectric thin film element, a circuit such as a transistor is integrated on a base substrate made of Si single crystal, an insulating film made of SiO 2 is formed thereon, and then a lower electrode layer, It is manufactured by sequentially laminating a crystal nucleus layer made of an oxide, a ferroelectric thin film layer, and an upper electrode layer.
[0035]
【Example】
On a Si (100) surface of a base substrate made of Si single crystal, an SiO 2 film is formed to a thickness of 400 nm by a sputtering method, Pt is formed to a thickness of 200 nm by a sputtering method, and PbTiO serving as a crystal nucleus is formed on the upper surface. Layer 3 was formed to a thickness of 30 nm by a high-temperature sputtering method at 500 ° C.
[0036]
After that, an amorphous thickness 270 nm of a composition of 0.384 PbZrO 3 -0.376 PbTiO 3 -0.24 Pb (Zn 1/3 Nb 2/3 ) O 3 is formed by rf magnetron sputtering using a ceramic target. A ferroelectric thin film layer made of a tetragonal crystal was formed.
[0037]
Thereafter, isotropic pressure annealing (HIP) is performed at a pressure of 1 to 180 MPa and a temperature range of 500 ° C. using an Ar-mixed inert gas containing 20% oxygen, thereby performing crystallization and porcelain. Was performed. Here, since the ferroelectric thin film layer is tetragonal, the orientation α of the (001) plane was determined.
[0038]
FIG. 2 shows the crystallinity and orientation when the treatment temperature was fixed at 500 ° C. and the pressurization condition with an Ar mixed inert gas containing 20% oxygen was changed in isotropic pressure annealing (HIP). The X-ray diffraction diagram showing the properties is described.
[0039]
From FIG. 2, (a) is an X-ray diffraction diagram when the pressing condition is 1 MPa, the orientation α is 2% and non-oriented, and (b) is the pressing condition is 1.3 MPa. FIG. 6 is an X-ray diffraction diagram at the time, where the orientation α is 51%, which is still insufficient.
[0040]
On the other hand, FIG. 2 (c) is an X-ray diffraction diagram when the pressure condition is 1.8 MPa, and the orientation α was 95%, showing a remarkably high orientation. FIG. 2D is an X-ray diffraction diagram when the pressure condition is 8.8 MPa, and the orientation α was as high as 78%. FIG. 2E is an X-ray diffraction diagram when the pressurizing condition is 17.7 MPa, and the orientation α was as high as 77%. FIG. 2 (f) is an X-ray diffraction diagram when the pressing condition is 176.5 MPa. The orientation α is 60%, and although the orientation gradually decreases as the pressure is increased, the orientation α is relatively high. Showed sex.
[0041]
The orientation α was 85% when pressed at a pressure of 1.4 MPa other than that shown in FIG. 2, and the orientation α was 60% when pressed at a pressure of 180 MPa.
[0042]
FIG. 2G shows an X-ray diffraction diagram before isotropic pressure annealing (HIP). From FIG. 2 (g), it can be seen that the crystallinity is not confirmed before the isotropic pressure annealing (HIP).
[0043]
When annealing was performed at a pressure of 1.8 MPa and a temperature of 400 ° C., the orientation α was 93%, and when annealing was performed at 600 ° C., the orientation α was 98%.
[0044]
Further, when the pressure condition of the isotropic pressure annealing (HIP) is increased to be higher than 17.7 MPa, the orientation of the crystal layer containing Pb (Zr, Ti) O 3 as a main component is maintained in a high state. However, the X-ray intensity of the perovskite crystal phase decreases. This is considered to be due to the fact that the amorphous layer was formed again at the interface between the PbTiO 3 formed as a crystal nucleus and the ferroelectric thin film layer by cross-sectional observation with a transmission electron microscope and electron beam diffraction, and residual stress. Here, the thickness generated as amorphous was about 10 nm at 176.5 MPa when observed by a transmission electron microscope.
[0045]
In FIG. 2, Pero indicates the peak of perovskite, Pt indicates the peak of the platinum electrode, and the numbers in parentheses added to Pero and Pt indicate the plane index of the crystal.
[0046]
FIG. 3 (a) shows the polarization when the treatment temperature was fixed at 500 ° C. and the pressurizing condition of the Ar mixed inert gas containing 20% oxygen was changed in the isotropic press annealing (HIP). The relationship between the moment P and the electric field E is shown. FIG. 3A shows a PE hysteresis loop when the pressure is changed from 1.8 MPa to 176.5 MPa under a pressurized condition, and a ferroelectric loop is obtained under any of the conditions.
[0047]
On the other hand, FIG. 3 (b) shown as a comparative example is a conventional PE hysteresis loop when crystallized by annealing at 700 ° C. for 2 hours in an oxidizing atmosphere. Usually, the polarization moment Pr (the value of the polarization P at an electric field of 0) is required to be about 10 μC / cm 2 or more. However, when the isotropic pressure annealing (HIP) treatment is performed under the conditions shown in FIG. While the desired characteristics of 1414 μC / cm 2 were obtained, the atmospheric pressure firing shown in FIG. 3B shown in the comparative example was as low as about 4 μC / cm 2, which is not suitable for memory applications.
[0048]
Further, in order to perform the polarization inversion at a low voltage, it is better that the value of the coercive electric field Ec (the value of the electric field E at a polarization moment of 0) is small. However, in the embodiment shown in FIG. Despite the high value of Pr, the coercive electric field Ec is 75 to 90 kV / cm, which is sufficiently smaller than 120 kV / cm that can operate at a low voltage, and has characteristics suitable for memory applications.
[0049]
Furthermore, the conditions of isotropic pressure annealing (HIP) were set to 1.8 MPa and 500 ° C., and the treatment was performed for 1 hour in an Ar mixed inert gas containing 20% oxygen. It is a fine crystal with a thickness of 80 nm. The surface roughness Rms of the ferroelectric thin film layer is 3 nm, and it has excellent surface flatness. The fineness and adhesion of the electrode wiring formed on the upper surface of the ferroelectric thin film are greatly improved. It can be seen that it improves.
[0050]
Further, in the insulation between the upper and lower electrodes of the ferroelectric thin film element shown in the embodiment of the present invention, the leakage current at 100 kV / cm is 1 × 10 −7 A / cm or less, and sufficient insulation is maintained. I understood that. Further, when a repeated fatigue test in which a voltage was continuously applied was performed, no deterioration of polarization was observed even after 1 × 10 10 times.
[0051]
Furthermore, as a result of changing the isotropic pressure annealing (HIP) processing time from 1 minute to 3 hours, a desired ferroelectric thin film element could be obtained in any case.
[0052]
On the other hand, in the conventional case where the ferroelectric thin film was crystallized by annealing at 700 ° C. for 2 hours in an oxidizing atmosphere, the average crystal grain was 3 μm, the surface roughness Rms of the ferroelectric thin film layer was about 200 nm, and the ferroelectric thin film element was The leakage current at 100 kV / cm between the upper and lower electrodes was 3 × 10 −5 A / cm. When a repeated fatigue test in which a voltage was continuously applied was performed, polarization was deteriorated after 1 × 10 10 times.
[0053]
Similar effects could be obtained even when the base substrate was a sapphire single crystal. As described above, according to the present invention, it is possible to obtain a ferroelectric thin film element particularly suitable for a memory application and a method for manufacturing the same. Further, a BAW filter, a SAW resonator, or a SAW filter using a ferroelectric thin film can be obtained.
[0054]
【The invention's effect】
According to the ferroelectric thin-film element of the present invention, when the amorphous ferroelectric thin-film layer is crystallized, the isotropic pressure annealing (HIP) treatment is carried out, so that the crystal of the ferroelectric thin film can be unpolarized. Since the orientation ratio is increased, polarization deterioration due to repeated fatigue during continuous voltage application can be significantly reduced. Further, since the dense ferroelectric thin film layer is formed, voids are not continuously present, and a ferroelectric thin film element having improved insulation and improved reliability can be obtained. Further, it is possible to obtain a stable ferroelectric thin-film element having high repetition reproducibility at the time of manufacturing and suppressing variation between substrates.
[Brief description of the drawings]
FIG. 1 is a schematic sectional view of a ferroelectric thin film element of the present invention.
FIG. 2 is an X-ray diffraction diagram in isotropic pressure annealing.
FIG. 3 (a) shows a hysteresis loop of the polarization P and electric field E of the ferroelectric thin film of the present invention, and FIG. 3 (b) shows the polarization P and electric field E of a conventional ferroelectric thin film crystallized in an oxidizing atmosphere. FIG. 4 is a diagram showing a hysteresis loop of FIG.
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Base substrate 2 ... Lower electrode layer 3 ... Crystal nucleus layer 4 made of an oxide 4 ... Ferroelectric thin film layer 5 ... Upper electrode layer 6 ... Base substrate and lower electrode Insulation film formed between

Claims (5)

ベース基板上に下部電極層、酸化物からなる結晶核層、強誘電体薄膜層、上部電極層を順次積層してなる強誘電体薄膜素子であって、前記強誘電体薄膜層の未分極時における結晶の配向率が60%以上であることを特徴とする強誘電体薄膜素子。A ferroelectric thin-film device comprising a base electrode, a lower electrode layer, a crystal nucleus layer made of an oxide, a ferroelectric thin film layer, and an upper electrode layer, which are sequentially laminated, wherein the ferroelectric thin film layer is not polarized. 3. The ferroelectric thin film device according to claim 1, wherein the crystal orientation ratio is 60% or more. ベース基板と下部電極層との間に、SiOからなる絶縁膜が形成されていることを特徴とする請求項1記載の強誘電体薄膜素子。 2. The ferroelectric thin-film element according to claim 1, wherein an insulating film made of SiO 2 is formed between the base substrate and the lower electrode layer. ベース基板が、Si単結晶、サファイア単結晶、MgO、SrTiOのいずれかであることを特徴とする請求項1又は2記載の強誘電体薄膜素子。 3. The ferroelectric thin film element according to claim 1, wherein the base substrate is one of Si single crystal, sapphire single crystal, MgO, and SrTiO3. ベース基板上に下部電極層、酸化物からなる結晶核層、強誘電体薄膜層、上部電極層を順次積層してなる強誘電体薄膜素子の製法であって、ベース基板上に、下部電極層、結晶核層を順次形成した後、該結晶核層上にアモルファス状の強誘電体薄膜層を形成し、圧力1.4〜180MPaの酸素を含有する不活性ガス中において400〜600℃の温度範囲で等方加圧アニール(HIP)処理して、前記強誘電体薄膜層を結晶化した後、該強誘電体薄膜層上に上部電極層を形成することを特徴とする強誘電体薄膜素子の製法。A method of manufacturing a ferroelectric thin-film element in which a lower electrode layer, a crystal nucleus layer made of an oxide, a ferroelectric thin film layer, and an upper electrode layer are sequentially laminated on a base substrate, wherein the lower electrode layer is formed on the base substrate. After forming a crystal nucleus layer sequentially, an amorphous ferroelectric thin film layer is formed on the crystal nucleus layer, and a temperature of 400 to 600 ° C. in an inert gas containing oxygen at a pressure of 1.4 to 180 MPa. A ferroelectric thin-film element comprising: crystallizing the ferroelectric thin-film layer by performing isotropic pressure annealing (HIP) in a range, and then forming an upper electrode layer on the ferroelectric thin-film layer. Recipe. 請求項1乃至3のうちいずれかに記載の強誘電体薄膜素子を用いることを特徴とする強誘電体メモリー。A ferroelectric memory using the ferroelectric thin-film element according to claim 1.
JP2003149440A 2003-05-27 2003-05-27 Ferroelectric thin film device, its manufacturing method, and ferroelectric memory Pending JP2004356212A (en)

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