JP2004354179A - Test socket, its manufacturing method, and semiconductor device using this - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To reduce the cost and to improve the reliability with regard to a test socket for testing an mounted electronic component, its manufacturing method and the semiconductor device using the socket. <P>SOLUTION: The test socket for testing the semiconductor 30A is provided with vias 15 for connecting between layers; a substrate part 11 laminated with a plurality of base material layers 13 on which through holes 18 are provided at the position where the pins 34 of the semiconductor device 34 are connected; and at the same time the contact parts 12 having electrode parts 20 electrically connected with the vias 15 provided on the substrate 11 and also electrically connected with the semiconductor 30A. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a test socket, a method for manufacturing the same, and a semiconductor device using the same, and more particularly, to a test socket for mounting and testing an electronic component, a method for manufacturing the same, and a semiconductor device using the same.
[0002]
[Prior art]
Conventionally, various test methods have been proposed as test methods for semiconductor devices. When an electrical operation test of a semiconductor device is performed, the reliability of the test is required to be high and the cost is low.
[0003]
2. Description of the Related Art As a conventional apparatus for testing a semiconductor device, for example, there is an apparatus using a test socket (hereinafter, referred to as a test socket). The test socket is configured to test the electrical operation of the semiconductor device using a probe (test needle). In this test method, a plurality of probes are arranged on a test board so as to correspond to a plurality of connection terminals (for example, solder balls) formed on the lower surface of the semiconductor device, and the tips of the probes are brought into contact with the connection terminals. The test is performed.
[0004]
However, in this test socket, it is necessary to arrange a plurality of probes in the socket housing (made of resin) so as to have the same arrangement as the plurality of connection terminals of the semiconductor device, and the configuration is complicated and the cost is high. Was something.
[0005]
Therefore, for example, as shown in Patent Document 1, there has been proposed a test socket that can reliably test a semiconductor device with a simple configuration. The test socket disclosed in Patent Document 1 is composed of a matrix frame provided with a number of openings, and a metal sheet fixed in the openings via an insulating cured resin. By forming a slit, a first contact that contacts a terminal of the semiconductor device and a second contact that contacts an electrode formed on the measurement substrate are formed.
[0006]
[Patent Document 1]
JP 2003-43102 A
[0007]
[Problems to be solved by the invention]
However, in the test socket disclosed in Patent Literature 1, it is necessary to dispose openings in the metal matrix frame having high rigidity in a number and a position corresponding to the terminals of the semiconductor device. In addition, it is necessary to fix a thin metal plate to each of the openings via an insulating cured resin, and it is necessary to provide a slit in each of the metal plates to form first and second contacts.
[0008]
For this reason, when manufacturing a test socket, a general and inexpensive manufacturing method such as a multilayer wiring board technique cannot be used, and although the manufacturing process can be simplified and the cost can be reduced as compared with the test socket. However, sufficient simplification of the manufacturing process and cost reduction have not yet been realized. Further, the configuration of the test socket disclosed in Patent Document 1 has a problem that when a terminal position is changed in a semiconductor device to be tested, it cannot be easily prepared.
[0009]
Further, since the first and second contacts provided in the test socket disclosed in Patent Document 1 are formed by forming slits in a metal plate and bending the slits, the terminals of the semiconductor device have bumps (balls). ), A good connection can be made, but if the terminals of the semiconductor device are pin-shaped, there is a problem that a good connection cannot be made.
[0010]
The present invention has been made in view of the above points, and has as its object to provide an inexpensive and highly reliable test socket, a method of manufacturing the same, and a semiconductor device using the same.
[0011]
[Means for Solving the Problems]
In order to solve the above problems, the present invention is characterized by taking the following means.
[0012]
The invention according to claim 1 is
In a test socket in which an electronic device is mounted and a test is performed on the electronic device,
A substrate portion formed by laminating a plurality of base material layers in which vias for performing interlayer connection are formed and through holes are formed in positions where terminals of the electronic device are connected,
A contact member provided on the substrate portion and electrically connected to the via, and having an electrode portion formed to be electrically connected to a terminal of the electronic component. is there.
[0013]
According to the above invention, the substrate layer has a structure in which vias and through holes for performing interlayer connection are formed, and the substrate portion has a structure in which the substrate layers are laminated. It can be manufactured by utilizing the manufacturing technology described above. Further, since the contact member has a simple configuration in which the electrode portion is formed only at a position electrically connected to the terminal of the electronic component, the cost of the test socket can be reduced. Further, since the via formation position, the through hole formation position, and the electrode formation position can be easily changed, even if the terminal position of the electronic device to be tested is changed, it can be easily and quickly performed. This can be accommodated.
[0014]
The invention according to claim 2 is
The test socket according to claim 1,
An uneven portion is formed in a portion of the electrode portion connected to the terminal portion.
[0015]
According to the above invention, unevenness is formed at a portion of the electrode portion connected to the terminal portion, so that the contact area between the electrode portion and the terminal portion can be increased, and thus the electrical connection between the electrode portion and the terminal portion is ensured. Can be connected.
[0016]
The invention according to claim 3 is:
The test socket according to claim 1 or 2,
A slit is formed in the electrode part.
[0017]
According to the above invention, the slit is formed in the electrode portion, so that the electrode portion can be displaced when the terminal portion is connected. Thus, since the electrode portion is displaced along the shape of the terminal portion, the contact area between the electrode portion and the terminal portion increases, and the electrode portion and the terminal portion can be reliably electrically connected.
[0018]
The invention according to claim 4 is
The test socket according to any one of claims 1 to 3,
The contact member is made of a material having a spring property.
[0019]
According to the above invention, since the material having the spring property is selected as the material of the contact member, the electrode portion is elastically deformed along the shape of the terminal portion when the terminal portion is connected. The contact area increases, and the electrode portion and the terminal portion can be reliably electrically connected.
[0020]
The invention according to claim 5 is
The test socket according to any one of claims 1 to 4,
The plurality of base material layers to be laminated have the same configuration.
[0021]
According to the above invention, since a plurality of base material layers to be stacked have the same structure, the manufacture of the base material layers becomes easier and an alignment process performed at the time of stacking as compared with a structure in which different types of base material layers are stacked. Can be facilitated.
[0022]
The invention according to claim 6 is:
In a method of manufacturing a test socket for performing a test on a mounted electronic device,
By forming a via and a through hole in the resin body formed on the support plate, a base layer forming step of forming a base layer on the support plate,
A substrate portion forming step of forming a substrate portion in which a plurality of substrate layers are laminated by laminating the substrate layer so as to be laminated, and then removing the support plate.
A contact member forming step of forming a contact member formed with an electrode portion electrically connected to a terminal of the electronic component from a conductive metal plate,
Arranging the contact member on the substrate portion so as to be electrically connected to the via.
[0023]
According to the invention, the base material layer formed on the support plate in the base material layer forming step is bonded so that the base material layer is laminated in the substrate part forming step, and then the support plate is removed. Since a substrate portion in which a plurality of material layers are stacked is formed, the base material layers can be stacked with high accuracy. Until the respective base layers are stacked, the base layers can be handled while being supported by the support plate, so that the stacking process can be easily performed.
[0024]
The invention according to claim 7 is
The method for manufacturing a test socket according to claim 6,
In the contact member forming step, a portion of the electrode portion connected to a terminal of the electronic component is subjected to a surface roughening process.
[0025]
According to the above invention, since the roughening process is performed, the unevenness is formed in the portion of the electrode portion connected to the terminal portion, so that the electrode portion having good electrical connection with the terminal portion can be easily formed. can do.
[0026]
The invention according to claim 8 is
The method for manufacturing a test socket according to claim 6 or 7,
In the contact member forming step, a central hole formed in a central portion of the electrode portion and a slit formed in the electrode portion are simultaneously formed.
[0027]
According to the invention, in the contact member forming step, the central hole formed in the central portion of the electrode portion and the slit formed in the terminal portion are formed simultaneously, so that the central hole and the slit are separately formed. The manufacturing efficiency can be improved as compared with the above.
[0028]
The semiconductor device according to the ninth aspect of the present invention is
A test socket according to claim 1 as an interposer,
A terminal of a semiconductor element is joined to the electrode portion, and an external connection terminal is provided in the via exposed on a side of the substrate portion opposite to a side where the contact member is provided.
[0029]
According to the above invention, since the test socket used for testing the semiconductor element can be used as an interposer as it is, there is no need to prepare an interposer separately from the test socket, realizing a semiconductor device that is inexpensive and has high component efficiency. can do.
[0030]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, embodiments of the present invention will be described with reference to the drawings.
[0031]
FIGS. 1 to 3 are views for explaining a test socket 10 according to an embodiment of the present invention. FIG. 1 is a sectional view of a test socket 10, and FIGS. 2 and 3 show a state where an electronic device is mounted. 2 shows an example in which a PGA (Pin Grid Array) type semiconductor device 30A is mounted as an electronic device, and FIG. 3 shows an example in which a BGA (Ball Grid Array) type semiconductor device 30A is mounted as an electronic device. I have.
[0032]
The test socket 10 is generally constituted by a board portion 11 and a contact portion 12. The substrate portion 11 has a structure in which a plurality of (two in this embodiment) base material layers 13 are stacked. The base layers 13 to be stacked have the same configuration, and a pair of base layers 13 adjacent to each other are stacked in the opposite direction.
[0033]
As described above, by making the plurality of base layers 13 to be stacked to have the same configuration, the manufacturing of the base layers 13 is facilitated and alignment performed at the time of stacking is made easier than a configuration in which different types of base layers are stacked. Processing can be facilitated. The base layer 13 has a configuration in which a via 15, a wiring pattern 16, a connection pad 17, and a through hole 18 are formed in the resin body 14 using the resin body 14 as a material.
[0034]
The resin body 14 is formed of an insulating resin such as polyimide or epoxy. The via 15 has a configuration in which a conductive metal (copper in this embodiment) is provided in a via hole 26 (see FIG. 4C) formed to penetrate the resin body 14.
[0035]
One end of the via 15 is connected to the wiring pattern 16, and a pad 15 a is formed integrally with the via 15 at the other end (see FIG. 4D). Further, a connection pad 17 is connected to the wiring pattern 16. The wiring patterns 16 and the connection pads 17 are also formed of copper in this embodiment.
[0036]
The through hole 18 is formed to penetrate the resin body 14 up and down. The positions where the through holes 18 are formed are set to correspond to the positions where the external connection terminals (pins 34, solder balls 35) provided on the semiconductor devices 30A and 30B mounted on the test socket 10 are formed.
[0037]
The through hole 18 formed in the lower substrate layer 13 of the pair of laminated base layers 13 and the through hole 18 formed in the upper substrate layer 13 substantially coincide with each other. It is configured as follows. Therefore, even in the substrate section 11 in which the plurality of base layers 13 are stacked, the respective through holes 18 are in a communicating state.
[0038]
Next, the contact portion 12 will be described with reference to FIGS. 7 and 8 in addition to FIGS. 7 is an enlarged plan view showing the vicinity of the electrode portion 20 of the contact portion 12, and FIG. 8 is an enlarged side view showing the vicinity of the electrode portion 20 of the contact portion 12.
[0039]
The contact portion 12 is formed by pressing a conductive metal plate into a predetermined shape by press molding. As the material of the contact portion 12, a material having excellent conductivity and having spring properties is selected (for example, phosphor bronze or the like). The contact section 12 is fixed to the substrate section 11 by being joined to the connection pad 17. Thereby, the contact portion 12 is electrically connected to the via 15 via the connection pad 17 and the wiring pattern 16.
[0040]
The contact portion 12 has a configuration in which a central hole 19, an electrode portion 20, an uneven portion 21, and a slit 23 are formed. The center hole 19 is formed so as to coincide with the formation position of the external connection terminals (pins 34, solder balls 35) provided on the semiconductor devices 30A, 30B when the semiconductor devices 30A, 30B are mounted on the test socket 10. (See FIGS. 2 and 3).
[0041]
The diameter of the central hole 19 is set smaller than the diameter of the pin 34 provided in the semiconductor device 30A. The diameter of the center hole 19 is set smaller than the diameter of the solder ball 35 provided in the semiconductor device 30B.
[0042]
The outer peripheral position of the central hole 19 is an electrode portion 20. When the semiconductor devices 30A and 30B are mounted in the test socket 10, the electrode portions 20 are connected to the pins 34 and the solder balls 35 of the semiconductor devices 30A and 30B, and are electrically connected.
[0043]
As shown in FIG. 7A and FIG. 8A, the electrode portion 20 is formed with an uneven portion 21 and a slit 23. In the present embodiment, as shown in FIG. 8A, the uneven portion 21 forms an uneven portion by forming a convex portion on the electrode portion 20. As shown in FIG. It is formed so that it may become concentric.
[0044]
By forming the uneven portion 21 on the electrode portion 20 in this manner, when the semiconductor devices 30A and 30B are mounted on the test socket 10, contact between the external connection terminals (pins 34, solder balls 35) and the electrode portion 20 is achieved. The area can be increased. Therefore, the electrode portion 20 and the external connection terminals (pins 34, solder balls 35) can be reliably electrically connected, and the connection reliability of the test socket 10 can be improved.
[0045]
On the other hand, a plurality of slits 23 are formed radially around the center hole 19 at the position where the electrode portion 20 is formed. As shown in FIG. 7A, in this embodiment, four slits 23 are formed at substantially equal intervals.
[0046]
By forming the slits 23 in the electrode portion 20 in this manner, when the pin 34 or the solder ball 35 is connected, the electrode portion 20 is displaced with the connection. As described above, the contact portion 12 is formed of a material having a spring property. However, in the configuration in which the center hole 19 is simply formed, the contact portion 12 easily conforms to the shape of the pin 34 or the solder ball 35 at the time of connection. There is no deformation.
[0047]
However, by forming the slit 23, the electrode portion 20 having the spring property is surely displaced along the shape of the pin 34 and the solder ball 35. Therefore, the contact area between the pins 34 and the solder balls 35 and the electrode portions 20 can be increased, and the electrode portions 20 and the pins 34 and the electrode portions 20 and the solder balls 35 can be reliably electrically connected. .
[0048]
The shape of the uneven portion 21 formed on the electrode portion 20 is not limited to a configuration in which a plurality of concavities and convexities are formed concentrically with respect to the central hole 19 shown in FIG. 7A. As shown in the example, one annular uneven portion 21 having a predetermined width may be formed on the outer periphery of the central hole 19. Further, the shape of the concave-convex portion 21 in a side view is not limited to the triangular shape shown in FIG. 8A, and may be a trapezoidal shape as shown in an example in FIG. 8B.
[0049]
FIG. 2 shows a state where the semiconductor device 30A is mounted on the test socket 10 having the above configuration. In the semiconductor device 30A, a semiconductor element 31 is flip-chip bonded to an upper surface of an interposer 32 by a bump 33. Since the semiconductor device 30A is a PGA type semiconductor device, pins 34 serving as external connection terminals are provided on the lower surface of the interposer 32.
[0050]
When the semiconductor device 30 </ b> A is mounted in the test socket 10, the pins 34 are located in the through holes 18 of the substrate 11 through the electrode portions 20. Specifically, when the semiconductor device 30 </ b> A is mounted on the test socket 10, the pin 34 first contacts the position where the central hole 19 of the electrode portion 20 is formed.
[0051]
Since the diameter of the central hole 19 is smaller than the diameter of the pin 34, the electrode portion 20 having the slit 23 is deformed along the shape of the pin 34 when the pin 34 presses the electrode portion 20, and the inside of the through hole 18 of the pin 34 Allow entry into Further, with this approach, the uneven portion 21 formed on the electrode portion 20 comes into sliding contact with the outer periphery of the pin 34.
[0052]
As a result, as shown in FIG. 2, the contact portion 12 and the pin 34 are electrically connected. At this time, as described above, the contact portion 12 has a spring property, the electrode portion 20 is formed with the slit 23, and the electrode portion 20 is formed with the uneven portion 21. The part 12 and the pin 34 are securely electrically connected.
[0053]
The contact 12 is electrically connected to an external connection terminal 22 provided on the back surface of the substrate unit 11 via a via 15 formed in each base material layer 13 or the like. The test socket 10 is connected to the test board by the external connection terminals 20. In this embodiment, an example in which solder balls are used as the external connection terminals 20 is shown.
[0054]
In the case of the PGA type semiconductor device 30A, the pins 34 are inserted deep into the substrate portion 11. However, in the test socket 10 according to the present embodiment, the thickness of the substrate portion 11 (that is, the depth of the through-hole 18 into which the pin 34 is inserted) can be easily increased or decreased by increasing or decreasing the number of stacked base layers 13. Can be adjusted. Therefore, the test socket 10 corresponding to the semiconductor device 30A having the pins 34 having different lengths can be formed in a short time and at low cost.
[0055]
On the other hand, FIG. 3 shows a state where the BGA type semiconductor device 30B is mounted on the test socket 10. Even when the semiconductor device 30B uses the solder ball 35 as an external connection terminal, the operation of mounting the semiconductor device 30A on the test socket 10 is substantially the same as the operation of mounting the semiconductor device 30A. That is,
When the semiconductor device 30 </ b> A is mounted on the test socket 10, the electrode portions 20 having the slits 23 are deformed along the shape of the solder balls 35 when the solder balls 35 press the electrode portions 20. Further, with this deformation, the uneven portion 21 formed on the electrode portion 20 comes into sliding contact with the outer periphery of the solder ball 35. At this time, the contact portion 12 has a spring property, the electrode portion 20 has a slit 23, and the electrode portion 20 has an uneven portion 21. The ball 35 is securely electrically connected. The contact section 12 is connected to an external connection terminal 22 via a via 15 or the like, and the external connection terminal 22 is connected to a test board.
[0056]
As described above, the test socket 10 according to the present embodiment has a configuration in which the base layer 13 is formed with the via 15 and the like and the through-hole 18 for performing interlayer connection, and the substrate section 11 is formed of the base material. This is a structure in which the layers 13 are stacked. For this reason, the board part 11 can be manufactured using the manufacturing technology of the multilayer wiring board.
[0057]
Further, the contact portion 12 provided on the substrate portion 11 also has a simple configuration in which the electrode portion 20 having the uneven portion 21 and the slit 23 is formed. Therefore, the test socket 10 can be manufactured with high productivity at low cost.
[0058]
Furthermore, the formation positions of the vias 15 and the like, the formation positions of the through holes 18, and the formation positions of the electrode portions 20 can be easily changed. Therefore, even if the external connection terminals (pins 34, solder balls 35) of the electronic devices (semiconductor devices 30A, 30B) to be tested are changed, it is possible to easily and quickly respond to the change.
[0059]
In the above-described embodiment, after the semiconductor devices 30A and 30B are mounted on the test socket 10, the test socket 10 is arranged on the test board using the external connection terminals 22. However, the configuration may be such that the test socket 10 is previously arranged on the test board using the external connection terminal 22, and the conductor devices 30A and 30B are mounted on the test socket 10 arranged on the test board. Good.
[0060]
Next, a method of manufacturing the test socket 10 having the above configuration will be described. 4 to 6 show one embodiment of a method for manufacturing the test socket 10. FIG.
[0061]
To manufacture the test socket 10, first, a flat support plate 25 made of a conductive metal is facilitated. In this embodiment, copper is selected as the material of the support plate 25. On one surface of the support plate 25, a wiring pattern 16 is formed in a predetermined pattern as shown in FIG.
[0062]
The formation position of the wiring pattern 16 is selected as the formation position of the via 15. In addition, the wiring pattern 16 is formed by forming a plating resist pattern on the support plate 25 so that the wiring forming portion of the support plate 25 is exposed, and then supplying power from the support plate 25 to perform electrolytic copper plating. It is formed by removing the pattern.
[0063]
Subsequently, the support plate 25 on which the wiring pattern 16 is formed is mounted on a mold, and a process of forming the resin body 14 is performed. This resin body 14 is an insulating resin such as polyimide or epoxy as described above. The resin body 14 is formed on the surface of the support plate 25 on which the wiring pattern 16 is formed. FIG. 4B shows a state where the resin body 14 is formed on the support plate 25.
[0064]
Subsequently, a process of forming a via hole 26 is performed on the resin body 14. In this embodiment, the via holes 26 are formed by using a laser processing method. At this time, the wiring pattern 16 formed in advance on the support plate 25 functions as a so-called laser stopper.
[0065]
That is, since the processing speed of processing the metal wiring pattern 16 by laser is lower than the processing speed of processing the resin body 14 as a resin by laser, the processing speed is applied to the resin body 14 using this processing speed. The hole processing of the via hole 26 is performed. Thereby, the via hole 26 penetrating the resin body 14 can be reliably formed. FIG. 4C shows a state in which the via hole 26 is formed.
[0066]
Subsequently, the via 15 is formed in the via hole 26. In this embodiment, an electrolytic plating method is used for forming the via 15. That is, the support plate 25 in which the resin body 14 in which the via hole 26 is formed is formed is immersed in a plating tank, and electrolytic plating is performed using the support plate 25 as an electrode. As a result, the via 15 is formed in the via hole 26. In the present embodiment, copper is selected as the material of the via 15, and the via 15 is formed by electrolytic copper plating.
[0067]
In this plating process, in this embodiment, a plating process is performed after a mask having an opening larger than the opening area of the via hole 26 is provided above the resin body 14. As a result, a pad portion 15 a that protrudes from the surface of the resin body 14 and is larger than the opening area of the via hole 26 is formed simultaneously with the via 15 above the via 15. FIG. 4D shows a state in which the via 15 in which the pad portion 15 a is integrally formed is formed in the resin body 14.
[0068]
Subsequently, a process of forming a through hole 18 in the resin body 14 is performed. The formation position of the through hole 18 is set to the formation position of the external connection terminals (pins 34, solder balls 35) of the semiconductor devices 30A and 30B mounted as described above. This through hole 18 is formed by a laser processing method in this embodiment.
[0069]
However, since the diameter of the through hole 18 is larger than that of the wiring pattern 16, the through hole 18 may be formed by using an etching method. Alternatively, a method in which a photosensitive resin is used in advance for the resin body 14 and the through-hole 18 is formed by using photolithography technology may be used.
[0070]
FIG. 4E shows a state in which the through-hole 18 is formed in the resin body 14. By forming the through holes 18 in the resin body 14 as described above, the base layer 13 is formed on the support plate 25 (base layer forming step).
[0071]
Subsequently, two support plates 25 on which the base material layers 13 manufactured by the above-described processing are formed are prepared, and are arranged such that the base material layers 13 face each other as shown in FIG. I do. Subsequently, the pair of base layers 13 are joined to fix the pad portions 15a to each other.
[0072]
The pad portions 15a may be fixed to each other by applying ultrasonic plating to the pad portions 15a after applying gold plating thereto, or may be fixed via a bonding material such as solder. As a result, as shown in FIG. 5A, the vias 15 formed on the pair of upper and lower base layers 13 are electrically connected, and the pair of base layers 13 are stacked. It becomes.
[0073]
When the pair of base layers 13 are thus laminated, the support plate 25 is subsequently subjected to a removal process. In the removal process of the support plate 25, a resist is formed on the support plate 25, and then exposure, development, and baking processes are performed so that the resist remains on the portion to be the connection pad 17. Then, using the resist thus formed as a mask, an etching process is performed on the support plate 25.
[0074]
As a result, unnecessary portions of the support plate 25 are removed, and the connection pads 17 are formed on the resin body 14 as shown in FIG. The connection pad 17 is configured to be electrically connected to the via 15 via the wiring pattern 16. By performing the above processing, the substrate unit 11 in which the plurality of base layers 13 are stacked is formed (substrate unit forming step).
[0075]
The contact portion 12 manufactured in a separate process is provided on the substrate portion 11 formed as described above. FIG. 6 shows a process of forming the contact portion 12.
[0076]
To form the contact portion 12, first, a flat conductive metal plate 27 as shown in FIG. 6A is prepared. As the material of the conductive metal plate 27, a material having excellent conductivity and having spring properties is selected (for example, phosphor bronze or the like).
[0077]
Pressing is performed on the conductive metal plate 27, and unnecessary portions are cut, and a central hole 19 and a slit 23 are simultaneously formed at the position where the electrode portion 20 is formed, as shown in FIG. Is done. Subsequently, as shown in FIG. 6 (C), a roughening process is performed on the formation position of the electrode portion 20 to form the uneven portion 21, thereby forming the contact portion 12 (contact member forming step). .
[0078]
As the surface roughening treatment, for example, a method of forming the uneven portion 21 by forming a convex portion by plating, a method of forming the uneven portion 21 by forming a concave portion by etching, and forming the uneven portion 21 by sandblasting Various methods are conceivable, such as a method for performing the operation.
[0079]
In the present embodiment, when the contact portion 12 is formed, the central hole 19 and the slit 23 are formed at the same time, so that the manufacturing efficiency can be increased as compared with a method in which the central hole 19 and the slit 23 are formed separately. In addition, since a roughening process is performed at a predetermined position of the electrode portion 20, that is, a position where the pins 34 and the solder balls 35 of the semiconductor devices 30A and 30B are connected, electrical connection between the pins 34 and the solder balls 35 is performed. The electrode portion 20 having a good quality can be easily formed.
[0080]
Here, the description returns to FIG. 5C again. The contact part 12 formed as described above is provided on the substrate part 11. Specifically, the contact portion 12 is electrically connected to the via 15 formed in the substrate portion 11 by being connected to the connection pad 17.
[0081]
As a result, as shown in FIG. 5D, the test socket 10 including the board portion 11 and the contact portion 12 is completed (arranging step). The contact portion 12 may be bonded to the connection pad 17 by applying gold plating to the connection pad 17 and then using ultrasonic welding, or by using soldering.
[0082]
In the above-described manufacturing method, the base material layer 13 formed on the support plate 25 in the base material layer formation step is laminated by bonding in the substrate part formation step, and then the support plate 25 is removed to remove the substrate part 11. Is formed, the base material layer 13 can be accurately laminated. Until the respective base layers 13 are stacked, the base layers 13 can be handled while being supported by the support plate 25. Therefore, the handling is easy, and the stacking process can be performed efficiently and easily.
[0083]
FIG. 9 shows an example in which a test socket 10 according to one embodiment of the present invention is used for testing a semiconductor element 31. In FIG. 9 and FIG. 10 used in the following description, the same components as those shown in FIGS. 1 to 8 used in the above description are denoted by the same reference numerals, and description thereof will be omitted.
[0084]
2 and 3, the semiconductor device 30A. Although an example of testing 30B has been described, it is also possible to test the semiconductor element 31 mounted on the semiconductor device with the test socket 10 as shown in FIG.
[0085]
FIG. 10 shows a semiconductor device 40 using the test socket 10 as an interposer according to one embodiment of the present invention. This semiconductor device 40 is roughly composed of a substrate portion 11 and a semiconductor element 31.
[0086]
In order to manufacture the semiconductor device 40, first, the semiconductor element 31 is mounted on the test socket 10 and a test is performed on the semiconductor element 31, as described with reference to FIG. Then, when the semiconductor element 31 is determined to be defective by the test, only the semiconductor element 31 is discarded.
[0087]
On the other hand, if it is determined that the semiconductor element 31 is a non-defective product, the underfill resin 41 is disposed between the semiconductor element 31 and the substrate 11 while the semiconductor element 31 is mounted on the test socket 10. Then, the semiconductor element 31 is fixed to the test socket 10. As a result, the semiconductor element 31 is mounted on the substrate 11, and the semiconductor device 40 is completed. When the semiconductor device 40 is mounted, the external connection terminals 22 are used as mounting terminals.
[0088]
In the semiconductor device 40 having the above configuration, the test socket 10 used for testing the semiconductor element 31 is used as it is as an interposer of the semiconductor device 40. Therefore, it is not necessary to prepare an interposer separately from the test socket 10, and the semiconductor device 40 which is inexpensive and has high component efficiency can be realized.
[0089]
【The invention's effect】
As described above, according to the present invention, the following various effects can be realized.
[0090]
According to the first aspect of the present invention, the cost of the test socket can be reduced, and even if the terminal position of the electronic device to be tested is changed, it can be easily and promptly dealt with.
[0091]
According to the second to fourth aspects of the present invention, the electrode portion and the terminal portion can be reliably electrically connected.
[0092]
According to the fifth aspect of the present invention, since a plurality of base material layers to be stacked have the same configuration, the manufacture of the base material layer is facilitated as compared with a configuration in which different types of base material layers are stacked. Alignment processing performed at the time of lamination can be facilitated.
[0093]
In addition, according to the invention described in claim 6, the base material layer can be accurately laminated, and the lamination process can be easily performed.
[0094]
According to the seventh aspect of the present invention, by performing the surface roughening process, unevenness is formed at a portion of the electrode portion connected to the terminal portion, so that the electrical connection with the terminal portion is improved. The electrode portion can be easily formed.
[0095]
Further, according to the invention described in claim 8, in the contact member forming step, the central hole formed in the central portion of the electrode portion and the slit formed in the terminal portion are simultaneously formed, so that the central hole and the slit are formed. The manufacturing efficiency can be improved as compared with the method of separately forming.
[0096]
According to the ninth aspect of the present invention, it is not necessary to prepare an interposer separately from the test socket, and a semiconductor device which is inexpensive and has high component efficiency can be realized.
[Brief description of the drawings]
FIG. 1 is a sectional view of a test socket according to an embodiment of the present invention.
FIG. 2 is a view showing a state in which a PGA type semiconductor device is mounted on a test socket according to one embodiment of the present invention.
FIG. 3 is a view showing a state in which a GGA type semiconductor device is mounted on a test socket according to an embodiment of the present invention.
FIG. 4 is a view for explaining a method of manufacturing a test socket according to an embodiment of the present invention (part 1).
FIG. 5 is a view for explaining the method of manufacturing the test socket according to one embodiment of the present invention (part 2).
FIG. 6 is a view for explaining a method of manufacturing a contact portion which is a component of the test socket according to one embodiment of the present invention.
FIG. 7 is an enlarged plan view showing the vicinity of an electrode portion of a contact portion.
FIG. 8 is an enlarged side view showing the vicinity of an electrode portion of a contact portion.
FIG. 9 is a diagram showing an example in which a test socket according to one embodiment of the present invention is used for testing a semiconductor device.
FIG. 10 is a cross-sectional view showing a semiconductor device using a test socket as an interposer according to one embodiment of the present invention.
[Explanation of symbols]
10. Test socket
11 Substrate
12 Contact part
13 Base material layer
14 Resin body
15 Vias
16 Wiring pattern
17 Connection pad
18 Through hole
20 Electrode section
21 Uneven part
22 External connection terminal
23 slit
25 Support plate
26 Via hole
27 Conductive metal plate
30A, 30B, 40 Semiconductor device
31 Semiconductor element
32 Interposer
33 Bump
34 pin
35 Solder Ball
41 Underfill resin

Claims (9)

In a test socket in which an electronic device is mounted and a test is performed on the electronic device,
A substrate portion formed by laminating a plurality of base material layers in which vias for performing interlayer connection are formed and through holes are formed in positions where terminals of the electronic device are connected,
A contact member provided on the substrate part, electrically connected to the via, and having an electrode part formed to be electrically connected to a terminal of the electronic component. socket. The test socket according to claim 1,
A test socket, wherein irregularities are formed in a portion of the electrode portion connected to the terminal portion. The test socket according to claim 1 or 2,
A test socket, wherein a slit is formed in the electrode portion. The test socket according to any one of claims 1 to 3,
A test socket, wherein the contact member is made of a material having a spring property. The test socket according to any one of claims 1 to 4,
The test socket, wherein the plurality of base material layers to be laminated have the same configuration. In a method of manufacturing a test socket for performing a test on a mounted electronic device,
By forming a via and a through hole in the resin body formed on the support plate, a base layer forming step of forming a base layer on the support plate,
A substrate portion forming step of forming a substrate portion in which a plurality of substrate layers are laminated by laminating the substrate layer so as to be laminated, and then removing the support plate.
A contact member forming step of forming a contact member formed with an electrode portion electrically connected to a terminal of the electronic component from a conductive metal plate,
Arranging the contact member on the substrate portion so as to be electrically connected to the via. The method for manufacturing a test socket according to claim 6,
A method for manufacturing a test socket, comprising performing a surface roughening process on a portion of the electrode portion connected to a terminal portion of the electronic component in the contact member forming step. The method for manufacturing a test socket according to claim 6 or 7,
A method for manufacturing a test socket, comprising: simultaneously forming a central hole formed in a central portion of the electrode portion and a slit formed in the electrode portion in the contact member forming step. A test socket according to claim 1 as an interposer,
A terminal for a semiconductor element is joined to the electrode portion, and an external connection terminal is provided in the via exposed on the side of the substrate portion opposite to the side where the contact member is provided. Semiconductor device.

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