JP2004349677A - Thin film transistor having self-alignment ldd structure and its fabrication process - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a polysilicon thin film transistor having a self-alignment LDD structure, and to provide its fabrication process. <P>SOLUTION: At first, an effective layer is formed on a substrate, a gate insulating layer having a center area, a shield area and an extension area defined on the surface is formed on the effective layer, and a gate layer is formed on the gate insulating layer. The shield area and the extension area are exposed while covering the center area with the gate layer and the gate insulating layer and the shield area are made thicker than the extension area by etching. Subsequently, in an ion implantation process, a first doped area is formed in the effective layer covered with the shield area, and a second doped area is formed in the effective layer covered with the extension area thus fabricating a thin film transistor having a self-alignment LDD structure. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a thin film transistor, and more particularly, to a lightly doped drain (LDD) structure of a polycrystalline silicon transistor and a method of manufacturing the same.

  A thin film transistor (TFT) of a liquid crystal display (LCD) is used as a pixel switching element. There are two types, a polycrystalline silicon TFT and an amorphous silicon TFT.

  Polycrystalline silicon TFTs have a relatively high carrier transfer rate, excellent integration of driving electric circuits, and low current leakage. Therefore, the polycrystalline silicon TFT is usually used for an electric circuit having a high operation speed, for example, an SRAM (static random access memory). However, a polycrystalline silicon TFT is liable to generate leakage current in the open / closed state, causing problems such as loss of LCD charge or consumption of standby power of the SRAM. In order to solve these problems, a lightly doped drain (LDD) structure is adopted to reduce the electric field at the drain junction, so that the leakage current problem can be improved.

  1 and 2 are cross-sectional views illustrating a conventional method for manufacturing an LDD structure of a polycrystalline silicon TFT.

As shown in FIG. 1, a polycrystalline silicon layer 12 is formed on a specific area of the transparent insulating substrate 10, and a gate insulating layer 14 covers the polycrystalline silicon layer 12. First, a photoresist layer 16 is formed on the gate insulating layer 14, and a heavy ion implantation step 17 is performed using the photoresist layer 16 as a mask. An N ⁺ doped area 18 is formed in the surrounding polycrystalline silicon layer 12.

As shown in FIG. 2, after removing the photoresist layer 16, a metal material is deposited, microlithography and etching are performed to form a gate layer 20 on the gate insulating layer 14 by definition. Thereafter, the pattern of the LDD structure is defined using the gate layer 20 as a mask, so that only the undoped area of the polycrystalline silicon layer 12 covered by the gate layer 20 is masked. Next, a low ion implantation step 21 is performed using the gate layer 20 as a mask, and an N ^- doped area 22 is formed in the undoped area of the polycrystalline silicon layer 12 located around the gate layer 20. Thus, the N ^- doped area 22 has an LDD structure, the N ⁺ doped area 18 has a source / drain area, and the undoped area of the polycrystalline silicon layer 12 covered with the gate layer 20 has a channel area.

  However, since the above method requires patterning the patterned source / drain area of the photoresist layer 16 and patterning the LDD structure with the pattern of the gate layer 20, a very accurate gate layer 20 is required. The position of the LDD structure cannot be ensured except for the pattern described above. In addition, since there is a limitation of misalignment due to the exposure technique, the amount of shift of the gate layer 20 is difficult to control, and the problem due to the shift of the LDD structure position is increased by two ion implantation steps. In addition, the steps of the above method are complicated, the production rate of the product is low, it is difficult to control the width of the LDD structure, and the shrinkage rate of polycrystalline silicon TFT, the function and reliability of the electric durability are affected. Effect.

  3 to 5 are cross-sectional views showing a conventional method for manufacturing an LDD structure of a polycrystalline silicon TFT.

  First, as shown in FIG. 3, a polycrystalline silicon layer 32, a gate insulating layer 34, and a gate layer 36 are formed on a transparent insulating substrate 30 in this order. Next, using the first photoresist layer 38 as a mask, a pattern of the gate layer 36 and the gate insulating layer 34 is formed by an etching method, and the polycrystalline silicon layer 32 is exposed.

Next, as shown in FIG. 4, taking a polysilicon TFT made of a PMOS as an example, after removing the first photoresist layer 38, a low ion implantation step 39 is performed using the gate layer 36 as a mask. Thus, an N ^- doped area 40 is formed in the polysilicon layer 32 located around the gate layer 36.

Subsequently, as shown in FIG. 5, a photoresist material is deposited, lithography and etching are performed to form a second photoresist layer 42, and the second photoresist layer 42 is in contact with the surfaces of the gate layer 36 and the gate insulating layer 34. The side wall and a part of the N ^- doped area 40 around the gate layer 36 are covered. Finally, using the second photoresist layer 42 as a mask, a heavy ion implantation step 43 is performed to change the N ⁻ doped area 40 located around the second photoresist layer 42 into an N ⁺ doped area 44. Thus, the N ^- doped area 40 covered by the second photoresist layer 42 has the LDD structure, the N ⁺ doped area 44 has the source / drain area, and the polycrystalline silicon layer 32 covered by the gate layer 36 has The undoped area is defined as a channel area.

  In the above method, the pattern of the LDD structure is first defined by using the pattern of the gate layer 36, and the source / drain electrodes are further defined by the pattern of the second photoresist layer 42. The effect on the LDD structure is eliminated. However, due to photo misalignment of the exposure technique and two ion implantation steps, the position shift of the LDD structure also occurs, and a complicated manufacturing process cannot be improved. There are also problems.

  Accordingly, a main object of the present invention is to provide a polycrystalline silicon thin film transistor having a self-aligned LDD structure, which utilizes a difference in thickness between a gate insulating layer and a source / drain area located in the LDD structure to perform one-time operation. An LDD structure and a source / drain area can be manufactured at the same time by combining with an ion implantation step, and an object of the present invention is to solve the problems of the conventional technology.

  To achieve the above object, the present invention provides a thin film transistor having a self-aligned lightly doped drain (LDD) structure. The thin film transistor according to the present invention forms, on a substrate, an effective layer including a channel area, a first doped area located around the channel area, and a second doped area located around the first doped area. A center area that covers the first dope area, a shielding area that covers the first dope area, and an extension area that covers the second dope area, and at least these three areas, A gate insulating layer formed on the effective layer and a gate layer formed on the gate insulating layer, covering the center area, exposing the shielding area and the extended area, are included. The thickness of the shielding area of the gate insulating layer is larger than that of the gate insulating layer extending area.

To achieve the above object, the present invention provides a method for manufacturing a thin film transistor having a self-aligned LDD structure. The manufacturing method includes the following steps.
1. Provide a substrate.
2. An effective layer is formed on a substrate.
3. A gate insulating layer is formed on the effective layer. On the gate insulating layer, a center area, a shield area located outside the center area, and an extension area located outside the shield area are defined.
4. A gate layer is formed over the gate insulating layer.
5. Etching is performed to cover the center area in the gate insulating layer with the gate layer, exposing the shielding area and the extended area, and making the gate insulating layer shielding area thicker than that of the extended area.
6. Next, an ion implantation step is performed to form a first doped area in the effective layer covered by the shielding area, and to form a second doped area in the effective layer covered by the extension area.

By adjusting the etching conditions can control the difference in thickness D ₂ of the first portion of the thickness D ₁ and the shielding area of a portion of the drawing area, can use more relatively thick cover area as a mask for ion implantation process LDD structure Therefore, the position of the LDD structure of the present invention becomes more accurate, and it can respond to the requirement in the electrical durability of the thin film transistor.

  Since it is not necessary to define the pattern of the LDD structure with a mask exceeding a certain amount, it is possible to prevent the position shift problem caused by the LDD structure due to misalignment of the exposure technology, and thus to accurately control the position of the LDD structure, Electricity expression can also be secured.

Since the use of the mask is reduced once and the ion implantation process is performed only once, it is possible to improve the production rate and production speed in addition to simplifying the manufacturing steps and reducing costs, so that it can respond to the demand for mass production. Is possible.
The method of the present invention can simultaneously adjust the characteristics of the parts by doping the NMOS area and the PMOS area with different degrees of doping, thereby contributing to simplification of the manufacturing process and improvement of the production rate and speed.

  In order that the objects, features, and advantages of the present invention will be more clearly understood, embodiments will be described below in detail with reference to the drawings.

  FIG. 6 is a sectional view showing a self-aligned LDD structure of the thin film transistor according to the first embodiment of the present invention. On the substrate 50, a buffer layer 52, an effective layer 54, a gate insulating layer 56, and a gate layer 58 are sequentially formed. The substrate 50 is preferably a transparent insulating substrate such as a glass substrate, and the buffer layer 52 is preferably a dielectric material layer such as a silicon oxide layer for the purpose of assisting the formation of the effective layer 54 on the substrate 50. . Further, the effective layer 54 is preferably a semiconductor silicon layer such as a polycrystalline silicon layer. The gate insulating layer 56 is preferably a silicon oxide layer, a silicon nitride layer, a silicon nitride oxide layer, or a deposited layer obtained by combining them. The gate layer 58 is preferably a conductive material layer such as a metal layer or a polycrystalline silicon layer.

  The features of the structure of the thin film transistor according to the first embodiment of the present invention will be described below.

  The gate insulating layer 56 includes a center area 56a, two shielding areas 56b, and two extending areas 56c. The center area 56a is covered by the bottom of the gate layer 58, and the shielding area 56b is formed on both sides of the bottom of the gate layer 58. And is located outside the center area 56a. The extension area 56c is located outside the shielding area 56b. The effective layer 54 includes a channel area 54c, two LDD structures 54b, and two source / drain areas 54a. The channel area 54c is covered by the bottom of the gate layer 58 and is located at a position corresponding to the center area 56a. The LDD structure 54b is located on both sides of the channel area 54c, covered by the shielding area 56b. The source / drain area 54a is covered with the extension area 56c and located on both sides of the LDD structure 54b.

Based on the features described above, controlled by adjusting the condition parameters of the photolithography and etching process of the gate layer 58 and the gate insulating layer 56, the difference in thickness D ₂ of the thickness D ₁ and the shielding area 56b of the extending segment 56c can, the relationship between the thickness _{D 1} and _{D 2} can be expressed using the formula _{D 1} <D _2. In addition, the thickness D ₁ of the extending segment 56c is much thinner than the thickness D ₂ of the shielding area 56b, it is also possible to close the thickness D ₁ to the minimum value. Therefore, by using the relatively thick shielding area 56b as a mask for the ion implantation step of the LDD structure 54b and adjusting the implantation energy and quantity of the ion implantation step, the completion of the LDD structure 54b can be achieved in one ion implantation step. , The source / drain area 54a can be manufactured simultaneously. In this case, the width of the shielding area 56b is 0.1 to 2.0 μm, the implantation energy is 1.60 × 10 ^{−15 to} 1.60 × 10 ⁻¹⁴ J (10 to 100 keV), and the ion implantation amount is 2 × 10 ¹⁸ atoms. / Cm ³ (this unit means that the number of ions or atoms per 1 cm ² in the LDD structure is 2 × 10 ¹⁸ per unit volume; the same applies hereinafter), and the doping concentration of the LDD structure 54b is 1 × 10 ¹² to 1 × 10 ¹⁴ atoms / cm ² (this unit means that the number of ions or atomic distribution per 1 cm ² in the LDD structure is 2 × 10 ¹⁴ per unit area; the same applies hereinafter), source The doping concentration of the / drain area 54a is preferably 1 × 10 ¹⁴ to 1 × 10 ¹⁶ atoms / cm ² .

  Therefore, the thin film transistor according to the first embodiment of the present invention has the following advantages.

First, by adjusting the etching conditions can be controlled for differences in the thickness D ₂ of the thickness D ₁ and the shielding area 56b of the extending segment 56c, further relatively thick shielding area 56b of the LDD structure 54b ion implantation step Can be used as a mask, so that the position of the LDD structure 54b of the present invention can be made more accurate, and it is possible to meet the requirements regarding the electrical durability of the thin film transistor.

  Second, since it is not necessary to use an extra mask to define the pattern of the LDD structure 54b, it is possible to avoid the problem that the misalignment of the exposure technique shifts the position of the LDD structure 54b, and therefore the LDD structure 54b. Since the position of 54b can be controlled accurately, it is possible to secure the electrical durability of the thin film transistor.

  Third, the number of mask and ion implantation steps can be reduced, which simplifies the manufacturing process, and has the advantages of keeping costs low, as well as mass production by improving yield and production speed. Can also answer the request.

In addition, the thin film transistor according to the first embodiment of the present invention can be applied to a P-type thin film transistor. The LDD structure 54b is an N ^- doped area, and the source / drain area 54a is an N ⁺ doped area. The thin film transistor of Embodiment 1 of the present invention can also be applied to an N-type transistor, in which case the LDD structure 54b is a P ^- doped area and the source / drain area 54a is a P ⁺ doped area. Although the shape of the gate layer 58 of the present invention is not limited, a square or trapezoid is relatively preferable.

  7 and 8 are sectional views showing a self-aligned LDD structure of a thin film transistor according to Embodiment 2 of the present invention. The features of the components and the structure of the thin film transistor of the second embodiment are almost the same as those of the first embodiment, and the description is omitted. The difference is that the gate insulating layer 56 according to the second embodiment is composed of a first insulating layer 55 and a second insulating layer 57. Among them, the first insulating layer 55 includes a silicon oxide layer, a silicon nitride layer, A silicon nitride oxide layer or a combination thereof is preferable, and the second insulating layer 57 is also preferably a silicon oxide layer, a silicon nitride layer, a silicon nitride oxide layer, or a combination thereof.

On the gate insulating layer 56, a center area 56a, two shielding areas 56b, and two extending areas 56c are defined. In the center area 56a, the two-layer structure of the first insulating layer 55 and the second insulating layer 57 covers the channel area 54c. In the shielding area 56b, a two-layer structure of the first insulating layer 55 and the second insulating layer 57 covers the LDD structure 54b, and is exposed on both sides of the gate layer 58. In the extension area 56c, the first insulating layer 55 covers the source / drain area 54a. By comparison, the thickness D ₁ of the gate insulating layer 56 in the extending segment 56c is relatively thin, the thickness D ₂ of the gate insulating layer 56 in the shielding area 56b is relatively thick.

The feature of Embodiment 2 of the present invention resides in that a difference in thickness between the shielding area 56b and the extended area 56c can be created by stacking the first insulating layer 55 and the second insulating layer 57, and the first insulating layer in the extended area 56c. thickness D ₁ and can control the thickness D ₂ of the gate insulating layer 56 of the shielding area 56b, the relationship of D ₁ and D ₂ can be represented by the formula such as D _{1 <D 2.} Furthermore, the thickness D ₁ of the extending segment 56c is much smaller than the thickness D ₂ of the shielding area 56b, D ₁ can be brought close to the minimum value. In this manner, the relatively thick shielding area 56b is used as a mask for the ion implantation step of the LDD structure 54b, and the implantation energy and the amount of the ion implantation step can be adjusted. It is also possible to complete the fabrication of 54a at the same time. In this case, the width of the shielding area 56b is 0.1 to 2.0 μm, the implantation energy is 1.60 × 10 ^{−15 to} 1.60 × 10 ⁻¹⁴ J (10 to 100 keV), and the ion implantation amount is 2 × 10 ^18. smaller than the atom / cm ^3, the doping concentration of the LDD structure 54b is ^{1 × 10 12 ~1 × 10 14} atom / cm 2, the doping concentration of the source / drain area 54a is ^{1 × 10 14 ~1 × 10 16} atom / cm ² is preferred. Therefore, the thin film transistor of the second embodiment has the same advantages as the first embodiment.

By way of comparison, FIG. 7 shows a stretched area 56c produced by stopping the etching of the second insulating layer 57 on the first insulating layer 55, and FIG. 8 shows a stretched area 56c that overetches the first insulating layer 55. It was produced by doing. Therefore, the thickness D ₂ of the first insulating layer 55 of the extending segment 56c in FIG. 7 is relatively thick, and the thickness D ₁ of the first insulating layer 55 of the extending segment 56c in FIG. 8 is relatively thin, D ₁ <represented by the formula such as D _2, both have similar advantages. In addition, the gate insulating layer 56 can have three or more insulating deposition effects, and an effect due to the difference in thickness between the shielded area 56b and the extended area 56c can be expected.

  9 to 14 are sectional views of a method for manufacturing a self-aligned LDD structure of a thin film transistor according to Embodiment 3 of the present invention.

  The thin film transistor manufacturing method of the present invention can be applied to a P-type thin film transistor or an N-type thin film transistor. Hereinafter, a method for manufacturing a self-aligned LDD structure will be described in detail using the thin film transistor of the first embodiment as an example.

  First, FIG. 9 shows a buffer layer 52 formed on a substrate 50 and an effective layer 54 formed on the buffer layer 52. The substrate 50 is preferably a transparent insulator such as a glass substrate, for example, and the buffer layer 52 is preferably an electrical material layer such as a silicon oxide layer that assists in forming the effective layer 54 on the substrate 50. The effective layer 54 is preferably a semiconductor silicon layer such as a polycrystalline silicon layer. The present invention is not limited to the thickness and the manufacturing method of the effective layer 54. For example, in manufacturing the effective layer 54, a low temperature polycrystalline silicon (LTPS) process can be adopted, and first, an amorphous silicon layer is formed on a glass substrate. Then, the amorphous silicon layer is changed to a polycrystalline silicon material by a heat treatment or an excimer laser annealing (ELA) method.

  Next, as shown in FIG. 10, a gate insulating layer 56 and a gate layer 58 are sequentially deposited on the effective layer 54, and a patterned photoresist layer 60 is formed on the gate layer 58. The gate insulating layer 56 is preferably a silicon oxide layer, a silicon nitride layer, a silicon nitride oxide layer or an integrated layer or a deposited layer of a combination thereof, and the gate layer 58 is a conductive material such as a metal layer or a polycrystalline silicon layer. Layers are preferred. The size and position of the patterned photoresist layer 60 correspond to the pattern of the gate layer 58 that will be formed next.

Next, as shown in FIG. 11, an etching process is performed using the patterned photoresist layer 60 as a mask, and one of the gate layer 58 and the gate insulating layer 56 outside the area of the patterned photoresist layer 60 is formed. The portions are removed and the pattern of the gate layer 58 is defined. At this time, a plasma etching or a reactive ion etching method is employed. In this step, the degree of etching of the gate insulating layer 56 can be appropriately adjusted, and the gate insulating layer other than the gate layer 58 pattern can be adjusted. It is also possible to reserve 56 parts. Therefore the area on which the source / drain of the active layer 54 is extending segment 56c is formed, and the thickness D ₂ of the drawing area 56c thicknesses D ₁ and the gate layer 58 under the gate insulating layer 56 is D _{1 <D It} needs to be expressed by an equation like ₂ .

Next, as shown in FIG. 12, the shape of the gate layer 58 is made trapezoidal, the bottom of the gate layer 58 covers only the center area 56a of the gate insulating layer 56, and the gate insulating layers 56 located on both sides of the bottom of the gate layer 58 are formed. Then, the source / drain area of the effective layer 54 is covered with the extension area 56c of the gate insulating layer 56. Moreover, this step can be adjusted to approximately etching of the gate insulating layer 56, the thickness D ₂ of the thickness D ₁ and the gate layer 58 under the gate insulating layer 56 of the extending segment 56c in expressions such as D _{1 <D 2} Can be represented.

  For example, a mixed gas containing oxygen and chlorine is used as a reaction gas in the etching process, and the flow rate of each gas is adjusted as necessary. In the step of etching the gate layer 58, the flow rate of the gas containing oxygen is gradually adjusted to a maximum value, or the shape of the gate layer 58 is formed in a trapezoidal shape using a gas containing only oxygen as an etching reaction gas. Can be. In the etching step of the gate insulating layer 56, the flow rate of the gas containing oxygen can be adjusted to the minimum value, and only the gas containing oxygen can be used as the etching reaction gas. Alternatively, this step can be further performed instead of the etching step shown in FIG. 11, thereby reducing manufacturing time and cost.

  Then, as shown in FIG. 13, after removing the patterned photoresist layer 60, an ion implantation step 62 is performed using the gate layer 58 and the shielding area 56b as a mask. In this way, the effective layer 54 covered by the shielding area 56b becomes a lightly doped area, which is used as the LDD structure 54b. The effective layer 54 that is not covered by the gate layer 58 and the shielding area 56b becomes a highly doped area, which is referred to as a source / drain area 54a. Further, the effective layer 54 covered with the gate layer 58 and the center area 56a is an undoped area, which is referred to as a channel area 54c.

As operation conditions of the ion implantation step 62, the implantation energy is 1.60 × 10 ^{−15 to} 1.60 × 10 ⁻¹⁴ J (10 to 100 keV), and the ion implantation amount is smaller than 2 × 10 ¹⁸ atoms / cm ³ . The doping concentration of the LDD structure 54b is preferably 1 × 10 ¹² to 1 × 10 ¹⁴ atoms / cm ² , and the doping concentration of the source / drain area 54a is preferably 1 × 10 ¹⁴ to 1 × 10 ¹⁶ atoms / cm ² . More preferably, the ion implantation amount is 1 × 10 ¹³ atoms / cm ³ or less. The method of the present invention can be applied to a P-type thin film transistor, in which case the LDD structure 54b is an N ^- doped area and the source / drain area 54a is an N ⁺ doped area. Also, the present invention can be applied to an N-type thin film transistor. In this case, the LDD structure 54b is a P ^- doped area, and the source / drain area 54a is a P ⁺ doped area.

  Finally, in FIG. 14, an interconnect process is performed, which involves the fabrication of an in-line dielectric layer 64, a plurality of contact holes 65, and a plurality of in-line 66, but the manner of performing this step is substantially the same as that of the present invention. It will not be described in detail here as it does not affect the features and effects.

  Therefore, the method for manufacturing a thin film transistor according to the third embodiment of the present invention has the following advantages.

First, as a mask for the extension of the area 56c between the thickness D ₁ can control the difference in thickness D ₂ of the shielding area 56b, further relatively thick shielding area 56b of the LDD structure 54b ion implantation process by adjusting the etching conditions It can be used, and thus, the position of the LDD structure 54b of the present invention becomes more accurate, and can meet the requirement in the electrical durability of the thin film transistor.

  Second, since there is no need to prepare an extra mask to define the pattern of the LDD structure 54b, it is possible to prevent the position shift problem caused by the LDD structure due to misalignment of the exposure technique, and thus to position the LDD structure 54b. Accurate control can be achieved, and the electrical durability of the thin film transistor can be secured.

  Third, since the use of the mask is reduced once and the ion implantation process is performed only once, the production rate and the production speed can be improved in addition to the simplification of the manufacturing steps and the reduction of the cost. It is possible to answer the request.

  Fourth, the method of the present invention can simultaneously adjust the characteristics of the device by doping to different extents in the NMOS area and the PMOS area, thereby contributing to simplification of the manufacturing process, yield, and improvement in production rate.

  15 to 18 are sectional views of a method for manufacturing a self-aligned LDD structure of a thin film transistor according to Embodiment 4 of the present invention.

  The method for manufacturing a thin film transistor of the present invention is applied to a P-type thin film transistor or an N-type thin film transistor. Hereinafter, a method for manufacturing the self-aligned LDD structure will be described in detail by taking the structure of the thin film transistor of the second embodiment as an example. The implementation steps of the fourth embodiment are almost the same as those of the third embodiment, and will not be described again here.

  First, in FIG. 15, a substrate 50 is provided, and a buffer layer 52, an effective layer 54, a first insulating layer 55, a second insulating layer 57, a gate layer 58, and a patterned photoresist layer 60 are sequentially formed on the substrate 50. Form. Preferably, the substrate 50 is a glass substrate, the buffer layer 52 is a silicon oxide layer, and the effective layer 54 is a polycrystalline silicon layer. The first insulating layer 55 includes a silicon oxide layer, a silicon nitride layer or a silicon nitride oxide layer, the second insulating layer 57 includes a silicon oxide layer, a silicon nitride layer, and a silicon nitride oxide layer, and the gate layer 58 includes a conductive material. Layers, metal layers and polycrystalline silicon layers are preferred. The size and position of the patterned photoresist layer 60 correspond to the pattern of the gate layer 58 to be formed later.

  The feature of Embodiment 4 of the present invention is that a first insulating layer 55 and a second insulating layer 57 are combined to form a gate insulating layer 56, and a center area 56a and two shielding areas 56b are formed on the gate insulating layer 56. The extension area 56c is defined.

  Next, in FIG. 16, an etching process is performed using the patterned photoresist layer 60 as a mask, and a portion of the gate layer 58 and a part of the gate insulating layer 56 other than the area of the patterned photoresist layer 60 are removed. This is defined as a pattern of the gate layer 58. Here, the etching step is preferably a plasma etching method or a reactive ion etching method, and this step is suitable for adjusting the degree of etching of the first insulating layer 55 and the second insulating layer 57, and the second step of the extension area 56c is performed. The insulating layer 57 is removed, and the first insulating layer 55 in the extension area 56c is reserved. Thus, the first insulating layer 55 covers the portion of the effective layer 54 that will be the source / drain area. In this way, the thickness of the first insulating layer 55 in the extension area 56c is smaller than the thickness of the two layers of the first insulating layer 55 and the second insulating layer 57 in the shielding area 56b.

Next, in FIG. 17, the shape of the gate layer 58 is trapezoidal, and the bottom of the gate layer 58 covers only the center area 56a. Further, two layers of the first insulating layer 55 and the second insulating layer 57 in the shielding area 56 are exposed from both sides of the bottom of the gate layer 58, and the first insulating layer 55 in the extension area 56c is formed on the effective layer 54. Covers source / drain areas. Moreover, this step can be selected approximately etching of the first insulating layer 55 of a material, a first insulating layer 55 and the second insulating layer in the first thickness D ₁ and the shielding area 56b of the insulating layer 55 of the extending segment 56c 57 the thickness D ₂ of the two layers can be represented by the formula such as D _{1 <D 2} of. Alternatively, this step can be further performed in place of the etching step shown in FIG. 11, thereby reducing manufacturing time and cost.

Then, as shown in FIG. 18, after removing the patterned photoresist layer 60, an ion implantation process is performed using the two layers of the gate layer 58, the first insulating layer 55 and the second insulating layer 57 in the shielding area 56b as a mask. Perform 62. In this way, the effective layer 54 in the shielding area 56b is made a lightly doped area, and the LDD structure 54b is obtained. The effective layer 54 in the extension area 56c is a highly doped area and is a source / drain area 54a. The effective layer 54 in the center area 56a is an undoped area, and is referred to as a channel area 54c. As operation conditions of the ion implantation step 62, the implantation energy is 1.60 × 10 ^{−15 to} 1.60 × 10 ⁻¹⁴ J (10 to 100 keV), and the ion implantation amount is smaller than 2 × 10 ¹⁸ atoms / cm ³ . The doping concentration of the LDD structure 54b is preferably 1 × 10 ¹² to 1 × 10 ¹⁴ atoms / cm ² , and the doping concentration of the source / drain area 54a is preferably 1 × 10 ¹⁴ to 1 × 10 ¹⁶ atoms / cm ² . More preferably, the amount of ion implantation is smaller than 1 × 10 ¹³ atoms / cm ³ .

  Finally, an interconnect process is performed. However, since the manner of performing this step does not substantially affect the features and effects of the present invention, the description is omitted here. The manufacturing method according to the fourth embodiment of the present invention also has the same advantages as the third embodiment, and will not be described here. In addition to this, the gate insulating layer 56 can adopt a three-layer or more deposition effect, and therefore, the effect of the difference in thickness between the shielding area 56b and the extension area 56c can be expected.

  Although the preferred embodiments of the present invention have been described above, they do not limit the present invention, and various changes and modifications that can be made by those skilled in the art without departing from the spirit and scope of the present invention. It is possible to add Therefore, the scope of the invention for which protection is sought is based on the claims that follow.

It is sectional drawing of the manufacturing method of the LDD structure of the conventional polycrystalline silicon TFT. It is sectional drawing of the manufacturing method of the LDD structure of the conventional polycrystalline silicon TFT. It is sectional drawing of the conventional manufacturing method of the LDD structure of another kind of polycrystalline silicon TFT. It is sectional drawing of the conventional manufacturing method of the LDD structure of another kind of polycrystalline silicon TFT. It is sectional drawing of the conventional manufacturing method of the LDD structure of another kind of polycrystalline silicon TFT. 1 is a cross-sectional view of a self-aligned LDD structure of a thin film transistor according to Embodiment 1 of the present invention. FIG. 6 is a cross-sectional view of a self-aligned LDD structure of a thin film transistor according to Embodiment 2 of the present invention. FIG. 6 is a cross-sectional view of a self-aligned LDD structure of a thin film transistor according to Embodiment 2 of the present invention. FIG. 13 is a sectional view of the method for manufacturing the self-aligned LDD structure of the thin film transistor according to the third embodiment of the present invention. FIG. 13 is a sectional view of the method for manufacturing the self-aligned LDD structure of the thin film transistor according to the third embodiment of the present invention. FIG. 13 is a sectional view of the method for manufacturing the self-aligned LDD structure of the thin film transistor according to the third embodiment of the present invention. FIG. 13 is a sectional view of the method for manufacturing the self-aligned LDD structure of the thin film transistor according to the third embodiment of the present invention. FIG. 13 is a sectional view of the method for manufacturing the self-aligned LDD structure of the thin film transistor according to the third embodiment of the present invention. FIG. 13 is a sectional view of the method for manufacturing the self-aligned LDD structure of the thin film transistor according to the third embodiment of the present invention. FIG. 13 is a sectional view of the method for manufacturing the self-aligned LDD structure of the thin film transistor according to the fourth embodiment of the present invention. FIG. 13 is a sectional view of the method for manufacturing the self-aligned LDD structure of the thin film transistor according to the fourth embodiment of the present invention. FIG. 13 is a sectional view of the method for manufacturing the self-aligned LDD structure of the thin film transistor according to the fourth embodiment of the present invention. FIG. 13 is a sectional view of the method for manufacturing the self-aligned LDD structure of the thin film transistor according to the fourth embodiment of the present invention.

Explanation of reference numerals

10 transparent insulating substrate 12 a polysilicon layer 14 gate insulating layer 16 a photoresist layer 17 heavy ion implantation process 18 N ⁺ doped area 20 gate layer 21 low ion implantation process 22 N ^- doped areas 30 transparent insulating substrate 32 polycrystalline silicon layer 34 Gate insulating layer 36 Gate layer 38 First photoresist layer 39 Low ion implantation step 40 N ^- doped area 42 Second photoresist layer 43 Heavy ion implantation step 44 N ⁺ doped area 50 Substrate 52 Buffer layer 54 Effective layer 54a Source / drain Area 54b LDD structure 54c Channel area 56 Gate insulating layer 56a Center area 56b Shielding area 56c Extension area 55 First insulating layer 57 Second insulating layer 58 Gate layer 60 Patterned photoresist layer 62 Ion implantation step 64 Interconnect Conductive layer 65 contact hole 66 Interconnect

Claims (9)

  Forming an effective layer including a channel area on the substrate, a first doped area located around the channel area, and a second doped area located around the first doped area; and forming at least an effective layer on the effective layer. A center area covering the channel area, a shielding area located around the center area and covering the first doped area, and an extension area located around the shielding area and covering the second doped area. Including a gate insulating layer, and a gate layer located on the gate insulating layer, covering the center area, exposing the shielding area and the extending area, wherein the thickness of the shielding area of the gate insulating layer is The self-aligned lightly-doped drain is thicker than the extension area of the gate insulating layer. ain, LDD).   The gate insulating layer includes a first insulating layer and a second insulating layer, a shielding area of the gate insulating layer is formed by depositing the first insulating layer and the second insulating layer, and an extending area of the gate insulating layer is The thin film transistor having a self-aligned LDD structure according to claim 1, comprising the first insulating layer.   3. The thin film transistor according to claim 1, wherein a doping concentration of the first doping area is lower than a doping concentration of the second doping area.   4. The thin film transistor having a self-aligned LDD structure according to claim 1, wherein a width of the shielding area of the gate insulating layer is 0.1 to 2.0 [mu] m.   The substrate is formed of a transparent insulating substrate or a glass substrate, the effective layer is formed of a semiconductor silicon layer or a polycrystalline silicon layer, and the gate insulating layer is formed of any of a silicon oxide layer, a silicon nitride layer, and a silicon nitride oxide layer. Item 5. A thin film transistor comprising the self-aligned LDD structure according to any one of Items 1 to 4.   Providing a substrate, forming an effective layer on the substrate, a center area on the effective layer, a shielding area located around the center area, and being located around the shielding area. Forming a gate insulating layer having three extended areas; forming a gate layer on the gate insulating layer; and performing an etching process, wherein the gate layer covers the center area of the gate insulating layer. Exposing the shielded area and the extended area of the gate insulating layer, making the thickness of the shielded area larger than the thickness of the extended area, and performing an ion implantation step, and the effective layer covered with the shielded area Forming a first doped area, and forming a second doped area in the effective layer covered by the extension area. Manufacturing method of a thin film transistor having a self-alignment LDD structure.   The method of manufacturing the shielded area and the extended area of the gate insulating layer includes: forming a first insulating layer on the effective layer; forming a second insulating layer on the first insulating layer; Performing a process, removing the second insulating layer in the extended area, and retaining the first insulating layer in the extended area; and the shielding area is constituted by the first insulating layer and the second insulating layer. 7. A method for manufacturing a thin film transistor having a self-aligned LDD structure according to claim 6, comprising the steps of: The doping concentration of the first doping area is in a range of 1 × 10 ¹² to 1 × 10 ¹⁴ atoms / cm ² , and the doping concentration of the second doping area is 1 × 10 ¹⁴ to 1 × 10 ¹⁶ atoms / cm ² . A method for manufacturing a thin film transistor having a self-aligned LDD structure according to claim 6, wherein the range is a range.   The substrate is formed of a transparent insulating substrate or a glass substrate, the effective layer is formed of a semiconductor silicon layer or a polycrystalline silicon layer, and the gate insulating layer is formed of any of a silicon oxide layer, a silicon nitride layer, and a silicon nitride oxide layer. Item 10. A method for manufacturing a thin film transistor having a self-aligned LDD structure according to any one of Items 6 to 8.

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