JP2004336699A - Impedance adjustment circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To realize highly accurate trimming by excluding the influence of production variation. <P>SOLUTION: A common bias part 11 is composed of a serial circuit wherein an incorporated resistor R1 and an external resistor Rext are serially connected, and an operational amplifier OP 1 wherein a reference voltage Vref is inputted to a first input terminal, a second input terminal is connected to a node Vr1, and an output terminal is connected to the serial circuit. An impedance trimming part 12 is composed of a serial circuit wherein an incorporated resistor Rto and an impedance simulating resistor Rto trim are serially connected, a comparator CMP wherein a first input terminal is connected to the node Vr1 and a second input terminal is connected to a node Vto1, a code control circuit 13 for latching the output signal of the comparator CMP with a clock signal CLK to generate a plurality of switching codes, and a circuit for switching resistance values of the impedance simulating resistor Rto trim. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to an impedance adjustment circuit that performs high-quality transfer of a high-speed serial signal by suppressing signal reflection by performing impedance matching such as an output impedance, an input impedance, and a terminating resistor. It is used for LSIs that need to automatically adjust impedance.

  Conventionally, in a high-speed interface such as USB 2.0 (480 Mbps) or LVDS (several Gbps), matching input impedance, drive impedance, pull-up / pull-down resistance, etc. to a standard value (for example, ± 10%) requires a transfer signal. This was indispensable for suppressing reflection of the waveform and transmitting high-quality high-speed signals.

  However, there are large variations (for example, ± 20%) of the resistance elements formed in the LSI manufacturing process, and large dependences of the on-resistance of the output transistor on temperature, power supply voltage, and threshold value (for example, worst vest = double / half). Some kind of adjustment circuit was needed.

Non-Patent Document 1 is shown as a first example of the related art.
In Non-Patent Document 1, as shown in FIGS. 26 and 27, the operational amplifier adjusts the voltage drop of the external resistor Rext to the internal reference voltage Vref. The output signal of the operational amplifier is supplied to the gates of two P-channel MOS transistors. The output signal of the output buffer is obtained as a positive and negative differential output at a Data + terminal and a Data− terminal by a voltage drop of a built-in resistor. This circuit has an auxiliary circuit for adjustment separately from the circuit for data transfer. The auxiliary circuit performs control to find a code such that the potential of the VA terminal is closest to Vref.

  In this case, the output impedance is a built-in resistance and a MOS resistance. In this conventional example, this value is adjusted to 45Ω ± 5Ω. That is, the size of the MOS transistor is adjusted by the comparator and the control circuit, a code with the smallest error is found, the size of the MOS transistor is adjusted, and the code is given to the output buffer.

  However, this method is affected by various factors such as the variation of the reference voltage, the input offset voltage of the operational amplifier, the variation of the current ratio of the current source including the P-channel MOS transistor, and the variation of the MOS resistance. However, it was difficult to adjust with high accuracy.

  For example, when the current ratio of a current source formed of a P-channel MOS transistor fluctuates by about 5%, the fluctuation alone results in an allowable range of output impedance of 45Ω ± 5Ω. For this reason, there are disadvantages such as a decrease in yield and a need for labor in management of the manufacturing process, and it is difficult to make adjustments with high accuracy in reality.

Further, Non-Patent Document 2 is shown as a second example of the related art.
In Non-Patent Document 2, as shown in FIG. 28, the value of the internal trimming resistor is switched so that the externally applied reference voltage Vref and the divided voltage by the external resistor and the internal trimming resistor are the most equal, and the switching is performed. The code is reflected in the switching of the input termination resistance.

  As shown in FIG. 29, the built-in trimming resistor is composed of a resistor R0 directly connected between IP and IN, and resistors R1 to R8 connected via switches whose ON / OFF are controlled by a code. You.

  As shown in FIG. 30, the value of the resistor R0 is set to a large value in advance in consideration of the variation range of the built-in resistor, and by sequentially connecting the resistors R1 to R8, the adjustment of the built-in trimming resistor is performed over a wide range. The value is in the range of 100Ω ± 10Ω.

  However, this method requires a circuit for generating the reference voltage Vref and two high-precision resistors externally, so that there is a problem that the cost increases. Also, this method can only be used at the end of the input. The output impedance must be adjusted including the on-resistance of the output buffer as shown in the first example of the prior art.

Patent Document 1 is shown as a third example of the related art.
In Patent Document 1, as shown in FIG. 31, the current of a current source composed of a P-channel MOS transistor is adjusted by an operational amplifier such that the voltage drop VZQ of the external resistor RQ becomes に な る of the power supply VDDQ. In addition, a current is caused to flow through the output driver by the current mirror, and the size of the output driver is adjusted so that the voltage drop is equal to VZQ.

Even in this case, since these factors directly affect the variation of the output resistance, such as the offset voltage of the operational amplifier and the variation of the current mirror current, there has been a limit to the adjustment with high accuracy.
JP 2001-94048 A JP-A-8-335871 JP-A-11-31960 JP 2003-69412 A ESSCIRC2001 "A New Impedance Control Circuit for USB2.0 Transceiver" Koo K.-H.SAMSUNG Electronics (http://www.esscirc.org/esscirc2001/C01_Presentations/5.pdf) ESSCIRC2001 "Digitally tuneable on-chip line termination resistor for 2.5Gbit / s LVDS receiver in 0.25μm standard CMOS technology" M. Kumric, F. Ebert, R. Ramp, K. Welch Alcatel SEL Stuttgart (http: //www.esscirc .org / esscirc2001 / C01_Presentations / 98.pdf)

  As described above, conventionally, there has been a long-felt need for an impedance adjustment circuit that eliminates the influence of variations in the LSI manufacturing process, realizes high-precision trimming, and can be configured with a small number of external components.

  SUMMARY OF THE INVENTION It is an object of the present invention to provide an impedance adjustment circuit that eliminates the influence of variations in LSI manufacturing processes, realizes highly accurate trimming, and can be configured with a small number of external components.

  An impedance adjustment circuit device according to an example of the present invention includes: (1) a first series circuit in which a first internal resistor and an external resistor are connected in series via a first node, and an internal reference voltage input to a first input terminal. A second input terminal is connected to the first node, and an output terminal is connected to the first operational amplifier; and a first operational amplifier is connected to the common bias section; and (2) a second internal resistor and impedance A second series circuit having a simulated resistor connected in series via a second node, a comparator having a first input terminal connected to the first node, and a second input terminal connected to the second node; An impedance trimming unit configured to latch an output signal of the comparator with a clock signal and generate a plurality of switching codes, and an output terminal of the first operational amplifier, Is also connected to the series circuit, with one of said plurality of switching code switches the resistance value of the target impedance adjusting resistor to be said impedance simulated resistance value of the resistor and the actual impedance adjustment.

  According to the impedance adjustment circuit according to the example of the present invention, it is possible to eliminate the influence of variations in the LSI manufacturing process, realize high-precision trimming, and reduce the manufacturing cost by configuring with a small number of external components. Can be.

  Hereinafter, the best mode for carrying out the example of the present invention will be described in detail with reference to the drawings.

1. Overview
First, the impedance adjustment circuit according to the example of the present invention includes a common bias circuit including a reference voltage circuit, a built-in resistor R1, a high-precision external resistor Rext, and an operational amplifier OP1, another built-in resistor Rto, a driver simulation resistor Rdrv, and an output. The circuit includes an impedance simulation resistor Rto_trim, an operational amplifier OP1, a comparator CMP, and an output impedance adjustment circuit including a code control circuit.

The resistance value of the built-in resistor is R1, the resistance value of the high-precision external resistor is Rext, the resistance value of another built-in resistor is Rto, the resistance value of the driver simulation resistor is Rdrv, and the resistance value of the output impedance simulation resistor is Rto_trim. And if
Rext: R1 = (Rdrv + Rto_trim): Rto
Or the value of Rto_trim is switched so as to be the relationship or the closest relationship, and this switching information is reflected in the driver circuit.

The impedance adjustment circuit according to the example of the present invention further includes an input impedance trimming circuit including another built-in resistor Rti, an input impedance simulation resistor Rti_trim, an operational amplifier OP2, a comparator CMP, and a code control circuit. When the resistance value of another built-in resistor is Rti and the resistance value of the input impedance simulation resistor is Rti_trim,
Rext: R1 = Rti_trim: Rti
The value of Rti_trim is switched so as to have the relationship of or the closest to this, and this switching information is reflected on the input impedance circuit.

  Note that the impedance adjustment circuit according to the example of the present invention may have at least one of the output impedance adjustment circuit and the input impedance adjustment circuit. When only the output impedance adjustment circuit is used, when only the input impedance adjustment circuit is used, or when both are used, a plurality of these elements may exist.

2. First embodiment
FIG. 1 shows an impedance adjustment circuit according to the first embodiment of the present invention.

  Rdrv (symbol △) represents an output driver. The common bias unit 11 includes an internal resistor R1 and a highly accurate external resistor Rext connected via the node Vr1, an operational amplifier OP1, to which the internal reference voltage Vref and the voltage of the node Vr1 are input, a P-channel MOS transistor P1, and N It has a channel MOS transistor N1. The P-channel MOS transistor P1 connected to the power supply VDD is a bias generation circuit for generating a constant current bias applied to another circuit, and is an attached circuit.

The operation will be described below with reference to FIG.
The operational amplifier OP1 controls the gate voltage of the N-channel MOS transistor (current control element) N1 so that the voltage Vr1 becomes equal to the internal reference voltage Vref. The voltage Vr2 is a value obtained by adding the voltage drop of the resistor R1 due to the current I1 to the voltage Vr1, that is, Vr2 = Vr1 + (R1 / Rext) × Vr1.

A specific calculation example will be described.
The internal reference voltage Vref is, for example, 1.2 V ± 5%. The external resistance Rext is a high-precision resistance, for example, 12 KΩ ± 0.1%. The power supply voltage VDD is, for example, 3.3 V ± 10%, and the offset voltage of the operational amplifier OP1 is, for example, ± 10 mV.

  The negative feedback circuit including the operational amplifier OP1 and the N-channel MOS transistor (current control element) N1 works so that the voltage drop value due to the external resistance Rext becomes equal to the internal reference voltage Vref. As a result, Vr1 becomes Vref. The accuracy is (1.2 V ± 5%) ± 10 mV, that is, 1.2 V ± 0.07 V due to the influence of the variation of the internal reference voltage Vref and the offset of the operational amplifier OP1.

The current I1 becomes Vr1 / Rext, and the current I1 also varies, for example, to 100 μA ± 7 μA. The voltage Vr2 is directly affected by the variation of the internal resistor R1. Assuming that the variation of the internal resistor R1 is, for example, 2.4 KΩ ± 20%, the voltage Vr2 becomes
Vr2 = Vr1 + I1 × R1
= (1.2V ± 0.07V) +
(100 μA ± 7 μA) × (2.4 KΩ ± 0.48 KΩ)
= 1.44V ± 0.13V
It becomes.

  What is important here is that Vr2 detects the ratio including the variation of the internal resistor R1 with respect to the external resistor Rext.

Next, the operation of the output impedance trimming unit 12 will be described.
The output impedance trimming unit includes a comparator CMP to which the voltage Vr1 and the voltage Vto1 are input, an operational amplifier OP2 to which the voltage Vr2 and the voltage Vto2 are input, a code control circuit 13 for receiving an output signal of the comparator CMP, an N-channel MOS transistor (current control element). ) N2, built-in resistor Rto, output impedance simulation resistor Rto_trim, and output driver simulation resistor Rdrv.

The operational amplifier OP2 controls the gate voltage of the N-channel MOS transistor N2 so that the voltage Vto2 becomes equal to the voltage Vr2. In this state, the voltage Vto1 is a divided voltage between Rto and (Rto_trim + Rdrv). What is important is that the ratio between Rext and R1 is equal to the ratio between Rto_trim + Rdrv and Rto.
Rext: R1 = (Rto_trim + Rdrv): Rto
The external resistance Rext is highly accurate. For this reason, even if the values of the built-in resistors R1, Rto, Rto_trim, and Rdrv vary, generally, if manufacturing is performed so that the relative accuracy between R1 and Rto is improved, the value of Rto_trim + Rdrv can be accurately specified. It can be within the range of values.

  The code control circuit 13 includes, for example, a multi-stage shift register. The output of the comparator CMP, which is the result of comparison between Vr1 and Vto1, is input to a multi-stage shift register that shifts with the clock signal CLK. The code is extracted from each stage of the shift register, and the resistance is switched. In switching the resistance, for example, the one shown in the second example of the prior art can be used.

  In this state, while the clock signal CLK is supplied many times, the potential relation between Vr1 and Vto1 switches back and forth (periodic transition) most, that is, Vr1 and Vto1 are closest and cross ±. Either back and forth between the two states, or the code will stall and stabilize. This state is a code in which Rto_trim + Rdrv is most equal to the standard value.

A specific calculation example will be described.
If the offset voltage of the operational amplifier is, for example, ± 10 mV,
Vto2 = Vr2 ± 10 mV = 1.44 V ± 0.13 V ± 10 mV
= 1.44V ± 0.14V
It becomes.

The current value Ito is
Vto2 / (Rto + Rto_trim + Rdrv)
It becomes.

Due to this current Ito, Vto1 has its voltage effect
Vto1 = Ito1 × (Rto_trim + Rdrv)
It becomes.

Therefore,
Vto1 = Vto2 / (Rto + Rto_trim + Rdrv) × (Rto_trim + Rdrv)
= Vto2 / (1 + Rto / (Rto_trim + Rdrv))
Vto2 is determined by the resistance ratio of Vto2.

The comparator CMP selects Rto_trim so that Vr1 and Vrto1 become the most equal. At this time, if the offset voltage of the comparator CMP is Voffcmp (± 20 mV),
Vto1 = Vr1 ± Voffcmp
It becomes.

In particular,
Right side = 1.2V ± 0.07V ± 0.02V = 1.2V ± 0.09V
It is.

Assuming that the right side and the left side Vto1 are equal,
1.2V ± 0.09V = (1.44V ± 0.14V) / (1 + Rto / (Rto_trim + Rdrv))
It becomes.

  Here, in order to reduce the current consumption, the output impedance adjustment circuit composed of Rto and (Rto_trim + Rdrv) adjusts the output impedance of the actual output buffer circuit Rdrv and the target impedance adjustment resistor Rto_use to be actually subjected to impedance adjustment. The resistance ratio is set to be several times, for example, six times.

Therefore, for example, when it is desired to set the actual driver output impedance to 45Ω,
Rto_trim + Rdrv becomes 270Ω,
Rto is Rext: R1 = (Rto_trim + Rdrv): Rto
, 12 KΩ: 2.4 KΩ = 270Ω: 54Ω
It becomes 54Ω.

  Further, it is assumed that Rto_trim + Rdrv = 270Ω, Rto_trim = 240Ω, and Rdrv = 30Ω.

  What is important here is that R1 and Rto are resistors formed in the same integrated circuit and can be manufactured with relative accuracy. Similarly, Rto_trim can be manufactured with relatively high accuracy. However, since Rdrv is composed of, for example, a MOS transistor, the variation includes transistor manufacturing variation.

Substituting into the previous equation,
1.2V ± 0.09V = (1.44V ± 0.14V) / (1+ (Rto / (Rto_trim + Rdrv))
And therefore,
Rto / (Rto_trim + Rdrv) = ((1.44V ± 0.14V) / (1.2V ± 0.09V))-1
It becomes.

Therefore, when the adjusted resistance Rto_trim is written on the left side,
Rto_trim = (Rto / ((1.44V ± 0.14V) / (1.2V ± 0.09V))-1) -Rdrv
It becomes.

Substitute specific values.
Rdrv = 30Ω ± 20Ω,
Rto = 54Ω ± 10.8Ω
Then
Rto_trim = ((54Ω ± 10.8Ω) / ((1.44V ± 0.14V) / (1.2V ± 0.09V) -1)) − (30Ω ± 20Ω)
It becomes.

If all are center conditions,
Rto_trim (center) = (54Ω / ((1.44V / 1.2V) -1))-30Ω = 240Ω
Can be calculated as

  That is, when Rto_trim is adjusted to be closest to 240Ω, 240Ω is finally obtained as the final value. If Rdrv = 30Ω in series is combined, the resistance becomes 270Ω, which is precisely adjusted to six times the target resistance of 45Ω.

  Variations of various factors can be obtained by the above-described calculation, however, since a complicated calculation is required, the description is omitted here. What is important is that, assuming a wide variation range, the adjustment range of the output impedance simulation resistor Rto_trim can be adjusted over a wide range.

FIG. 2 shows an embodiment of the adjustment range of the trimming circuit.
If the resistance ratio between the impedance adjustment circuit and the actual driver circuit is the same, a large amount of current flows through the impedance adjustment circuit, which is not preferable. Therefore, in order to reduce the current value in the impedance adjustment circuit, the value of the output impedance simulation resistor Rto_trim is set to a positive multiple of the resistance value of the target impedance adjustment resistor Rto_use to be actually adjusted, for example, about six times. Design large. In Table 1 below, the values are converted into the impedance of the output driver.

  By configuring the code control circuit 13 from a seven-stage shift register (see FIG. 4), the state of each stage of the code control circuit 13 is changed to eight states, and how the actual output impedance of the driver changes by switching. Is shown.

  Rto_trim is 20%, and the resistance of the switch required for switching is 5Ω + 3Ω / −2Ω, and is shown in the graph including the variation range.

  The trimming circuit is the same as the resistance switching unit of the second example of the prior art, and is calculated as R0 = 53.33Ω, the resistance value of each switch = 5Ω, R1,... R7 = 560Ω, and the driver resistance Rdrv = 5Ω. I have.

  Rto_trim + Rdrv is set in consideration of the variation in the built-in resistance in advance so that the value can be switched from a larger value to a smaller value with respect to the target (in this case, 45Ω).

  For example, in the driver circuit, Rto + Rdrv is set to be 58.33Ω at the maximum and 37Ω at the minimum. * 0.8, * 1.2, and the like are examples of variation calculation in which each variation and various dependencies are added. In the standard, the optimum 45Ω is crossed between code 3 and code 4. However, even if the best condition is * 0.8, the worst condition is * 1.2 between code 0 and code 1. Also, an optimum value can be found between code 6 and code 7.

  It can be seen that even when the standard value is set to 45Ω ± 5Ω, it is possible to adjust for a variation of ± 20% of the built-in resistance.

  After all, Vt1 ≒ Vto2, Ito, etc., are controlled so that Vr1 ≒ Vto1 is equal, and consequently, such intermediate variables as Vref, such that the exact resistance ratio and the final result are equal to each other. It can be understood that this is only an intermediate variable of the control system, and the direct influence is excluded.

  What is important is that although not shown in detail, it is very insensitive to Vref, offset of the operational amplifier OP1, variation in current, and the like. The resistance ratio between R1 and Rto needs to be accurate. However, if they are arranged close to each other in an LSI with a certain area or more, the relative accuracy of ± 0.5% or less can be easily obtained. Can be realized.

  FIG. 3 shows the result of circuit simulation using SPICE.

  The figure shows a simulation in which Rto_trim is linearly varied from 37Ω to 58.33Ω with the vertical axis taking Vto1−Vr1 as the input of the comparator CMP and the horizontal axis taking time from 0 to 10 μs. The result. Even if the above-described variation range is combined 100 times by the Monte Carlo method, all the lines except the lower two lines cross the 0V line, which indicates that the adjustment is possible.

  FIG. 4 shows an embodiment of the code control circuit and the impedance simulation resistor.

  The code control circuit 13 includes, for example, a seven-stage shift register. The impedance simulation resistor Rto_trim includes the resistor R1 and seven series elements connected in parallel to the resistor R1. Each series element includes a resistor R and a switch SW.

  The resistance values of the resistors R and R1 are Rtrm, and the resistance value when the switch is on is Rsw. Hereinafter, Rsw is set to zero.

  In this case, the number of code control signals (code values) is eight, for example, 0 to 7. That is, when all the output signals a, b,... G of the code control circuit 13 are “L” (= “0”), for example, the code value becomes 0, and all the switches SW are turned off. , The resistance value of the impedance simulation resistor Rto_trim is Rtrm.

  When one of the output signals a, b,... G of the code control circuit 13 is “H” (= “1”), for example, the code value becomes 1, and one switch SW is turned on. In this state, the resistance value of the impedance simulation resistor Rto_trim becomes Rtrm / 2.

  As described above, with respect to the output signals a, b,... G of the code control circuit 13, the resistance value of the impedance simulated resistor Rto_trim is changed from Rtrm to Rtrm / in accordance with the number (k) of signals that become “1”. It changes within the range up to (k + 1).

  In the circuit of this example, the comparator CMP of FIG. 1 keeps outputting “1” under the condition of Vto1> Vr1. “1” output from the comparator CMP is sequentially shifted in the shift register in synchronization with the clock signal CLK. That is, when Vto1> Vr1, the number of output signals a, b,... G of the code control circuit 13 that become “1” gradually increases (ups).

  Specifically, the code value gradually increases, the number of switches SW in the ON state gradually increases, and the resistance value of the impedance simulation resistor Rto_trim gradually decreases.

  When Vto1 <Vr1, the comparator CMP of FIG. 1 outputs “0”. This “0” is sequentially shifted in the shift register in synchronization with the clock signal CLK. After that, when a certain period elapses and the first input “1” is output from the last shift register, the code value decreases, the number of switches SW in the ON state decreases, and the resistance value of the impedance simulation resistor Rto_trim is reduced. Rises.

Thereafter, the code value repeatedly switches between a code value having a relationship of Vto1> Vr1 and a code value having a relationship of Vto1 <Vr1 (periodic transition). Note that this is the case where the code value transitions with a 1-bit width (between two code values), and if the code value transitions with a 2-bit width (between three code values), the code value is , Between the code value satisfying the relationship of Vto1 ≧ Vr1 and the code value satisfying the relationship of Vto1 ≦ Vr1 are repeatedly switched back and forth. In this manner, the code value is fixed to the optimum value. In a state where all the shift registers are “1”, that is, in a state where all the resistors R are electrically connected in parallel to the resistor R1, if Vto1 ≧ Vr1, the code is immediately determined in that state (maximum value 7). ). If all the shift registers are “0”, that is, only the highest resistance value (the resistance value of the resistor R1), if Vto1 ≦ Vr1, the code is immediately determined in this state (minimum value 0).

The state of this adjustment is shown in the operation waveform diagram of FIG.
The figure shows a state where the states are coming and going.

3. Second embodiment
FIG. 6 shows an impedance adjustment circuit according to the second embodiment of the present invention.

  This embodiment relates to an input impedance adjustment circuit 14. This circuit does not require a driver simulated resistor and the driver itself as compared with the output impedance adjusting circuit described above, and simply adjusts the input impedance by trimming the resistor and using the obtained code.

  The circuit operation is the same as the operation in the first embodiment, and a description thereof will be omitted.

4. Third embodiment
FIG. 7 shows an impedance adjustment circuit according to the third embodiment of the present invention.

  This embodiment relates to an input / output impedance adjustment circuit. This circuit has an output impedance trimming section 12 and an input impedance trimming section 14. In this case, one common bias unit 11 can be shared by the input impedance trimming unit 12 and the output impedance trimming unit 14.

  The circuit operation is the same as the operation in the first embodiment, and a description thereof will be omitted.

5. Fourth embodiment
FIG. 8 shows an impedance adjustment circuit according to the fourth embodiment of the present invention.
This embodiment relates to a resistance adjusting circuit.

  In the method shown in the second example of the related art, impedance adjustment is performed by connecting resistors R1 to R8 having the same resistance value in parallel with the resistor R0. However, this method has problems such as an increase in the number of codes and an increase in the range from high resistance to low resistance when the variation tolerance is widened.

  In this embodiment, since the relationship between the cord and the resistance value is an S-shaped curve or a polygonal curve, the impedance can be adjusted with a small cord even in a wide range of variation.

  Specifically, for example, the resistor R0 in the second example of the related art is 55Ω, the resistors R1 and R2 are 67Ω, the resistors R3, R4, and R5 are 100Ω, the resistor R6 is 42Ω, and the resistor R7 is 33Ω. In this way, a difference between the resistance values of the respective resistors is set, and the relationship between the code and the resistance value is defined as an S-shaped curve or a broken line curve.

  When the resistance value used for the adjustment is changed, the number of one level is detected based on the output of each stage of the multi-stage shift register, and is connected in parallel according to the number, instead of the simple switch control by the shift register. A decoding circuit for selecting a resistor may be further provided.

6. Fifth embodiment
FIG. 9 shows an impedance adjustment circuit according to the fifth embodiment of the present invention.
This embodiment relates to a resistance adjustment circuit and is an application example of the resistance adjustment described in the first embodiment.

  In an LSI, a lead frame resistance, a bonding wire resistance, a wiring resistance in a pellet, and the like that are parasitic on the package are parasitic. Therefore, when the impedance is viewed from outside the package, these resistances appear to be all connected in series. In the present embodiment, the value of the impedance simulated resistance Rtrim is adjusted in consideration of all of these parasitic resistances in advance, and the impedance is adjusted so as to have a desired impedance including all the parasitic resistances.

  For example, if the wiring resistance Rmetal is 0.5Ω, the bonding wire resistance Rbdg is 0.3Ω, and the lead frame resistance Rfrm is 0.2Ω, the resistance of the entire current path from the power supply pin to the output pin of the buffer becomes 2 × (0.5Ω + 0.3Ω + 0.2Ω) = 2Ω.

  In such a case, the impedance simulation resistor Rtrim may be adjusted to a desired resistance value, for example, 43Ω, which is lower than 45Ω by about 2Ω. However, it is too complicated for the circuit to switch the impedance simulation resistor Rtrim around this 43Ω.

  In this embodiment, the adjustment range of the impedance simulation resistor Rtrim can be shifted by switching the resistor R1.

  If Rext: R1 = Rtrim: Rt and Rtrim should be changed from 45Ω to 43Ω for adjustment, R1 should be increased by a ratio of 45/43. In this case, an LSI pattern may be prepared in advance so that R1 can be switched in consideration of all expected parasitic resistances, and R1 may be increased or decreased. Switching is performed by a method such as switching an analog switch or a metal layer by a master slice.

  FIG. 10 and FIG. 11 show examples of the resistance change with respect to the code when the impedance simulated resistance Rtrim is switched in consideration of the parasitic resistance.

  As shown in these figures, when the parasitic resistance is small, the impedance simulation resistance Rtrim1 can be switched around a larger value, for example, 43Ω. When the parasitic resistance is large, The impedance simulation resistor Rtrim2 can be switched around a smaller value, for example, 40Ω.

  According to this embodiment, even if the package changes, the impedance can be kept constant.

7. Sixth embodiment
Next, an impedance adjustment circuit according to a sixth embodiment of the present invention will be described.

  This embodiment is a modification of the above-described fifth embodiment. That is, in FIG. 9, the value of the high-precision resistor Rext does not necessarily need to be determined as one value. For example, when the resistance value of the high precision resistor Rext is 12 kΩ, the resistance value of the resistor R1 is set to 2.4 kΩ. When the resistance value of the high precision resistor Rext is 13 kΩ, the resistance value of the resistor R1 may be increased from 2.4 kΩ by (13/12) × 2.4 kΩ. That is, it becomes 2.6 KΩ.

  Although the description of the circuit operation is omitted, the relationship of Rext: R1 = Rtrim: Rt is maintained.

  Thus, even if the value of the high-precision resistor Rext is changed, the impedance can be kept constant.

8. Seventh embodiment
Next, an impedance adjustment circuit according to a seventh embodiment of the present invention will be described.

  This embodiment is a combination of the fifth and sixth embodiments. As described above, when the fifth and sixth embodiments are combined, it is possible to correct the resistance value of the high-precision resistor Rext and the resistance values of various resistors parasitic on the package by switching the resistance value of the resistor R1. it can. That is, even if the value of the high-precision resistor Rext is changed or the type of the package is changed, the impedance can be kept constant.

9. Eighth embodiment
Next, an impedance adjustment circuit according to an eighth embodiment of the present invention will be described.

  This embodiment relates to a countermeasure when the internal reference voltage Vref deviates from a desired value in the above-described fifth embodiment. For example, it is assumed that the target of the internal reference voltage Vref is 1.2 V and the high precision resistor Rext is 12 KΩ. At this time, the current flowing through the high-precision resistor Rext is Vref / Rext = 100 μA.

  Here, the internal reference voltage Vref may deviate from 1.2 V due to a change in the manufacturing process or the like. Assuming that the internal power supply voltage Vref becomes 1.25 V, the current flowing through the high-precision resistor Rext becomes 125 μA, and Vr2 also increases as the voltage drop of the resistor R1 increases.

  In such a case, the resistor R1 is divided into two parts, and the middle point is set as Vr1 and connected to the minus input terminal of the operational amplifier OP1. Then, of the two parts (under R1) connected to the high-precision resistor Rext, the potential difference of 1.25 V-1.2 V = 0.05 V is absorbed. Further, of the two portions of the resistor R1, the portion (on R1) connected to the output terminal of the operational amplifier OP1 has a resistance value that satisfies the relationship of Rext: (R1 lower + R1) = Rtrim: Rt.

  As described above, according to the present embodiment, even if the internal reference voltage Vref varies, the operating current is always kept constant, so that Rtrim can be adjusted with high accuracy.

10. Ninth embodiment
Next, an impedance adjustment circuit according to a ninth embodiment of the present invention will be described.

(1) Assumption
According to the impedance adjustment circuit described above, impedance matching such as output impedance, input impedance, and terminating resistance is performed, signal reflection is suppressed, high-quality serial signals can be transferred with high quality, and such trimming is improved. It can be done accurately and automatically.

  However, for example, in the output impedance adjustment circuit shown in FIG. 1, the output impedance is trimmed by using the output signal of the code control circuit 13 as it is. Therefore, for example, as shown in FIG. 12, when the value of Vto1 becomes close to Vr1, the value of Vto1 repeatedly fluctuates up and down around Vr1.

  As a result, the value of the output impedance simulated resistor Rto_trim of the output impedance adjustment circuit of FIG. 1 is constantly fluctuating during the trimming of the output impedance, and there is a concern that the fluctuation may affect the circuit operation. .

  Similarly, for example, also in the input impedance adjustment circuit shown in FIG. 6, since the input impedance is trimmed using the output signal of the code control circuit 13 as it is, the same phenomenon as the phenomenon shown in FIG. A situation occurs in which the value of Vti1 is not constant. As a result, the value of the input impedance simulated resistor Rti_trim of the input impedance adjustment circuit of FIG. 6 also fluctuates during the trimming of the input impedance.

  Further, when the value of Vto1 fluctuates in a 2-bit width around Vr1, for example, as shown in FIG. 12, when the value of Vto1 reciprocates between “2” and “4” , Vto1 is “3”, the value of Vto1 is closest to Vr1. Therefore, in such a case, the code value for controlling the impedance is fixed to the center value of the variation range of the value of Vto1, that is, the code value when the value of Vto1 becomes "3". It can be carried out. The same can be said for the value of Vti1.

  Therefore, in consideration of the above, when Vto1 or Vti1 reaches the vicinity of the target value Vr1, the values of the input / output impedance simulated resistors Rto_trim and Rti_trim, specifically, the output signal of the code control circuit 13, It is understood that the value should be fixed to a predetermined value.

  Meanwhile, as an impedance adjustment circuit that latches the value of the output signal of the code control circuit, there is one disclosed in Patent Document 4, for example.

  FIG. 13 shows a main part of the impedance adjustment circuit disclosed in Patent Document 4.

  Although the description of the details of this circuit will be omitted, first, unlike the impedance adjustment circuit according to the example of the present invention, the circuit is provided inside the chip without using an external resistor. Secondly, the current source 215 trims the impedance, and secondly, when the value of Vtarget approaches Vref, the thermal code C1i corresponding to the code of the impedance adjustment circuit according to the example of the present invention is fixed. is there.

  However, in the impedance adjusting circuit disclosed in Patent Document 4, for example, as shown in the timing chart of FIG. 14, when the value of Vtarget is larger than Vref, the U / D signal becomes “H” and Vtarget is set. Of the U / D signal becomes "H" twice, that is, when the U / D signal becomes "H" twice, that is, when the U / D signal becomes "H" twice. The control circuit 211 detects the time point of change to, and sets COMPLETE to “H”, thereby fixing the value of the thermal code C1i in the register 213.

  Therefore, this impedance adjusting circuit has a problem in that the time from when the value of Vtarget comes close to Vref to when the value of the thermal code C1i is fixed is long (response is poor).

  Also, for example, as shown in the timing chart of FIG. 15, when the value of Vtarget fluctuates in a 2-bit width around Vref, ideally, as described above, the code value for impedance adjustment is , Vtarget is fixed to the value when it is at the center value of the fluctuation range, it is possible to perform highly accurate trimming.

  However, in the impedance adjustment circuit disclosed in Patent Document 4, as described above, after detecting the second change point of the U / D signal from “H” to “L”, COMPLETE is set to “H”. To fix the value of the thermal code C1i. Therefore, when COMPLETE is set to “H”, the value of Vtarget is at a position shifted from the center value (Vref) of the fluctuation range, and as a result, high-precision trimming cannot be performed.

  Therefore, in the ninth embodiment described below, when Vto1 or Vti1 reaches the vicinity of the target value Vr1, the code value for impedance adjustment is changed to the value where Vto1 or Vti1 is closest to Vr1. (When Vto1 or Vti1 fluctuates in a 2-bit width centering on Vref, an impedance adjustment circuit that fixes the value at the time when Vto1 = Vr1 or Vti1 = Vr1) is proposed.

(2) Circuit example 1
FIG. 16 shows a circuit example 1 of the impedance adjustment circuit according to the ninth embodiment of the present invention.

  Rdrv (symbol △) represents an output driver.

  The common bias unit 11 includes a built-in variable resistor R1a and a highly accurate external resistor Rext connected via the node Vr1, an operational amplifier OP1 to which the internal reference voltage Vref and the voltage of the node Vr1 are input, P-channel MOS transistors P1a and P1b, And an N-channel MOS transistor N1. The P-channel MOS transistors P1a and P1b connected to the power supply VDD are bias generation circuits for generating a constant current bias and are accessory circuits.

  Note that the operation and calculation example of the common bias unit 11 are the same as those of the common bias unit shown in FIG. 1, and thus description thereof is omitted here.

  The output impedance trimming unit 12 includes a comparator CMP to which the voltage Vr1 and the voltage Vto1 are input, an operational amplifier OP2 to which the voltage Vr2 and the voltage Vto2 are input, a code control circuit 13 to receive an output signal of the comparator CMP, and an N-channel MOS transistor (current control). Element) N2, built-in resistor Rto, output impedance simulation resistor Rto_trim, and output driver simulation resistor Rdrv.

The operational amplifier OP2 controls the gate voltage of the N-channel MOS transistor N2 so that the voltage Vto2 becomes equal to the voltage Vr2. In this state, the voltage Vto1 is a divided voltage between Rto and (Rto_trim + Rdrv). What is important is that the ratio between Rext and R1 is equal to the ratio between Rto_trim + Rdrv and Rto.
Rext: R1 = (Rto_trim + Rdrv): Rto
The external resistance Rext is highly accurate. For this reason, even if the values of the built-in resistors R1, Rto, Rto_trim, and Rdrv vary, the value of Rto_trim + Rdrv can be accurately adjusted to a standard value if manufactured so that the relative accuracy between R1 and Rto is improved. It can be within the range of values.

  The code control circuit 13 includes, for example, a multi-stage shift register. The output of the comparator CMP, which is the result of comparison between Vr1 and Vto1, is input to a multi-stage shift register that shifts with the clock signal CLK. The code is extracted from each stage of the shift register, and the resistance is switched. In switching the resistance, for example, the one shown in the second example of the prior art can be used.

  In this state, Vto1 gradually approaches the target value Vr1 in synchronization with the clock signal CLK. When the magnitude relationship between Vr1 and Vto1 changes repeatedly, that is, when the value of Vto1 moves up and down around Vr1, the code control circuit 13 sets Rto_trim + Rdrv to the maximum standard value. Output code that is close.

  The operation and the calculation example of the output impedance trimming unit 12 are not significantly different from those of the output impedance trimming unit illustrated in FIG. 1, and thus description thereof is omitted here.

  The code flattening unit 15 has a code flattening circuit 16.

  The code flattening circuit 16 receives an output signal (code value) of the code control circuit 13. When Vto1 is constantly changing in one direction (for example, the plus direction) toward Vr1, the code flattening circuit 16 outputs the output signal of the code control circuit 13 as the output signal SEL as it is. When Vto1 becomes closest to Vr1, the code flattening circuit 16 fixes the output signal (code value) of the code control circuit 13 when Vto1 becomes closest to Vr1. The output code value is output as the output signal SEL.

  FIG. 17 shows a circuit example of the code flattening circuit.

  The register 17 latches a code control signal (code value) output from the code control circuit 13 in FIG. The down detection signal DOWN is input to the register 17, and when the down detection signal DOWN becomes “H”, the register 17 latches the code control signal.

  The down detection signal generation circuit 18 fetches, for example, the up / down signal UP / DOWN of FIG. 4 in synchronization with the clock signal CLK, and outputs a down detection signal DOWN based on the up / down signal UP / DOWN. .

  Here, in the example of FIG. 4, when Vto1 is larger than Vr1, the up / down signal UP / DOWN becomes “H” (= “1”), and when Vto1 is smaller than Vr1, the up / down signal The circuit configuration is such that the signal UP / DOWN becomes “L” (= “0”).

  However, in the examples of FIG. 16 and FIG. 17, since it is considered that Vto1 is gradually increased from the condition of Vto1 <Vr1, the example of FIG. 4 is modified so that when Vto1 is smaller than Vr1, the up / When the down signal UP / DOWN becomes "H" (= "1") and Vto1 is larger than Vr1, the up / down signal UP / DOWN becomes "L" (= "0"). Note that such a circuit configuration can be easily realized by modifying the comparator CMP.

  In this example, when the value of Vto1 is smaller than Vr1, the up / down signal UP / DOWN becomes “H” (up). This indicates that the value of Vto1 is currently increasing toward Vr1, so that the down detection signal DOWN remains “L”.

  On the other hand, the up / down signal UP / DOWN becomes “L” (down) when the value of Vto1 becomes larger than Vr1. This indicates that the value of Vto1 has reached near Vr1 and has exceeded Vr1. Therefore, thereafter, since it is necessary to lower Vto1, the down detection signal DOWN is set to "H".

  At the time of impedance trimming, the value of Vto1 gradually increases toward the target value Vr1 as described above.

  Naturally, as a modified example, when the value of Vto1 gradually decreases toward the target value Vr1, the down detection signal generation circuit 18 outputs a signal to the up detection signal generation circuit that detects that Vto1 has increased. It is also possible to change it (in this case, the configuration of FIG. 4 can be used as it is).

  The multiplexer (MUX) 19 selects and outputs one of the output signal (code control signal) of the code control circuit 13 and the output signal of the register 17 in FIG. 16 based on the value of the down detection signal DOWN. .

  That is, when the down detection signal DOWN is “L”, the multiplexer (MUX) 19 selects and outputs the output signal (code control signal) of the code control circuit 13 in FIG. When the down detection signal DOWN is “H”, the multiplexer (MUX) 19 selects and outputs the output signal of the register 17.

  For example, once the down detection signal DOWN once becomes “H”, the multiplexer (MUX) 19 always selects and outputs the output signal of the register 17 thereafter.

  The bit transition monitoring circuit 20 constantly monitors a code control signal (code value), in other words, a bit value (code value). When the bit value changes to a maximum value, for example, the bit value changes from “0” to “7”, when the bit value becomes “7”, a predetermined value, for example, “6” is set as the bit value. Output.

  At this time, the bit transition monitoring circuit 20 outputs a control signal CT for controlling the operation of the multiplexer (MUX) 21 so that the multiplexer (MUX) 21 selects the output signal of the bit transition monitoring circuit 20.

  The bit transition monitoring circuit 20 is provided mainly based on a user's request, and may be omitted.

  Next, the operation of the output impedance adjustment circuit of FIGS. 16 and 17 will be described.

  First, based on the timing chart of FIG. 18, a case where the value of Vto1 periodically transitions up and down with one bit width near Vr1 will be described.

  In the initial state, the value of Vto1 is far away from the target Vr1. For this reason, the value of Vto1 gradually increases in synchronization with the clock signal CLK. Here, in order to make the description easy to understand, the value of Vto1 is represented by 0 to 7 corresponding to the code control signal (code values 0 to 7) output from the code control circuit 13.

  In such a situation, since the value of Vto1 is constantly rising, the down detection signal generation circuit 18 keeps, for example, “L” as the value of the down detection signal DOWN. At this time, the register 17 does not latch the code control signal, and the multiplexer (MUX) 19 selects and outputs the code control signal from the code control circuit 13.

  Further, since the value of the code control signal is not the maximum value, the bit transition monitoring circuit 20 controls the multiplexer 21 so that the multiplexer 21 selects and outputs the output signal of the multiplexer 19.

  When the value of Vto1 becomes close to Vr1, the value of Vto1 repeats vertical fluctuations around Vr1. For example, in the example of FIG. 18, the value of Vto1 reciprocates between “3” and “4”. That is, the value of Vto1 fluctuates by 1 bit width around Vr1.

  Here, when the value of Vto1 becomes larger than Vr1, the code control circuit 13 outputs “L” (= “0”) as the up / down signal UP / DOWN. When detecting that the up / down signal UP / DOWN has become "L", the down detection signal generation circuit 18 in the code flattening circuit 16 determines that the value of Vto1 goes down, and the down detection signal DOWN. To “H”.

  Note that the down detection signal generation circuit 18 may be configured to output a down signal (pulse signal) DOWN when detecting a down edge of Vto1 (change from “4” to “3”). Good.

  Upon receiving the first down detection signal DOWN, the register 17 latches "3" as a code control signal, and thereafter does not accept an input signal. At the same time, the multiplexer 19 selects and outputs the output signal of the register 17, and thereafter continuously selects and outputs the output signal of the register 17.

  As described above, when the value of Vto1 becomes close to Vr1, the code flattening circuit 16 fixes the code control signal (code value) to the value when the value of Vto1 is closest to Vr1, in this example, “3”. I do. Therefore, according to the present example, when performing high-precision trimming, the resistance value (code value) of the resistor Rto_use for adjusting the actual output impedance can be fixed to the optimum value at high speed, so that it can be used for other circuits. It is not necessary to consider the influence.

  In this example, when the value of Vto1 becomes close to Vr1 and the value of Vto1 repeatedly changes up and down around Vr1, the code is flattened by detecting the first down edge of Vto1. The output signal (code control signal) SEL of the circuit 16 is fixed. As described above, the output signal SEL of the code flattening circuit 16 is fixed at an optimum value at high speed.

  In this example, when Vto1 (= “3”) <Vr1, the output signal (code control signal) SEL of the code flattening circuit 16 is fixed, as shown in the timing chart of FIG. Alternatively, when Vto1 (= "4")> Vr1, the output signal (code control signal) SEL of the code flattening circuit 16 may be fixed.

  Next, a case where the value of Vto1 periodically transitions up and down with a 2-bit width near Vr1 will be described with reference to the timing chart of FIG.

  In the initial state, as described above, the value of Vto1 gradually increases in synchronization with the clock signal CLK. In such a situation, since the value of Vto1 is constantly rising, the down detection signal generation circuit 18 keeps, for example, “L” as the value of the down detection signal DOWN. At this time, the register 17 does not latch the code control signal, and the multiplexer (MUX) 19 selects and outputs the code control signal from the code control circuit 13.

  Further, since the value of the code control signal is not the maximum value, the bit transition monitoring circuit 20 controls the multiplexer 21 so that the multiplexer 21 selects and outputs the output signal of the multiplexer 19.

  When the value of Vto1 becomes close to Vr1, the value of Vto1 repeats vertical fluctuations around Vr1. For example, in the example of FIG. 20, the value of Vto1 reciprocates between “2” and “4”. That is, the value of Vto1 fluctuates in a 2-bit width around Vr1.

  Here, when the down detection signal generation circuit 18 in the code flattening circuit 16 detects that the up / down signal UP / DOWN becomes “L” (down) and thereafter the value of Vto1 goes down, the down detection signal generation circuit 18 goes down. The detection signal DOWN is set to “H”.

  As described above, when the down detection signal generation circuit 18 detects the down edge of Vto1 (change from “4” to “3” and change from “3” to “2”), The down signal (pulse signal) DOWN may be configured to be output.

  Upon receiving the first down detection signal DOWN, the register 17 latches "3" as a code control signal, and thereafter does not accept an input signal. At the same time, the multiplexer 19 selects and outputs the output signal of the register 17, and thereafter continuously selects and outputs the output signal of the register 17.

  As described above, when the value of Vto1 becomes close to Vr1, the code flattening circuit 16 fixes the code control signal (code value) to the value when the value of Vto1 is closest to Vr1, in this example, “3”. I do. Therefore, when performing high-precision trimming, the resistance value (code value) of the resistor Rto_use for adjusting the actual output impedance can be fixed at a high speed, so that the influence on other circuits does not need to be considered.

  Also in this example, the output signal (code control signal) SEL of the code flattening circuit 16 is fixed by detecting the first down edge of Vto1 for the first time. As described above, the output signal SEL of the code flattening circuit 16 is fixed at an optimum value at high speed.

  Further, in this example, since the value of Vto1 fluctuates in a 2-bit width centering on Vr1, the code flattening circuit 16 outputs the output signal when Vto1 (= "3") = Vr1. (Code control signal) SEL is fixed. Thus, in this example, the output impedance can be trimmed with high accuracy.

  FIG. 21 shows a timing chart when the value of Vto1 reaches the maximum value “7”. At this time, the bit transition monitoring circuit 20 forcibly sets the output signal SEL of the code flattening circuit 16 to a predetermined value, "6" in this example, regardless of the code control signal from the code control circuit 13. Output.

(3) Circuit example 2
FIG. 22 shows a circuit example 2 of the impedance adjustment circuit according to the ninth embodiment of the present invention.

  Circuit example 2 relates to an input impedance adjustment circuit. This circuit does not require a driver simulated resistor and the driver itself as compared with the output impedance adjusting circuit described above, and simply adjusts the input impedance by trimming the resistor and using the obtained code.

  Except for the above points, the input impedance trimming section 14 does not differ greatly from the output impedance trimming section 12 of FIG. The code flattening circuit 16 'of the code flattening unit 15' is the same as the code flattening circuit 16 of the code flattening unit 15 in FIG.

  The operation of the circuit is the same as the operation of the impedance adjustment circuit in the first embodiment, and will not be described here.

(4) Circuit example 3
FIG. 23 shows a third circuit example of the impedance adjustment circuit according to the ninth embodiment of the present invention.

  Circuit example 3 relates to an input / output impedance adjustment circuit. This circuit has an output impedance trimming section 12 and an input impedance trimming section 14. In this case, one common bias unit 11 can be shared by the input impedance trimming unit 12 and the output impedance trimming unit 14.

  The output impedance trimming unit 12 and the code flattening unit 15 are the same as the output impedance trimming unit 12 and the code flattening unit 15 in FIG. The input impedance trimming unit 14 and the code flattening unit 15 'are the same as the input impedance trimming unit 14 and the code flattening unit 15' of FIG.

  The operation of the circuit is the same as the operation of the impedance adjustment circuit in the first embodiment, and will not be described here.

10. Conclusion
As described in the first to ninth embodiments, the impedance adjustment circuit according to the example of the present invention has the following effects.

-It can be manufactured in a normal process of a CMOS LSI.
-Only one external resistor is required, which is advantageous in cost.
-The impedance can be kept constant even when the value of the external high-precision resistor is changed.
-The impedance can be kept constant even if the package changes, the LSI layout changes, or the parasitic resistance changes.

・ It is easy to increase the number of adjustment codes, and adjustment with higher precision can be easily realized.
・ Since the output impedance is adjusted including the driver, it can be performed with high accuracy.
-The manufacturing yield can be easily increased even for a wider range of variation.
-Since circuit elements can be disassembled, they can be easily shared and the area can be reduced.

  -The resistance value of the resistance element used inside the LSI can be dynamically determined.

  By providing a resistance element having a high-precision resistance value outside the LSI, the resistance value of the resistance element used inside the LSI can be determined with high accuracy.

  The value (code value) of the code control signal for impedance trimming is immediately fixed to the most optimal value based on the first down detection signal DOWN. Thus, the optimum resistance value of the resistance element used for impedance trimming can be determined at high speed. Thereafter, by keeping the resistance value fixed, the influence on other circuits can be reduced.

  In particular, when Vto1 fluctuates with respect to Vr1 in a 2-bit width, impedance trimming can be performed using the code value (resistance value) at which Vto1 becomes equal to Vr1. In addition, highly accurate trimming becomes possible.

  The basic elements of the present invention for realizing such effects are as shown in FIG. 24 or FIG. The concept of the present invention is to realize Rtrim closest to the relationship of Rext: R1 = Rtrim: Rt with respect to the resistance value of each resistance element.

It goes without saying that the following modifications are possible within the scope of this concept.
-To enhance the output current of the power amplifier, connect a P-channel MOS transistor (current driver) to the power supply terminal VDD.
Similarly, the source follower of the N-channel MOS transistor is connected to the power supply terminal VDD.
The resistance R1 is formed in the LSI such that the resistance value of the resistance R1 can be changed according to the resistance value of the external resistance Rext.

・ The code control circuit should be composed of latches and coders, not multi-stage shift registers.
-The possible states of the code signal must be adjusted according to the relationship between the adjustable range and the adjustment accuracy.
In order to improve the relative accuracy between the resistor R1 and the resistor Rt, unit resistors having the same shape should be arranged close to each other in the LSI.

The relation between the reference voltage Vref and the power supply voltage VDD is kept constant, and the relation between the power supply voltage VDD and the ground voltage VGND of the entire circuit is reversed.
Adjusting the resistance Rt instead of adjusting the value of the resistance R1 according to the value of the external resistance Rext and the parasitic resistance.
A certain ratio is provided between the feedback system resistor Rtrim and the actual impedance-adjusted circuit (output driver section, input resistor section, etc.).

  If the code control circuit outputs a code that goes down gradually, replace the down detection signal generation circuit in the code flattening circuit with an up signal generation circuit.

  The example of the present invention is not limited to the above-described embodiment, and can be embodied by modifying the components without departing from the gist of the invention. In addition, various inventions can be configured by appropriately combining a plurality of constituent elements disclosed in the above embodiments. For example, some components may be deleted from all the components disclosed in the above-described embodiments, or components of different embodiments may be appropriately combined.

  The impedance adjustment circuit according to the example of the present invention is applied to all types of semiconductor integrated circuits that are required to perform impedance matching such as output impedance, input impedance, and termination resistance.

FIG. 2 is a diagram illustrating an impedance adjustment circuit according to the first embodiment. The figure which shows the relationship between a code and output impedance. The figure which shows the simulation result by SPICE. The figure which shows the example of a code control circuit and an impedance simulation resistor. The figure which shows the operation waveform at the time of impedance adjustment. FIG. 9 is a diagram illustrating an impedance adjustment circuit according to a second embodiment. FIG. 13 is a diagram illustrating an impedance adjustment circuit according to a third embodiment. FIG. 14 is a diagram illustrating a relationship between a code and an output impedance according to the fourth embodiment. FIG. 14 is a diagram illustrating an impedance adjustment circuit according to a fifth embodiment. The figure which shows the relationship between a code and the resistance value of an impedance simulation resistor. The figure which shows the relationship between a code and the resistance value of an impedance simulation resistor. 2 is a timing chart showing the operation of the circuit of FIG. The figure which shows the impedance adjustment circuit as a reference example. 14 is a timing chart showing the operation of the circuit of FIG. 14 is a timing chart showing the operation of the circuit of FIG. FIG. 19 is a diagram illustrating an output impedance adjustment circuit according to a ninth embodiment. FIG. 3 is a diagram illustrating an example of a code flattening circuit. 17 is a timing chart showing the operation of the circuit in FIG. 17 is a timing chart showing the operation of the circuit in FIG. 17 is a timing chart showing the operation of the circuit in FIG. 17 is a timing chart showing the operation of the circuit in FIG. The figure which shows the input impedance adjustment circuit concerning 9th Embodiment. The figure which shows the input / output impedance adjustment circuit concerning 9th Embodiment. FIG. 2 is a diagram showing basic elements of an impedance adjustment circuit according to an example of the present invention. FIG. 2 is a diagram showing basic elements of an impedance adjustment circuit according to an example of the present invention. The figure which shows the conventional impedance adjustment circuit. The figure which shows the conventional impedance adjustment circuit. The figure which shows the conventional impedance adjustment circuit. FIG. 9 is a diagram illustrating an example of a conventional trimming resistor. FIG. 4 is a diagram illustrating a relationship between a code and a resistance value of a trimming resistor. The figure which shows the conventional impedance adjustment circuit.

Explanation of reference numerals

  11: common bias section, 12: output impedance trimming section, 13: code control circuit, 14: input impedance trimming section, P1: P-channel MOS transistor, N1, N2: N-channel MOS transistor, OP1, OP2: operational amplifier, CMP: Comparators, R1, Rto, Rti: built-in resistors, Rext: external high-precision resistors, Rto trim, Rti trim: impedance simulated resistors.

Claims (19)

A first series circuit in which a first internal resistor and an external resistor are connected in series via a first node, an internal reference voltage is input to a first input terminal, and a second input terminal is connected to the first node; A common bias unit having an output terminal and a first operational amplifier connected to the first series circuit;
A second series circuit in which a second built-in resistor and an impedance simulation resistor are connected in series via a second node; a first input terminal connected to the first node; and a second input terminal connected to the second node And a code control circuit that latches an output signal of the comparator with a clock signal and outputs one of a plurality of switching codes.
An output terminal of the first operational amplifier is also connected to the second series circuit,
An impedance adjustment circuit, wherein one of the plurality of switching codes is used to switch a resistance value of the impedance simulation resistor and a resistance value of a target impedance adjustment resistor to be actually subjected to impedance adjustment. The impedance adjustment circuit according to claim 1, further comprising:
A code flattening unit including a code flattening circuit that latches one of the plurality of switching codes output from the code control circuit,
The impedance adjustment circuit, wherein the code flattening circuit fixes a resistance value of the target impedance adjustment resistor based on one of the latched switching codes.   When one of the plurality of switching codes output from the code control circuit repeats a periodic transition, one of the plurality of switching codes is latched by the code flattening circuit. The impedance adjustment circuit according to claim 2, wherein:   The value of the switching code output from the code control circuit gradually increases according to the output signal of the comparator, and when the value first decreases, the code flattening circuit sets the switching code among the plurality of switching codes. 4. The impedance adjustment circuit according to claim 3, wherein one of the following is latched.   The plurality of switching codes are composed of n (n is a plurality) bits, and when the periodic transition is repeated between specific two bits, the code flattening circuit includes the two bits. 4. The impedance adjustment circuit according to claim 3, wherein any one of them is latched.   The plurality of switching codes are composed of n (n is a plurality) bits, and when the periodic transition is repeated between specific three bits, the code flattening circuit includes the three bits. 4. The impedance adjustment circuit according to claim 3, wherein an intermediate bit is latched.   3. The impedance adjustment circuit according to claim 1, wherein one or more pairs of the common bias unit and the impedance trimming unit exist.   The impedance adjustment circuit according to claim 1, wherein the impedance simulation resistor includes an output buffer.   The impedance adjustment circuit according to claim 1, wherein the impedance simulation resistor includes an input impedance, a terminating resistor, a pull-up resistor, or a pull-down resistor.   3. The impedance adjustment circuit according to claim 1, wherein a relationship between the plurality of switching codes and a resistance value of the impedance simulation resistor has a reciprocal, a broken line, or an S-shaped relationship. 4.   The resistance value of the first and second internal resistors includes a parasitic resistance parasitic on a package, a lead, or a frame, and is adjusted to shift an adjustment range of the resistance value of the impedance simulation resistor. Item 3. The impedance adjustment circuit according to item 1 or 2.   3. The device according to claim 1, wherein the external resistor is a high-precision resistor provided outside the LSI, and the resistance values of the first and second internal resistors are switched based on the value of the external resistor. The impedance adjustment circuit according to 1.   3. The impedance adjustment according to claim 1, wherein the resistance values of the first and second internal resistors are switched based on a parasitic resistance parasitic on a package and a lead frame and a value of the external resistance. 4. circuit. The first internal resistor is composed of first and second resistance elements, and the first resistor is a voltage having a difference between a value of the internal reference voltage at the time of design and a value of the internal reference voltage at the time of use. And the resistance values of the first and second resistance elements are:
Rext: R1under + R1upper = Rtrim: Rt
(However, Rext is the resistance value of the external resistance, R1under is the resistance value of the first resistance element, R1upper is the resistance value of the second resistance element, Rtrim is the resistance value of the impedance simulation resistance, and Rt is , The resistance value of the second internal resistor)
3. The impedance adjustment circuit according to claim 1, wherein the impedance adjustment circuit is adjusted according to a value of the built-in reference voltage so as to satisfy the following relationship.   3. The impedance adjustment circuit according to claim 1, wherein a built-in resistor having higher accuracy than the first and second built-in resistors and the impedance simulation resistor is used instead of the external resistor. 4.   The impedance trimming unit has a second operational amplifier, a first input terminal of the second operational amplifier is connected to the first series circuit, and a second input terminal and an output terminal of the second operational amplifier are connected to the second operational amplifier. 3. The impedance adjustment circuit according to claim 1, wherein the impedance adjustment circuit is connected to a series circuit.   3. The impedance adjustment circuit according to claim 1, wherein a resistance value of the impedance simulation resistor is maintained to be a positive multiple of a resistance value of the target impedance adjustment resistor. 4.   The impedance adjustment circuit according to claim 1, wherein the impedance trimming unit is an output impedance trimming unit that trims an output impedance or an input impedance trimming unit that trims an input impedance. A first series circuit in which a first internal resistor and an external resistor are connected in series via a first node, an internal reference voltage is input to a first input terminal, and a second input terminal is connected to the first node; A common bias unit having an output terminal and a first operational amplifier connected to the first series circuit;
A second series circuit in which a second built-in resistor and an output impedance simulation resistor are connected in series via a second node; a first input terminal connected to the first node; and a second input terminal connected to the second node. An output impedance trimming unit including a first comparator connected thereto, and a first code control circuit that latches an output signal of the first comparator with a clock signal and outputs one of a plurality of first switching codes When,
A third series circuit in which a third internal resistor and an input impedance simulation resistor are connected in series via a third node; a first input terminal connected to the first node; and a second input terminal connected to the third node. Input impedance trimming comprising a connected second comparator and a second code control circuit for latching an output signal of the second comparator with the clock signal and outputting one of a plurality of second switching codes. And a part,
An output terminal of the first operational amplifier is also connected to the second and third series circuits,
Using one of the plurality of first switching codes to switch a resistance value of the output impedance simulation resistor and a resistance value of a first target impedance adjustment resistor to be actually subjected to output impedance adjustment;
The resistance value of the input impedance simulation resistor and the resistance value of a second target impedance adjustment resistor to be actually subjected to input impedance adjustment are switched using one of the plurality of second switching codes. Impedance adjustment circuit.

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