JP2004335761A - Inductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve characteristics of an inductor (on-chip inductor) in a semiconductor chip by raising high frequency characteristic value (Q factor). <P>SOLUTION: Improvement is given to the Q factor by utilizing the technology of wafer level packaging, and applying a differential inductor to a re-wiring layer so as to form inductive components in a circuit element forming region of the semiconductor chip. Thus, with the reduction of a chip area, an inductive element having high reliability and excellent high frequency characteristics can be provided at low cost. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to downsizing and performance improvement of an inductor device by a structure of a passive element built in a semiconductor device of a high frequency integrated circuit.
[0002]
[Prior art]
In recent years, with the spread of mobile phones and PDAs (Personal Digital Assistants), there has been an increasing demand for miniaturization of high-frequency circuits having a wireless interface, and these have been mounted on printed circuit boards outside semiconductor devices (external components). In many cases, passive devices such as inductors are housed in a semiconductor device.
[0003]
The resistance element and the capacitance element are relatively easy to form in a chip, but it is difficult to form an inductor, and various techniques can be adopted for a structure that causes inductiveness.
[0004]
Here, the inductor is a component that is indispensable for application to RFIC design, such as an LNA (Low Noise Amplifier), a PA (Power Amplifier), and an RF oscillator. In particular, in a VCO (voltage controlled oscillator), a pair of inductors having the same characteristics are used.
[0005]
In the following description, the layer below the protective film 5 will be described as a diffusion step in a semiconductor manufacturing process, and the metal material in the diffusion step will be described as two aluminum layers. It is possible.
[0006]
FIG. 9A is a plan view of a conventional spiral inductor formed in a semiconductor chip portion. FIG. 9B is a cross-sectional view taken along a line indicated by a one-dot chain line A-a in FIG.
[0007]
In FIG. 9B, an inductor is formed by the lead conductors 21 and 22 of the first conductor layer and the spiral inductor 4 of the second conductor layer. An electrical signal is extracted to the outside from the center of the inductor 4 by the lead conductors of the first conductor layers 21 and 22.
[0008]
In this case, the lead conductors 21 and 22 of the first conductor layer and the spiral inductor 4 of the second conductor layer use different layers because of the occurrence of intersections, and pass through the lead portions 21 and 22 of the first conductor layer. Perform electrical extraction to the left and right. The first conductor layers 21 and 22 and the second conductor layer 4 are usually formed of a metal such as aluminum.
[0009]
The advantage of this structure is that the semiconductor device can be manufactured by a conventional manufacturing process, and an inductor with less variation in shape and high accuracy can be manufactured as compared with other methods.
[0010]
Next, FIG. 10 is a view showing the shape of another conventional inductor.
[0011]
FIG. 10A is a plan view, and FIG. 10B is a cross-sectional view of the cut surface Aa described in FIG.
[0012]
In this manufacturing method, a first rewiring resin layer 6 is formed after forming a protective film 5 in a final step of a chip diffusion process in semiconductor manufacturing, and then a spiral inductor is formed by a second rewiring conductor layer 7. Usually such a process is called wafer level packaging. The first redistribution resin layer 6 is formed of a resin having a low dielectric constant and a high insulating property such as polyimide or BCB (benzocyclobutene), and the second redistribution conductor layer 7 is formed of a material having a high conductivity, for example. Made of copper.
[0013]
Here, the characteristics of the spiral inductor will be described. There is a quality (Q) factor as a characteristic of an inductor. For example, in a series resonance LC circuit, Q is determined by a value obtained by dividing an inductor value at a resonance frequency by a series resistance value of the circuit, and is expressed by the following equation.
[0014]
Q = ωL / R
Here, ω is an angular frequency, L is an inductance value, and R is a resistance value.
[0015]
The larger the Q value is, the better the electrical characteristics of the inductance component are, which contributes to lower power consumption of the circuit.
[0016]
FIG. 11 shows the Q characteristic of a general inductor.
[0017]
As shown in FIG. 11, when the frequency increases, the Q value decreases in a high frequency region due to a capacitance loss due to a capacitance value between the inductor and the substrate. In order to increase the Q value, it is effective to reduce the resistance component of the inductor and suppress the capacitance loss.
[0018]
From the above, in the case of FIG. 10 having high conductivity using copper, the resistance value is smaller and the result is better in the characteristics.
[0019]
FIG. 12 is a diagram showing a conventional inductor device. The inductor uses a differential inductor and is implemented in a conventional semiconductor process.
[0020]
Document (Non-Patent Document 1) realizes a differential inductor in a semiconductor manufacturing process.
[0021]
In this case, the Q value of the inductor is low, which is a fraction of that of the external type inductor, but in the case of this differential type inductor, it is necessary to obtain two inductors with uniform characteristics. It is intended for.
[0022]
First, a comparison between the differential inductor and the spiral inductor will be described. As can be seen from FIG. 13, the spiral inductor forms a larger conductor loop when viewed from the left side of the terminal than when viewed from the right side. Each time the loop advances, the radius of curvature of the loop becomes smaller, and the characteristic impedance differs from place to place. In other words, the electrical characteristics differ depending on the selection of the left or right terminal.
[0023]
14 and 15 show the structure of the differential inductor. The differential inductor also requires two conductor layers. FIG. 14 shows an inductor portion, and FIG. 15 shows a crossing portion of the inductor. Regarding the inductor portion shown in FIG. 14, the spiral inductor has a spiral shape that goes inward by one pitch in one round and is not a true octagon, but the differential inductor is constituted by a true octagon. Is minimized, an ideal differential inductor is completed. Therefore, it is important technology to make the intersection as small as possible. Further, the differential inductor has a symmetrical structure with respect to the terminals, and the electrical characteristics also have symmetry. In particular, in a circuit represented by a VCO or the like, two inductors having the same characteristics may be required. In order to achieve this, it is necessary to consider variations in inductors used externally to the semiconductor device in order to select an inductor having the same characteristics from many inductors.
[0024]
In this case, when the neutral point is grounded in the case of the differential inductor, it is very advantageous since two inductors having the same characteristics are built in. Further, there is an advantage that an area occupied is smaller than when two inductors built in a semiconductor device are arranged.
[0025]
FIG. 16A is a cross-sectional view of the via portion of the redistribution layer, and FIG. 16B is a plan view of the via portion of the redistribution layer. The area surrounded by oblique lines is the wiring prohibited area. A spiral inductor is formed using the redistribution layer. In a spiral inductor, a via portion can be provided at a position distant from the inductor conductor. However, in a differential inductor, the intersection is dense, so that the wiring prohibited area needs to be made as small as possible.
[0026]
In addition, the spiral inductor has one of the two terminals that has a lead from the center of the structure, and a capacitive component is generated at the intersection of the inductor and the lead, so that the component reduces the inductive component. It becomes. On the other hand, in the case of the differential type inductor, both ends of the lead portion appear in regions outside the inductor, and the long lead portion is advantageous because it does not have a structure. Therefore, most of the wiring portions all contribute to the inductive component and have efficient magnetic characteristics.
[0027]
Even when a differential inductor is used, an intersection occurs. The intersection must be as short as possible to minimize the resistance component.
[0028]
In a general semiconductor process, the lead portion uses a conductor with a higher resistance value such as aluminum than copper, so if the lead portion is long, the resistance value increases, and the spiral inductor is disadvantageous in characteristics. There is a face.
[0029]
As prior art document information relating to the invention of this application, for example, Patent Document 1 is known.
[0030]
[Patent Document 1]
Japanese Patent Application Laid-Open No. 2002-57292 [Non-Patent Document 1]
IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 36 NO. 7 JULY "Low Power Low-Phase-Noise Differentially Tuned Quadrature VCO Design in Standard CMOS (MarcTiebout)
[0031]
[Problems to be solved by the invention]
However, the thickness of the dielectric is extremely thin, for example, from 600 nm to 1000 nm, and a magnetic field component generated when the inductor circuit is operated strongly affects the surroundings, and there is a high risk that a circuit existing in the surroundings malfunctions.
[0032]
In addition, the method of mounting a spiral inductor directly on a semiconductor chip requires a place for laying the inductor in the semiconductor chip, which causes an increase in chip cost.
[0033]
In a method of forming an inductor on a resin film of a redistribution layer, which is a wafer level package, a spiral inductor is used.
[0034]
However, the Q value of the spiral inductor circuit has a limit that the Q value cannot be increased because the DC resistance component is indispensable in the structure at the lead portion.
[0035]
Also, it has been difficult to mount a differential inductor using a method of forming a spiral inductor. An example of the reason will be described below.
[0036]
As shown in FIG. 14, the differential inductor needs to arrange vias close to each other. However, it is difficult to install a differential type inductor because there is a wiring prohibited area near the via due to the design limitation of the via.
[0037]
Generally, the rewiring layer is applied by using a resin such as polyimide and masking the semiconductor via. At this time, the first redistribution resin layer 6 in FIG. 10 is removed at the via portion, and the sharpness of the edge of the removed portion is important. For this reason, a situation occurs in which another wiring portion cannot be arranged within a predetermined distance from the via portion.
[0038]
Conventionally, in a differential type inductive element using a redistribution layer, the wiring pitch and the like have been irregular due to the presence of a wiring restriction region near a via, and as a result, the frequency-dependent characteristics have been irregular.
[0039]
On the other hand, when a passive element is mounted on an external component at a position outside the semiconductor device, the inductance value may vary due to various factors, such as variations in the characteristics of the external component, the mounting direction when mounting the external component, and the amount of solder when soldering. Adjustment is required.
[0040]
In general, a passive element changes its characteristic value due to a conductor or a dielectric placed around the element. In other words, since the adjustment work is not possible before the semiconductor is mounted on the mounting printed board, the work of adjusting the circuit constants is required after the mounting of the printed board, and additional work is required. For this reason, there are many disadvantages, such as an increase in manufacturing man-hours and an increase in semiconductor manufacturing costs, such as the need for a person having knowledge of a high-frequency engineer for adjustment work.
[0041]
[Means for Solving the Problems]
In order to solve the above problem, an inductor device according to claim 1 of the present invention provides a circuit element forming layer on which a circuit element is formed, and a dielectric layer formed on a surface adjacent to the circuit element forming layer. A conductor layer formed in contact with the dielectric layer, a protective film layer covering the conductor layer and formed in contact with the dielectric layer, and a resin layer formed in contact with the protective film layer, A second conductor layer formed in contact with the resin layer; and a third conductor layer penetrating the dielectric layer and the resin layer and connecting the first conductor layer and the second conductor layer. An inductor device, wherein an inductor shape formed by the first to third layers is substantially line-symmetric with respect to the inductor terminal pair.
[0042]
Thus, the area of the chip can be reduced, and an inductive element having a high Q value can be arranged.
[0043]
Further, in the inductor device according to the second aspect, a circuit element forming layer on which a circuit element is formed, a dielectric layer formed on a surface adjacent to the circuit element forming layer, and a dielectric layer formed in contact with the dielectric layer Protective film layer, a conductor layer formed in contact with the protective film layer, a resin layer covering the conductor layer and formed in contact with the protective film layer, and a resin layer formed in contact with the resin layer. An inductor device comprising: two conductor layers; and a third conductor layer that penetrates the resin layer and connects the first conductor layer and the second conductor layer, wherein the first to third layers define The formed inductor shape is substantially line-symmetric with respect to the inductor terminal pair.
[0044]
As a result, a more reliable inductor device having a higher Q value is possible.
[0045]
Further, in the inductor device according to the third aspect, a circuit element forming layer on which a circuit element is formed, a dielectric layer formed on a surface adjacent to the circuit element forming layer, and a dielectric layer formed in contact with the dielectric layer A protective film layer, a first resin layer formed in contact with the protective film layer, a conductive layer formed in contact with the first resin layer, and a conductive layer covering the conductive layer and in contact with the first resin layer. Connecting the first conductor layer and the second conductor layer through the second resin layer, the second conductor layer formed in contact with the second resin layer, and the second resin layer. And an inductor device formed by the first to third layers is substantially line-symmetric with respect to the inductor terminal pair.
[0046]
This makes it possible to provide a highly reliable inductor device having a higher Q value.
[0047]
According to a fourth aspect of the present invention, in the inductor device of the first, second and third aspects, the connection conductor is a via having a high aspect ratio.
[0048]
Thereby, miniaturization and installation of a plurality of devices are possible.
[0049]
According to a fifth aspect of the present invention, in the inductor device according to the first, second, and third aspects, the connection conductors are interconnected by a wire.
[0050]
According to a sixth aspect of the present invention, in the inductor device of the first, second, third, fourth, and fifth aspects, a magnetic material having high magnetic permeability is disposed at the center of the differential inductor. It is characterized by having.
[0051]
The method for manufacturing an inductor device according to claim 7 is the inductor device according to claims 1 to 3, wherein the low melting point material is removed after the periphery of the columnar lamination of the low melting point material is filled with the resin layer. Forming the through-hole through
[0052]
As a result, a via having a high aspect ratio can be manufactured, and miniaturization and installation of a plurality of devices are possible.
[0053]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, a first embodiment of the present invention will be described with reference to the drawings.
[0054]
FIG. 1 is a plan view of the first embodiment of the present invention.
[0055]
The differential inductor is formed on the surface of the first redistribution layer, and the intersection of the differential inductor is formed on the first conductor layer of the semiconductor device.
[0056]
According to this method, most of the inductor is formed of copper, and the Q value can be greatly improved compared to the conventional product. The experimental results showed that the characteristics were improved about twice that of the conventional product.
[0057]
Next, an inductor device according to a second embodiment of the present invention will be described with reference to the drawings. FIG. 2A is a plan view of a second embodiment of the present invention, and FIG. 2B is a cross-sectional view taken along a dashed-dotted line Aa shown in FIG.
[0058]
In the first embodiment, the intersection of the differential inductor is made of aluminum before the protection film 5 is formed in the diffusion step. However, the present invention is based on the following. In the wafer leveling process, it is possible to wire the intersections of the inductors with copper. For this reason, the wafer leveling step and the diffusion step can be separated, and the state in which the protective film 5 is provided makes handling of the wafer easy.
[0059]
In addition, it is possible to use copper having high conductivity for all parts of the differential inductor.
[0060]
Next, an inductor device according to a third embodiment of the present invention will be described with reference to the drawings.
[0061]
FIG. 3A is a plan view of a third embodiment of the present invention. FIG. 3B is a cross-sectional view taken along a dashed-dotted line Aa shown in FIG.
[0062]
The present invention is a step of arranging a copper wiring on the second redistribution conductor layer 7 after laminating the second redistribution resin layer 9 which is a wafer level process such as polyimide or BCB on the protective film 5. This is an effective means when it is difficult to form a copper wiring on the protective film for some reason. In addition, since the differential inductor can be arranged far away from the semiconductor device and away from the circuit element forming layer 1, the influence of the magnetic field component generated by the inductor on the circuit of the semiconductor device is reduced, and noise is reduced. It is valid.
[0063]
Here, an example of laminating two layers of the rewiring resin is shown, but the same effect can be obtained if the number of laminations is two or more.
[0064]
Next, an inductor device according to a fourth embodiment of the present invention will be described with reference to FIG.
[0065]
When the first rewiring resin layer 6 or the second rewiring resin layer 9 is stacked, the edge inclination of the rewiring resin at the via 12 is important. However, if the edge inclination is as steep as possible, wiring is prohibited. The area becomes smaller, the degree of freedom in inductor design increases, and it is possible to contribute to higher density devices.
[0066]
A method for steepening the edge of the first redistribution resin layer as steeply as possible in order to minimize the wiring prohibited area of the via will be described below.
[0067]
FIG. 4 is a diagram showing a configuration in which the vicinity of the via 12 is reduced according to the thickness of the first rewiring resin layer 6. Since the wiring restriction area and the thickness of the rewiring resin layer tend to be proportional, the wiring restriction area is thereby reduced. In order to realize this shape, the rewiring resin layer laminating step is divided into at least two or more steps, and masking around the via 12 is performed in each step, and the lamination thickness of the rewiring resin layer near the via 12 is reduced. Yes, this method limits the thickness.
[0068]
Next, an inductor device according to a fifth embodiment of the present invention will be described with reference to FIG.
[0069]
FIGS. 5A to 5C show a method in which a low-melting substance 13 having the same height as the via shape is placed at the via position in advance at the location where the via exists, and after the rewiring resin layer laminating step is completed. And a method of melting and removing the low-melting substance 13. Here, the low melting point material 13 is selected so as to melt at a temperature lower than the Tg (gelation temperature) of the rewiring layer. For example, when the rewiring layer is made of polyimide, Tg is set to 300 ° C., and when the remelting substance 13 is made of solder, the temperature is set to 230 ° C.
[0070]
In FIG. 5, a similar effect can be obtained by using a substance that can be washed away by a chemical treatment after the rewiring resin layer laminating step is completed instead of the low melting point substance 13.
[0071]
According to the above method, the pitch of the conductors of the spiral inductor can be reduced, and a higher-density spiral inductor can be formed.
[0072]
FIG. 6A is a plan view of a fifth embodiment of the present invention. FIG. 6B is a cross-sectional view taken along the dashed-dotted line Aa shown in FIG. FIG. 7 is a partially enlarged view of the dashed line in FIG. 6B. Electrical connection is made to the second redistribution conductor layer 7 laid on the first redistribution resin layer 6 by the metal wires 10 by direct wire bonding. In addition, it is preferable to apply, for example, gold plating or gold flash plating to the bonding region in advance in order to secure the connection strength at the time of wire bond connection. According to this embodiment, it is not necessary to prepare a new wiring layer in order to realize the intersection of the differential inductors, and the number of steps can be reduced.
[0073]
Next, an inductor device according to a sixth embodiment of the present invention will be described with reference to the drawings. FIG. 8A is a plan view of the sixth embodiment of the present invention. FIG. 8B is a cross-sectional view taken along the dashed-dotted line Aa shown in FIG. As shown in FIG. 8A, the structure is such that a magnetic film 11 is provided at or near the center of the differential inductor. The magnetic film 11 can be formed of a ferromagnetic material, or can be formed by kneading a ferromagnetic material or a soft magnetic material with a resin. When the magnetic film 11 is provided at or near the center of the differential inductor as described above, a strong inductive component is generated. As a result, the size of the inductive element can be reduced, and the induction characteristics can be improved. it can.
[0074]
Further, the magnetic flux is concentrated on the magnetic film, and as a result, noise due to the operation of the differential inductor can be reduced, and a highly reliable inductor device can be realized.
[0075]
Although the shape of the inductor is shown as an octagon here, it goes without saying that the same effect can be obtained even if the shape is a polygon such as a circle or a square.
[0076]
【The invention's effect】
According to the first aspect of the present invention, the area of the chip can be reduced, and an inductive element having a high Q value can be arranged. According to the second aspect of the present invention, a more reliable inductor device having a higher Q value is possible. According to the third aspect of the present invention, it is possible to provide a highly reliable inductor device having a higher Q value. According to the fourth aspect of the present invention, miniaturization and installation of a plurality of devices are possible. According to the fifth aspect of the present invention, it is possible to reduce the number of manufacturing steps and reduce the thickness at low cost. According to the present invention, the size can be reduced and a more reliable inductor device can be realized. According to the seventh aspect of the present invention, since the method of manufacturing a via having a high aspect ratio for the connection conductor is employed, miniaturization and installation of a plurality of devices are possible.
[Brief description of the drawings]
FIG. 1 is a diagram for explaining a first embodiment of the present invention; FIG. 2 is a diagram for explaining a second embodiment of the present invention; FIG. 3 is a diagram for explaining a third embodiment of the present invention; FIG. 4 is a view for explaining a fourth embodiment of the present invention. FIG. 5 is a view for explaining a fifth embodiment of the present invention. FIG. 6 is a view for explaining a fifth embodiment of the present invention. FIG. 8 is a partial enlarged view of FIG. 6; FIG. 8 is a view for explaining a sixth embodiment of the present invention; FIG. 9 is a view showing a conventional spiral inductor; FIG. 10 is a view showing another conventional spiral inductor; FIG. 12 shows a conventional inductor device. FIG. 13 shows a conventional spiral inductor. FIG. 14 shows a conventional differential inductor. FIG. 15 shows a conventional differential inductor. Fig. 16 shows a conventional inductor. Fig. 16 is a sectional view of a conventional via portion.
REFERENCE SIGNS LIST 1 circuit element forming layer 3 first dielectric layer 4 second conductor layer 5 protective film 6 first redistribution resin layer 7 second redistribution conductor layer 8 first redistribution conductor layer 9 second redistribution resin layer 10 metal wire DESCRIPTION OF SYMBOLS 11 Magnetic film 12 Via 13 Low melting point substance 21, 22 First conductor layer

Claims (7)

A circuit element forming layer on which a circuit element is formed;
A dielectric layer formed on a surface adjacent to the circuit element forming layer,
A conductor layer formed in contact with the dielectric layer,
A protective film layer covering the conductor layer and formed in contact with the dielectric layer;
A resin layer formed in contact with the protective film layer,
A second conductor layer formed in contact with the resin layer;
An inductor device comprising: a third conductor layer penetrating the dielectric layer and the resin layer and connecting the first conductor layer and the second conductor layer,
An inductor device, wherein an inductor shape formed by the first to third layers is substantially line-symmetric with respect to the inductor terminal pair. A circuit element forming layer on which a circuit element is formed;
A dielectric layer formed on a surface adjacent to the circuit element forming layer,
A protective film layer formed in contact with the dielectric layer,
A conductor layer formed in contact with the protective film layer,
A resin layer that covers the conductor layer and is formed in contact with the protective film layer;
A second conductor layer formed in contact with the resin layer;
An inductor device comprising: a third conductor layer that penetrates through the resin layer and connects the first conductor layer and the second conductor layer,
An inductor device, wherein an inductor shape formed by the first to third layers is substantially line-symmetric with respect to the inductor terminal pair. A circuit element forming layer on which a circuit element is formed;
A dielectric layer formed on a surface adjacent to the circuit element forming layer,
A protective film layer formed in contact with the dielectric layer,
A first resin layer formed in contact with the protective film layer;
A conductor layer formed in contact with the first resin layer;
A second resin layer which covers the conductor layer and is formed in contact with the first resin layer;
A second conductor layer formed in contact with the second resin layer;
An inductor device comprising: a third conductor layer that penetrates through the second resin layer and connects the first conductor layer and the second conductor layer,
An inductor device, wherein an inductor shape formed by the first to third layers is substantially line-symmetric with respect to the inductor terminal pair. 4. The inductor device according to claim 1, wherein the third conductor layer is a via having a high aspect ratio. 4. The inductor device according to claim 1, wherein the second conductor layers are interconnected by a wire. 6. The inductor device according to claim 1, wherein a magnetic material having high magnetic permeability is arranged at or near the center of the inductor. The inductor device according to claim 1, wherein the through-hole is formed by removing the low-melting-point substance after filling the periphery of the low-melting-point substance stacked in a column shape with the resin layer. 5. Production method.

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