JP2004328441A - Image capturing device and image processor - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image capturing device whose accuracy of connectability with a host device is enhanced by separating a vertical synchronizing signal from various complex synchronizing signals without requiring image size information. <P>SOLUTION: Regarding pulse width value setting of a pulse for detecting the vertical synchronizing signal used for separating the vertical synchronizing signal from the complex synchronizing signals, rough measurement of a horizontal period is performed first, a pulse width value is set based on its result, detailed measurement of the horizontal period is performed then and a pulse width value calculated based on its result is set as the final value. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention provides an image capturing device for inputting a video signal from a host device, capturing image information of the signal and outputting the image information to a printer, transmitting the image information to another device via a network, and outputting to a projector, and The present invention relates to an image processing device that incorporates the image capturing device and performs processing of image information related to images or characters.
[0002]
[Prior art]
Video signal formats include a horizontal synchronizing signal (hereinafter abbreviated as H signal), a vertical synchronizing signal (hereinafter abbreviated as V signal), and red, green, and blue image signals (hereinafter abbreviated as R, G, and B signals). A separate type composed of five signals, an H signal on which a V signal is superimposed, a composite sync type composed of four signals of R, G and B signals, and a V signal and an H signal superimposed on a G signal Alternatively, there is a composite video type composed of three signals of R, G, and B superimposed on all the R, G, and B signals.
[0003]
In order to capture image information, it is necessary to detect a frame start signal indicating the start of an image frame from the V signal, and to detect a line start signal indicating the start of the image scanning line from the H signal. In the separate type, since the V signal and the H signal are independent, the frame start and the line start can be detected without any special processing. However, in the composite sync type and the composite video type, since the V signal and the H signal are superimposed, it is necessary to separate each signal. Basically, by extracting one signal, the remaining signal can be separated, and in general, a method of extracting a V signal having a low frequency is often used. For example, a composite video type will be described below. In this composite video type, a video signal has a signal waveform as shown in FIG. 9 and is usually called a composite video signal. As shown in FIG. 9, the composite video signal is a signal in which an image signal is further superimposed on a pulse-like synchronization signal (hereinafter, referred to as a composite synchronization signal) in which an H signal and a V signal are superimposed. In most cases, the amplitude value of the composite synchronization signal is about 0.3 Vp-p. Therefore, paying attention to this amplitude value, for example, as shown in FIG. 10, if a comparator circuit set to an appropriate threshold voltage (0.15 V in FIG. 10) is used, only the image signal is converted from this composite video signal. And only the composite synchronizing signal on which the H signal and the V signal are superimposed can be separated.
Next, a description will be given of a method of separating the composite synchronization signal obtained in this manner into synchronization signals of a V signal and an H signal. As described above, basically, by extracting one of the synchronization signals, that is, the V signal having a low frequency, the remaining H signal can be separated.
[0004]
FIG. 11 is a time chart for explaining a method of separating the V signal from the composite synchronization signal. In order to separate the V signal from the composite synchronizing signal, as shown in FIG. 11, a vertical synchronizing signal detecting pulse which has a proper pulse width and is repeated at a constant period from the falling of the composite synchronizing signal is used as a starting point. The composite synchronizing signal is sampled at the rising edge of the pulse for detecting the vertical synchronizing signal (the black circle in FIG. 11), and if it is 1 (or High), it is a non-vertical synchronizing part. The V signal can be separated as shown in FIG. 11 by judging that the signal is a vertical synchronizing unit (that is, a V signal).
[0005]
As the pulse width of the pulse for detecting the vertical synchronization signal, an approximate value obtained from image size information is usually used. As an example, in the VGA mode in which the number of horizontal pixels * the number of vertical pixels = 640 * 480, one cycle of the horizontal synchronization signal (hereinafter abbreviated as horizontal cycle) is about 30 .mu.s. In the XGA mode in which the number of horizontal pixels * the number of vertical pixels = 1024 * 768, the horizontal period is about 20 μs, so that 30% of 6 μs is set as the pulse width of the pulse for detecting the vertical synchronization signal. This is the usual way.
[0006]
In determining the pulse width of the pulse for detecting the vertical synchronizing signal, 30% of the horizontal cycle is used for the following reason, and will be briefly described with reference to FIG.
[0007]
FIG. 12 is a time chart illustrating the types and timings of the composite synchronization signal. Many display devices such as recent monitor devices and video display devices perform processing using various kinds of pulse signals in order to improve display quality. For this reason, as shown in FIG. In some cases, complicated unnecessary pulses such as serrations (reverse polarity pulses) and equalization pulses are mixed in the region. An example in which serrations (reverse polarity pulses) are mixed in the vertical synchronizing section (V signal) region is a composite synchronizing signal A, and an example in which equalization pulses are further mixed so as to overlap with the serrations. This is the composite synchronization signal B.
[0008]
The composite synchronizing signal C indicates a video synchronizing signal in which neither a serration nor an equalizing pulse is mixed in the vertical synchronizing section (V signal) area. Assuming such various composite synchronization signals, for example, in the case of the composite synchronization signal A, if the pulse width of the vertical synchronization signal detection pulse is too short, the H signal is erroneously recognized as the V signal. On the other hand, in the case of the composite synchronizing signal B, if the pulse width of the pulse for detecting the vertical synchronizing signal has a long pulse width of 50% to 60%, the equalizing pulse is converted to a V signal. There is a risk of sampling and misidentifying. For this reason, from the experience so far, the pulse width of the pulse for detecting the vertical synchronization signal is generally set to about 30% of the horizontal period (for example, Non-Patent Document 1).
[0009]
[Non-patent document 1]
Analog devices, documents, (Japan time, search February 14, 2003) Internet <URL, http: // www. analog. com / UploadedFiles / Datasheets / 91119016AD9888_a. pdf>
[0010]
[Problems to be solved by the invention]
The video signals of all host devices do not always conform to the standards such as VGA and XGA, and many devices output signals at their own timing. In particular, in the case of video signals output from measuring instruments, industrial plant control equipment, medical equipment, and the like, cases where individual products are uniform are conspicuous. In recent years, even when the image size is VGA or XGA standard size, a plurality of vertical frequencies and horizontal frequencies are present. Therefore, the method of extracting the V signal from the composite synchronization signal itself does not pose a problem as in the conventional method in which a pulse for detecting a vertical synchronization signal is generated starting from the fall of the synchronization signal and the synchronization signal is sampled. It is becoming difficult to determine the pulse width of the detection pulse only from the image size.
[0011]
Further, it is sufficient to measure the horizontal period and set 30% of the period as the pulse width. However, the horizontal period cannot be measured unless the V signal and the H signal are separated from the composite synchronization signal. In addition, even when trying to measure the horizontal period of the composite synchronization signal, the measured timing sometimes coincides with the vertical synchronization part. As described above, there is a demand for an image capturing device that can correspond to any host device that generates various complicated video signals.
[0012]
Therefore, the present invention does not require the image size information generated by the host device, and can separate the vertical synchronizing signal and the horizontal synchronizing signal from a variety of video signals, in particular, a composite synchronizing signal, so that the image can be compatible with any host device. It is an object to provide a capturing device.
[0013]
[Means for Solving the Problems]
Therefore, in the present invention, when determining the appropriate value of the pulse width for detecting the vertical synchronization signal for extracting the V signal from the composite synchronization signal, first, the approximate horizontal period is measured and the approximate appropriate value of the pulse width for detecting the vertical synchronization signal is determined. Then, the V signal is extracted using the pulse width value, the period of the H signal (ie, the horizontal period) is measured, and the value of 30% of the accurate horizontal period obtained as a result of the measurement is used as the final vertical value. The device configuration can be used as a pulse width for detecting a synchronization signal.
[0014]
That is, in order to obtain an approximate horizontal cycle, a first horizontal cycle comprising a first counter for counting the number of falling edges of the composite synchronization signal and a second counter for managing the enable time of the first counter. A measuring unit, and a third counter that outputs a measurement enable signal during a period of the H signal to be measured using the V signal output from the sync separator that separates the composite synchronization signal into a V signal and an H signal as a count start pre-trigger; Controlling a sequence of a second horizontal cycle detail measuring section comprising a fourth counter for measuring the time during which the enable signal is 1 and further to a first horizontal cycle detail measuring section and a second horizontal cycle detail measuring section. The configuration uses a CPU for performing the operation.
[0015]
Therefore, the image capturing device of the present invention receives a video signal from a host device and separates and detects three signals of a horizontal synchronizing signal, a vertical synchronizing signal, and an image signal from the video signal. An image capturing device that captures an image generated in the host device through the video signal receiving unit, wherein the video signal receiving unit uses the pulse for detecting a vertical synchronization signal generated by itself to perform the horizontal synchronization. A sync separator for separating the horizontal synchronization signal and the vertical synchronization signal from a composite synchronization signal in which a signal and the vertical synchronization signal are superimposed, and measuring the number of pulses generated within a predetermined time of the composite synchronization signal. The pulse width value of the pulse for detecting the vertical synchronization signal is roughly set, and based on the roughly set pulse width value, A horizontal cycle rough measuring section for controlling the pulse width of the direct sync signal detecting pulse, and the vertical sync signal detecting pulse which is roughly set by the horizontal cycle rough measuring section is output so as to be separated by the sync separator. The pulse width of the vertical synchronization signal detection pulse is reset again from the horizontal synchronization signal and the vertical synchronization signal, and the vertical synchronization signal detection is performed via a CPU based on the reset pulse width value. And a horizontal cycle detail measuring unit for re-controlling the pulse width of the application pulse.
[0016]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
[0017]
FIG. 1A is a block diagram showing an external connection configuration of the image capturing device according to the embodiment of the present invention. The image capturing device 1 of this embodiment captures a video signal output from a host device, outputs image information to a printer, transmits the image information to another device via a network, outputs the image information to a projector, Or an auxiliary storage device such as a memory card. Needless to say, it is not necessary to provide all outputs, and it is possible to appropriately output any of the image information output devices as needed.
[0018]
The host device is, for example, a personal computer or a workstation used in an office, for example, and may be a dedicated computer used in an image processing field such as a medical field, an industrial field, and a measurement field. And the like.
[0019]
On the other hand, FIG. 1B shows an example of an external connection configuration showing another embodiment of the present invention. As shown in FIG. 1B, an image capture device having the same function as the image capture device 1 is provided. The present invention can also be applied to an integrated device (image processing device) in which a unit is built in a printer. Of course, it is not limited to a printer but is configured as an integrated device (image processing device) incorporated in an appropriate image information output device such as a projector, an auxiliary storage device such as a hard disk, a memory card, a network device, or the like. It is also possible.
[0020]
FIG. 2 is a block diagram showing the overall configuration of the image capturing device 1. The video signal output from the host device is received by the video signal receiving unit 26. The video signal receiving unit 26 separates the video signal into a vertical synchronizing signal, a horizontal synchronizing signal, and an image signal and outputs the video signal to the image memory write / read control unit 27.
[0021]
The image memory write / read control unit 27 analyzes the separated image signal to obtain image information, and writes the image information into the image memory 28. The image information written in the image memory 28 is read from the printer interface unit 29 via the image memory write / read control unit 27, and is output to a printer connected to the outside or read from the network interface unit 30. Over the network, read from the video signal output unit 31 and output to the projector, or read from the disk drive interface unit 32 and externally connected to a hard disk or floppy disk, CD-R or CD-R. The data is stored in an auxiliary storage device such as an RW, or is read from the memory card interface unit 33 and stored in an externally connected memory card.
[0022]
As the above-mentioned interface standards, for example, there are IEEE1284, USB, IEEE1394 and the like as printer interfaces, 100BASE-TX as a network interface, VGA and XGA as video signal output standards, and RS-170A as well as video signal output standards. . The disk drive interface includes SCSI or ATA, and the memory card interface includes PCMCIA. Each of the interface units outputs and transmits image information to the outside according to signal specifications conforming to those standards.
[0023]
On the other hand, the control system includes a CPU (Central Processing Unit) 21 for performing overall control inside the printer, a ROM (Read Only Memory) 22 in which control programs and control data executed by the CPU 21 are stored, and a working memory in the CPU 21. A RAM (Random Access Memory) 23 for providing a space, an NVRAM (non-volatile RAM) 24 which stores custom information and the like registered by a user and can retain data even when power is shut off by a backup battery, and an operation panel 34 An operation panel control unit 25 for controlling the key input of the keypad and the output to the display unit of the operation panel 34 is provided.
[0024]
FIG. 3 is an internal block diagram of the video signal receiving unit 26 of FIG. Video signals output from the host device include a vertical synchronization signal VIN, a horizontal synchronization signal HIN, a red (red) analog image signal RA, a green (green) analog image signal GA, and a blue (blue) analog image signal BA. From the signals RA, GA, and BA, an AC component is extracted by an AC coupling 41, amplified by an operational amplifier 42, and converted into digital image signals RD, GD, and BD by an A / D converter 43. The horizontal synchronizing signal of the video signal may be output as an independent signal as the horizontal synchronizing signal HIN, or may be superimposed on an image signal, for example, green. .
[0025]
The AC component of the horizontal synchronizing signal superimposed on the green analog image signal GA is extracted by an AC coupling 41, converted into a digital signal by a comparator 44, and then input to a selector 45. The horizontal synchronization signal output from the selector 45 is output to the image memory write / read control unit 27 via the sync separator 46 as a horizontal synchronization signal HSYNC, that is, a signal HOUT.
[0026]
The vertical synchronizing signal of the video signal may be output as an independent signal as the vertical synchronizing signal VIN, may be superimposed on the horizontal synchronizing signal HIN, or may be superimposed on an image signal, for example, green. When the signal is output as a single V signal, the VIN signal is output as the signal VOUT via the selector 46. When the V signal is superimposed on the horizontal synchronizing signal HIN, the selector 45 selects HIN, the sync separator 46 separates the V signal, and the selector 49 selects the V signal, that is, VSYNC, and outputs an image as the signal VOUT. Output to the memory write / read controller 27.
[0027]
When the V signal is superimposed on the image signal, for example, green, the selector 45 selects the H signal on which the V signal output from the comparator 44 is superimposed, the sync separator 46 separates the V signal, and the selector 49 selects the H signal. The V signal output from the sync separator 46, that is, VSYNC is selected and output to the image memory write / read control unit 27 as the signal VOUT. The horizontal cycle approximate measuring section 47 is a block for measuring an approximate horizontal cycle, and the horizontal cycle detail measuring section 48 is a block for measuring a detailed horizontal cycle. This will be described in the description of block 2.
[0028]
FIG. 4 is an internal block diagram of the horizontal cycle measurement block 2 of FIG. The approximate horizontal cycle measurement is performed on the composite synchronization signal output from the selector 45 by the horizontal cycle approximate measurement section 47 in this block, and the detailed horizontal cycle measurement is further performed by the horizontal cycle detail measurement section 48. A pulse width value for vertical synchronization signal detection used for typical V signal separation is determined, the pulse width value is set in the sync separator 46, and the V signal separated from the composite synchronization signal is output to the selector 49 as a signal VSYNC.
[0029]
The specific processing procedure will be described with reference to FIGS. FIG. 5 is a time chart showing the transition between the composite synchronizing signal and the count value CNT1 of the counter 51 in the horizontal cycle measurement by the above-described horizontal cycle rough measuring section 47. Here, the count enable time t of the counter 52 is shown. Is set to 20 ms, and the count result of the counter 51 at the time when the counting of the counter 52 ends is CNT1 = 1066.
[0030]
First, the CPU 21 sets a count time t for the counter 52 using the signal CLK as a count clock. Next, the CPU 21 outputs a count start signal ST to the counter 52. The counter 52 outputs 1 to the counter 51 as the count enable signal EN2 for the count time t. While the signal EN2 is 1, the counter 51 counts up using the falling edge of the composite synchronization signal as a count clock. When the count time t has elapsed, the signal EN2 becomes 0, and the counter 51 stops counting operation and the CPU 21 detects the end of counting.
[0031]
The CPU 21 reads the count value CNT1 of the counter 51, calculates the approximate horizontal cycle by the calculation of t / CNT1, and uses the pulse width PLS of the vertical synchronization signal detection pulse used to separate the V signal from the composite synchronization signal. Is calculated from the arithmetic expression t / CNT1 * 0.3 and set in the sink separator 46.
[0032]
In the example shown in FIG. 5, the counter 52 is operated with the count enable time t of 20 ms, and the count result of the counter 51 at the time when the counting of the counter 52 ends is CNT1 = 1066. In this case, the CPU 21 sets PLS = t / CNT1 *. 0.3 = 5.62 [μs] is set in the sync separator 46 as the pulse width value of the vertical synchronization signal detection pulse used to separate the V signal from the composite synchronization signal.
[0033]
FIG. 6 is a time chart showing a state in which the V signal is separated from the composite synchronization signal as a result of setting PLS to 5.62 [μs] as described above. At this stage, the V signal can be separated with sufficient accuracy. However, an embodiment in which the horizontal period is measured in more detail, and the pulse width value of the pulse PLS for detecting the vertical synchronization signal is calculated and applied is shown in FIGS. 7 will be described below. Although detailed description is omitted, the detailed value of the horizontal period is required when the analog image signal is converted into a digital signal by the A / D converter 43 in FIG. Even if only a rough measurement of the horizontal cycle is sufficient, the detailed measurement of the horizontal cycle does not become unnecessary.
[0034]
FIG. 7 is a time chart showing the VSYNC signal, the HSYNC signal, and the transition of the counter 53 and the counter 54 in the horizontal cycle detail measurement by the horizontal cycle detail measurement section 48 described above. Here, the period T of the count clock signal CLK of the counter 54 is set to 0.1 μs, and the count enable timing of the counter 54 is set between the tenth HSYNC after the VSYNC and the eleventh HSYNC.
[0035]
The count enable timing is set to be Nth (in this example, 10th) instead of immediately after VSYNC even in the case where the vertical synchronizing portion and the equalizing pulse before and after the vertical synchronizing portion like the composite synchronizing signal B in FIG. This is to enable the period to be measured. Normally, when an equalization pulse is present in the synchronization signal, it is up to about three horizontal periods before and after the vertical synchronization unit. Therefore, the number of HSYNC pulses after VSYNC until the timing when the equalization pulse no longer exists is 2 * 3 = 6. It is sufficient to set N = approximately 10 in view of the margin as in this example.
[0036]
In FIG. 4, the counter 53 outputs 1 to the count enable signal EN3 of the counter 54 from the Nth HSYNC to the (N + 1) th HSYNC after VSYNC output from the sync separator 46. The counter 54 using the signal CLK whose clock cycle is T as a count clock counts up while the signal EN3 is 1. When the (N + 1) th HSYNC is output, the signal EN3 becomes 0, the counter 54 stops the counting operation, and at the same time, the CPU 21 detects the end of the counting.
[0037]
The CPU 21 reads the count value CNT4 of the counter 54, calculates a detailed horizontal cycle by an arithmetic expression T * CNT4, and calculates the pulse width PLS of the vertical synchronization signal detection pulse used for separating the V signal from the composite synchronization signal. It is calculated from the arithmetic expression T * CNT4 * 0.3 and set in the sink separator 46.
[0038]
In the example shown in FIG. 7, the count end value of the counter 54 is 189, and the value of the detailed horizontal cycle is obtained by the CPU 21 as T * CNT4 = 0.1 [μs] * 189 = 18.9 [μs]. The pulse width PLS of the pulse for detecting the vertical synchronization signal is obtained as PLS = T * CNT4 * 0.3 = 5.67 [μs]. Finally, the CPU 21 sets PLS = 5.67 [μs] in the sync separator 46, and is used to separate the V signal from the composite synchronization signal. According to the above-described procedure, a more detailed value of the pulse width of the pulse for detecting the vertical synchronization signal is determined.
[0039]
FIG. 8 is a time chart showing how the synchronization signal separation flow of the present invention can be applied to the three cases of composite synchronization signals as shown in FIG. 12, and FIG. 8B is a schematic horizontal cycle measurement of the composite synchronization signal B in FIG. 12, and FIG. 8C is a schematic horizontal cycle of the composite synchronization signal C in FIG. FIG. 8D is a time chart showing a detailed horizontal cycle measurement of the composite synchronization signal C in FIG. The schematic horizontal cycle measurement of the composite synchronization signal A of FIG. 12 and the detailed horizontal cycle measurement of the composite synchronization signal B of FIG. 12 are as described with reference to FIGS. 5 and 7, respectively. Thus, the present invention is applicable to each case.
[0040]
【The invention's effect】
As described above, according to the present invention, a video signal is input, and image information of the signal is captured and output to a printer, transmitted to another device via a network, or output to a projector. The image capture device does not require the conventional image size information for the synchronization signal separation from the composite synchronization signal, and is reliable even in the case where the equalization pulse exists in the vertical synchronization unit or the case where there is no serration in the vertical synchronization unit. And the accuracy of synchronization signal separation can be dramatically improved. As a result, it is possible to greatly increase the types and the number of host devices to be connected to the image capturing device.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating an example of an external connection configuration (a) of an image capturing device according to an embodiment of the present invention, and another example of an external connection configuration (b).
FIG. 2 is a block diagram illustrating an overall configuration of an image capturing device according to the present invention.
FIG. 3 is an internal block diagram of a video signal receiving unit according to the present invention.
FIG. 4 is an internal block diagram of a horizontal cycle measurement block according to the present invention.
FIG. 5 is a time chart illustrating the operation of the horizontal cycle schematic measurement unit according to the present invention.
FIG. 6 is a time chart illustrating the operation of the horizontal cycle schematic measurement unit according to the present invention.
FIG. 7 is a time chart illustrating the operation of the horizontal cycle detail measurement unit according to the present invention.
FIG. 8 is a time chart for explaining the operation of the horizontal cycle rough measurement section or horizontal cycle detail measurement section according to the present invention.
FIG. 9 is a waveform diagram for explaining a composite video signal waveform.
FIG. 10 is an example of a circuit for separating a composite synchronization signal from a composite video signal.
FIG. 11 is a time chart illustrating a method of separating a V signal from a composite synchronization signal.
FIG. 12 is a time chart illustrating types and timings of a composite synchronization signal.
[Explanation of symbols]
1 Image capture device
2 Horizontal cycle measurement block
21 CPU
22 ROM
23 RAM
24 NVRAM
25 Operation panel control unit
26 Video signal receiver
27 Image Memory Write / Read Control Unit
28 Image memory
29 Printer interface
30 Network interface
31 Video signal output section
32 Disk drive interface
33 Memory card interface
34 Operation panel
41 AC coupling circuit
42 Operational Amplifier
43 A / D converter
44 Comparator
45 selector
46 sink separator
47 Horizontal Cycle Outline Measurement Unit
48 Horizontal Cycle Detail Measurement Unit
49 Selector
51 counter
52 counter
53 counter
54 counter
RA red analog image signal
GA green analog image signal
BA Blue analog image signal
HIN horizontal sync signal
VIN vertical sync signal
RD Red digital image signal
GD green digital image signal
BD blue digital image signal
HOUT horizontal synchronization signal output from the video signal receiving unit 26
VOUT Vertical synchronization signal output from the video signal receiving unit 26
CNT1 Counter 51 count value
EN2 count enable signal of counter 51
CLK Clock signal of the counter 52 and the counter 54
t Counter 52 count time
Start signal of ST counter 52
Set value of one-shot pulse width used for synchronization signal separation in PLS sync separator 46
HSYNC Horizontal sync signal output from sync separator 46
VSYNC Vertical sync signal output from sync separator 46
EN3 count enable signal of counter 54
Count value of CNT4 counter 54

Claims (6)

A video signal receiving unit that receives a video signal from a host device, and separates and detects three signals of a horizontal synchronization signal, a vertical synchronization signal, and an image signal from the video signal, and includes an image generated by the host device. An image capturing device for capturing via the video signal receiving unit,
The video signal receiving unit,
A sync separator that separates the horizontal synchronization signal and the vertical synchronization signal from a composite synchronization signal in which the horizontal synchronization signal and the vertical synchronization signal are superimposed, using a vertical synchronization signal detection pulse generated by itself,
By measuring the number of pulses generated within a predetermined time of the composite synchronizing signal, the pulse width value of the pulse for detecting the vertical synchronizing signal is roughly set, and the pulse width value is set via the CPU based on the pulse width value that is roughly set. A horizontal period rough measuring unit for controlling a pulse width of a pulse for detecting a vertical synchronization signal,
From the horizontal synchronization signal and the vertical synchronization signal output so as to be separated in the sync separator using the vertical synchronization signal detection pulse roughly set by the horizontal cycle outline measurement unit, the vertical synchronization signal A horizontal cycle detail measuring unit that resets the pulse width of the detection pulse and re-controls the pulse width of the vertical synchronization signal detection pulse via the CPU based on the reset pulse width value. An image capturing device, comprising: The horizontal cycle rough measurement unit includes a first counter that measures the predetermined time based on a count start signal and a count end set value, and the first counter that is generated within the predetermined time during which the first counter is operating. 2. The image capturing device according to claim 1, further comprising a second counter that measures the number of pulses of the composite synchronization signal. The horizontal cycle detail measuring unit includes: a third counter for measuring the number of horizontal synchronization signals generated after the vertical synchronization signal output so as to be separated by the sync separator; 2. The image capturing apparatus according to claim 1, further comprising a fourth counter for measuring a time from the (integer) th horizontal synchronization signal to the (N + 1) th horizontal synchronization signal. The image capturing device according to any one of claims 1 to 3, further comprising an interface unit connected to an externally provided image information output device. The image information output device includes a printer that prints images or characters on recording paper, a communication device that transmits the images or characters to other devices via a network, a projector that projects images or characters, and an auxiliary storage that stores data related to images or characters. The image capturing device according to claim 4, wherein the image capturing device is one of a device and a memory card. An image processing device incorporating the image capturing device according to any one of claims 1 to 3 and processing image information on an image or a character.

Images