CN116208759A - Video communication system delay test method and equipment based on image watermark - Google Patents

Video communication system delay test method and equipment based on image watermark Download PDF

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Publication number
CN116208759A
CN116208759A CN202211637320.9A CN202211637320A CN116208759A CN 116208759 A CN116208759 A CN 116208759A CN 202211637320 A CN202211637320 A CN 202211637320A CN 116208759 A CN116208759 A CN 116208759A
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module
image
information
video information
display
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水云鹏
任翔
刘雅婧
陈伯昕
宋锐
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Nanjing Xiandian Tongyuan Information Technology Co ltd
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Nanjing Xiandian Tongyuan Information Technology Co ltd
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    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N17/00—Diagnosis, testing or measuring for television systems or their details
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N21/00—Selective content distribution, e.g. interactive television or video on demand [VOD]
    • H04N21/80—Generation or processing of content or additional data by content creator independently of the distribution process; Content per se
    • H04N21/83—Generation or processing of protective or descriptive data associated with content; Content structuring
    • H04N21/835—Generation of protective data, e.g. certificates
    • H04N21/8358—Generation of protective data, e.g. certificates involving watermark

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  • Multimedia (AREA)
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  • Health & Medical Sciences (AREA)
  • Biomedical Technology (AREA)
  • General Health & Medical Sciences (AREA)
  • Computer Security & Cryptography (AREA)
  • Testing, Inspecting, Measuring Of Stereoscopic Televisions And Televisions (AREA)

Abstract

The invention provides video communication system delay test equipment based on image watermarking, which belongs to the technical field of imaging and comprises an upper computer, an FPGA (field programmable gate array) and a display, wherein the upper computer and the display are respectively in communication connection with the FPGA; the FPGA is used for receiving initial video information sent by the upper computer, adding watermark information to the video information, then sending the video information to the display, and driving the display to display the video information added with the watermark information; the FPGA is also used for receiving video information returned by the system to be tested and returning the video information to the upper computer; the display is used for receiving video information sent by the FPGA and displaying the video information for acquisition of a system to be tested; a method of using the test apparatus; the invention can simplify the image matching process and reduce the influence of test equipment on the result.

Description

Video communication system delay test method and equipment based on image watermark
Technical Field
The invention belongs to the technical field of imaging, and particularly relates to a video communication system delay test method and device based on image watermarking.
Background
The video transmission process mainly involves encoding, transmitting and decoding image frames, in which video communication delays are created. Wherein the encoding delay includes video acquisition delay (i.e., block capture delay), frame ordering delay, and video encoding processing delay; the transmission delays include an encoding buffer delay, a network delay, and a decoding buffer delay; the decoding delay includes a video decoding processing delay and a frame reordering delay. The traditional delay measurement mode is mainly based on a stopwatch experiment for measurement, and is greatly influenced by human factors, so that the error is large, and the test efficiency is low.
In order to solve the above problems, chinese patent publication No. CN113612988A discloses a method, apparatus and video transmission device for automatically testing video delay. The video delay test method transmits a dynamic video signal into equipment to be tested, and re-outputs the dynamic video signal; capturing a frame of image in a dynamic video signal as a first image, and obtaining corresponding first time; capturing each frame of image of a dynamic video signal output by the equipment to be tested, and obtaining a plurality of frames of second images and a plurality of corresponding second times; and comparing the first image with a plurality of second images in turn to determine the second image which is the same frame as the first image, and calculating the video delay of the device to be tested by using the corresponding second time and the first time. The method can automatically test video delay, and has the advantages of small test error, low cost, convenience in debugging and the like. However, the method has higher requirements on the matching accuracy of the image frames, the matching workload is larger, and the calculation force is higher.
In the prior art, U.S. patent publication No. US20170039999A1 discloses "Photon Latency Measurement System and Method" (photon delay measurement system and method). The method provides a benchmark test method for measuring delay of a computer application program to a physical display, and comprises three parts of the display, a measurement framework and hardware detection. Wherein the display is used to display the computer application under test, the measurement framework is used to obtain a computer hardware timestamp (e.g., a timestamp that detects the transmission of a computer signal executing the application), and the hardware detection is used to detect a transition on the display (e.g., detecting and capturing a change in screen using a camera). When the computer application and the measurement framework are executed, the application is displayed on a display and the measurement framework is notified to begin a delayed measurement instance. The measurement framework is executed synchronously to obtain a timestamp internal to the current computer hardware as a first timestamp. And detecting information by hardware detection, and sending a notification to a measurement frame when detecting that the display is changed, wherein the measurement frame records that the current time stamp is the second time stamp. The video transmission delay is calculated by comparing the first timestamp generated by the application with a second timestamp associated with the indication of the display to present the new information and subtracting the hardware detected characteristic delay. The method can accurately obtain the time stamp of the change of the application program, and can be used for relatively clear PC system test, such as virtual reality game. However, in the hardware detection link in the method, errors are easy to occur in detecting the change of the display, uncertainty exists in external time delay, and the influence on the measurement result is large.
U.S. patent publication No. US20140085459A1 discloses "Latency Measurement System and Methon" (delay test system and method). Comprising an event generating means for generating an initial event for measuring a system delay; a component test system receives the event and responsively outputs a test component signal and a zero delay indicator; an electronic system including a multi-functional display unit receives the output signal of the test assembly and displays a visual element on the multi-functional display unit; one camera produces a series of recorded images, where each recorded image contains an image of the zero-delay indicator and an image of the visible element. The processor determines the system delay by determining a time difference between a state of occurrence of an event in the zero-delay indicator image and a state of occurrence of an event in the visible element image in a series of consecutive recorded images. The method is suitable for delay measurement of specific components in the electronic system, can avoid influence on the electronic system by adopting non-invasive measurement, and is simple to operate. But requires higher requirements for measurement equipment, such as camera frame rate.
The delay test mode has the following defects: (1) The testing process needs to be accurately compared and the processing efficiency of the matched images is low, so that the timeliness is poor; (2) The uncertainty exists in the test equipment, and the influence on the accuracy of the test result is large.
Disclosure of Invention
The invention aims to solve the problems in the background art, and provides a video communication system delay test method and device based on image watermarking, which can simplify the image matching process, improve the test result processing efficiency, reduce the influence of test equipment on the result, improve the accuracy and reduce the test cost.
In order to achieve the technical purpose, the invention adopts the following technical scheme:
a video communication system delay test method based on image watermarking includes the following steps:
step one: the testing equipment preprocesses the video information; adding a digital watermark to each frame of image information in the video information, and driving a display to display the video information added with the image watermark; the digital watermark comprises a plurality of positioning points and timestamp information T when the frame image is output through an interface 1 ；
Step two: the system to be tested collects video information of the display and transmits the video information to the testing equipment;
step three: the testing equipment acquires video information returned by the system to be tested and records time stamp information T of each received frame of image 2 .
Step four: the testing equipment processes the video information returned by the system to be tested, and determines a time stamp T corresponding to the digital watermark in each frame of image through a locating point 1 And for time stamp information T 1 Performing recognition recovery;
step five: by calculating time stamp information T for each frame of image as received by the test device 2 Timestamp information T corresponding to the digital watermark of the frame image 1 And obtaining the video communication delay of the system to be tested.
The video communication system delay test equipment based on the image watermark comprises an upper computer, an FPGA and a display, wherein the upper computer and the display are respectively in communication connection with the FPGA, and the FPGA is also in communication connection with a system to be tested;
the upper computer is used for sending initial video information, receiving the video information returned by the identification FPGA, and calculating the video communication delay of the system to be tested;
the FPGA is used for receiving initial video information sent by the upper computer, adding watermark information to the video information, then sending the video information to the display, and driving the display to display the video information added with the watermark information; the FPGA is also used for receiving video information returned by the system to be tested and returning the video information to the upper computer;
the display is used for receiving video information sent by the FPGA and displaying the video information for acquisition of a system to be tested;
the upper computer comprises a communication module, an image recognition module and a delay calculation module;
the communication module is used for realizing information transmission between the upper computer and the FPGA;
the image recognition module is used for recognizing watermark information of each frame of image in video information sent back by the FPGA and obtaining a time stamp T in the watermark information of each frame of image 1 ；
The delay calculation module is used for calculating a time stamp T when the FPGA receives one frame of image in the video information returned by the system to be tested 2 And a time stamp T contained in watermark information in the frame image 1 Calculating to obtain video communication delay of the system to be tested;
the FPGA comprises a timer module and an image preprocessing module
The timer module is used for acquiring a time stamp of the current frame image when the current frame image is received or transmitted;
the image preprocessing module is used for adding watermark information to each frame of image in the video information, wherein the watermark information comprises a plurality of positioning points and a time stamp T when the FPGA sends the current frame of image 1 ；
Preferably, the watermark information includes 3 anchor points.
Preferably, the upper computer further comprises a result display module and a communication configuration module; the result display module is used for displaying delay information of the current frame image and video information which is received in real time and returned by the system to be tested through the FPGA; and the communication configuration module is used for starting communication between the upper computer and the FPGA.
Preferably, the communication module uses a UDP communication protocol as an information transmission protocol between the upper computer and the FPGA.
Preferably, the FPGA further comprises a DDR3 control module, a DDR storage module, a UART serial port module, an ETH network port module, a high-speed display driving module and a test result feedback module;
the DDR3 control module is used for screening out required data information according to a serial port instruction output by the UART serial port module and controlling the high-speed display driving module to display the data information on a display; the DDR3 also determines the burst length and the address maximum value of the DDR memory module;
the DDR storage module comprises an MIG IP core module, a read-write module and a FIFO scheduling module;
the MIG IP core module is used for connecting the peripheral equipment and the FPGA;
the read-write module is used for interaction between the MIG IP core module and the DDR3 read-write command and read-write address;
the FIFO scheduling module is used for converting the input data bit width of the external equipment into MIG IP core bit width and converting DDR3 read data bit width into the input data bit width of the external equipment;
the UART serial port module is used for realizing communication of an upper computer or a system to be tested;
the EHT network port module is used for receiving video information of the upper computer and the system to be tested;
the high-speed display driving module is used for driving the display to display corresponding image or video information according to the serial port instruction of the UART serial port module;
the test result feedback module is used for feeding back the video information fed back by the system to be tested and the time stamp obtained by the timer module when the video information is received to the upper computer.
Preferably, the FPGA is connected to the display through an HDMI1 interface and connected to the system under test through HDMI 2.
The beneficial effects of the invention are as follows:
1. the FPGA is used for adding watermark information to each frame of image of video information, so that subsequent image matching is realized, only watermark information which is easy to locate and simple in content is needed to be matched, the image matching process is greatly simplified, the processing efficiency is improved, real-time delay display can be realized, and the requirement on the calculation power of test equipment is reduced.
2. The whole test equipment is mainly processed and calculated through the FPGA and the upper computer internal module, external hardware equipment is not needed, the influence of the test equipment on the result is reduced, the accuracy is improved, the test cost is reduced, and the method has practical significance and good application prospect.
Drawings
FIG. 1 is a schematic diagram of a test apparatus according to the present invention;
FIG. 2 is a schematic diagram of a frame of video information after PFGA preprocessing;
FIG. 3 is a schematic diagram of an upper computer interface;
FIG. 4 is a DDR read/write state jump diagram;
FIG. 5 is an ETH portal module receiving state jump flow chart;
FIG. 6 is a flow chart of a test result return module sending state jumps.
Detailed Description
Embodiments of the present invention are described in further detail below with reference to the accompanying drawings.
It should be noted that the terms like "upper", "lower", "left", "right", "front", "rear", and the like are also used for descriptive purposes only and are not intended to limit the scope of the invention in which the invention may be practiced, but rather the relative relationship of the terms may be altered or modified without materially altering the teachings of the invention.
Example 1
As shown in fig. 1, the video communication system delay test device based on the image watermark comprises an upper computer, an FPGA and a display, wherein the upper computer and the display are respectively in communication connection with the FPGA, and the FPGA is also in communication connection with a system to be tested;
the upper computer is used for sending initial video information, receiving the video information returned by the identification FPGA, and calculating the video communication delay of the system to be tested;
the FPGA is used for receiving initial video information sent by the upper computer, adding watermark information to the video information, then sending the video information to the display, and driving the display to display the video information added with the watermark information; the FPGA is also used for receiving video information returned by the system to be tested and returning the video information to the upper computer; the watermark is shown in figure 2 and comprises three positioning points and a time stamp T when the frame image is sent to a display by an FPGA 1 Specifically, the method is described in detail in an image preprocessing module.
The display is used for receiving video information sent by the FPGA and displaying the video information for acquisition of a system to be tested;
as shown in fig. 3, the upper computer interface displays a configurable local address, a local port, a target address and a target port, and a test result (unit millisecond) of video communication delay and a video transmitted back by the device to be tested in real time;
the upper computer mainly comprises the following functional modules:
(1) And a communication module: and the UDP communication protocol is used as a transmission protocol for video learning and instruction information between the upper computer and the FPGA. The method specifically comprises the steps of determining a specific data transmission format, wherein the specific data transmission format comprises a frame head, a frame number, a line number, an image data field, a delay T2 and a frame tail, and the frame head and the frame tail are used for judging the beginning and the ending of data transmission in the protocol; the frame number indicates the position of the current frame image in the video information; the image data field packs and transmits the current frame image in a row unit, and takes 1080p as an example, RGB 8bit values of each pixel in a row are sequentially transmitted; the row number indicates the row in which the pixel information transmitted in the current data packet is located; organizing the pixel data according to the frame number and the line number, and recovering a complete image; the delay T2 is a time stamp of the current frame image information received by the FPGA.
(2) An image recognition module: the method is used for obtaining watermark information of each frame of image in the video and obtaining time stamp information T when the FPGA sends the frame of image 1 . Firstly, determining the area of the nixie tube according to three positioning points, then determining the specific position of the four-bit nixie tube according to the positioning point positions, and finally, recognizing the digital information of the nixie tube as the timestamp T of the frame image 1 。
The main flow of determining the digital tube region positioning algorithm is as follows: firstly, searching three positioning angular points which are arranged before, carrying out smooth filtering on the picture in the process, binarizing and searching the outline, screening the features of two sub-outlines in the outline, and finding out three closest area positioning angular points from the screened outline; judging the positions of the three found positioning angular points, and mainly correcting the picture; connecting the three characteristic points, judging the connecting angles of the three characteristic points, wherein the largest angle in the triangle is the locating point of the upper left corner of the image; determining the positions of two other positioning points according to the angle difference of two sides of the angle; and finally, determining the range of the image watermark according to the positioning point position information, and calibrating the nixie tube region.
The main flow of the nixie tube information identification algorithm is as follows: performing binarization and corrosion expansion operation on the digital tube region on the basis of smoothing and filtering the image, searching a digital outline, and performing digital segmentation to obtain four independent nixie tube information; identifying nixie tube information by using threading method to obtain timestamp T of the frame image 1 。
(3) Delay calculation module: calculating a time stamp T of a frame of image when video information output by equipment to be tested is received by FPGA 2 And a time stamp T contained in the frame image watermark information 1 Obtaining video communication delay of the equipment to be tested;
that is, video communication delay t=t 2 -T 1 。
(4) The result display module: the method is used for displaying delay information (unit: millisecond; namely, the result obtained by calculation of the delay calculation module) of the current frame image and receiving video information returned by the equipment to be tested (returned by the FPGA) in real time.
(5) And a communication configuration module: and the communication between the upper computer and the FPGA is started. The method comprises the following steps: and setting a local IP address and a port and a target IP address and a port of the device to be tested.
The FPGA mainly comprises the following functional modules:
(1) An image preprocessing module: the method is used for preprocessing the test video information (original video information) sent by the upper computer, namely adding image watermark information; specifically, an analog four-bit nixie tube is added at the left upper corner of each frame of image of video information to be transmitted, the size of the area is 200 x 320 pixels, the background is white, three positioning points are included, the size of the positioning points is 40 x 40 pixels, the background area of the nixie tube is pure black, and the nixie tube is red.
(2) A timer module: to obtain the time stamp of the current frame image at the time of reception or transmission. The FPGA internal logic contains a timer with an accuracy of 1ms (so the overall accuracy of the test equipment is 1 ms), and cycles for 2.5s, with a count range of 0-2500.
The digital displayed by the watermark information nixie tube is the time stamp T when the FPGA sends the video information processed by the image preprocessing module to the display 1 (the timestamp is obtained by the timer module).
The timer module also obtains a time stamp when the video information output by the device to be tested is received by the FPGA, namely a time stamp T when a certain frame of image in the video information output by the device to be tested is received by the FPGA 2 The timer module is also used for acquiring and communicating the returned video information and transmitting the video information back to the upper computer for calculating the video communication delay by the delay calculation module.
(3) And the UART serial module is used for realizing communication with an upper computer or a system to be tested.
The UART serial port receiving protocol is specifically designed to capture a start bit by detecting a falling edge of a serial port receiving end, and because the serial port receiving end is an asynchronous signal, metastable state is brought, asynchronous processing, namely beat processing, is needed, the signal is beaten for two beats to prevent metastable state, a receiving state mark is pulled up to enter a serial port receiving process after the start bit is detected, in the process, the received data is counted by whether a baud rate period is reached through clock counting, the data is registered, and when a stop bit is received, the receiving state mark bit is pulled down to indicate that the receiving is completed.
(4) DDR3 control module: the UART serial port module is used for screening out required file information according to serial port instructions output by the UART serial port module, and the file information is displayed on a display through the HDMI 1.
The DDR3 control module selects the video image data output by the UART serial port module and the video image data output by the ETH network port module according to the serial port instruction output by the UART serial port module, and then displays the video image data on a display through HDMI 1; and simultaneously, setting the burst length and the address maximum value in the corresponding DDR memory module according to the image resolution in the serial port instruction information, thereby controlling the resolution of the DDR memory module for outputting video information images.
(5) DDR memory module: the system mainly comprises an MIG IP core module, a read-write module and a FIFO scheduling module.
DDR read-write module: the read-write module interacts with the MIG IP core module and the FIFO scheduling module at the same time, and generates read-write commands and addresses of the MIG IP core module according to the read-write count output by the FIFO scheduling module, namely the residual data quantity and DDR3 parameters (the MIG IP module interacts with DDR 3), and outputs the read-write commands and addresses to the MIG IP core module, and a state jump flow chart of the read-write commands and addresses is shown in figure 4.
MIG IP core module: is responsible for connecting the peripheral device and the FPGA.
FIFO scheduling module: the MIG IP core sets the bit width to 128 bits, and the bit width of the input and output image pixel data is 16 bits, and the FIFO mainly completes the conversion of 128 bits and 16 bits, namely, the switching of clock domains and the conversion of bit widths are carried out on the input and output data.
(6) An ETH portal module: the Ethernet receiving module is used for receiving the original video information sent by the upper computer and the video information output by the equipment to be tested;
for an ETH network port module, namely a UDP receiving module, whether a target MAC address is consistent with a development board MAC address or not, and whether a target IP address is consistent with the development board IP address or not is judged; the flow of the receiving module is as follows: receiving a preamble and a frame start delimiter, performing preamble discrimination, receiving an Ethernet frame header, performing MAC address discrimination, receiving an IP header, performing IP address discrimination, receiving a UDP header, receiving UDP data and finishing the reception; note that when any one of the received preamble, ethernet header, or IP header is erroneous, the direct jump is made to the end of reception. The ETH portal module state jump flowchart is shown in fig. 5.
(7) A high-speed display driving module: and the display is driven to display corresponding video information according to the serial port instruction of the UART serial port module. In particular, in this embodiment, the high-speed display driving module converts the RGB565 format, i.e., the 16-bit pixel data, output by the host computer into the RGB888 format, i.e., the 24-bit pixel data, for display on the display.
(8) And a test result returning module: the method is used for packaging video information received through the HDMI2 and time stamps thereof during receiving and transmitting the video information back to the upper computer through the UDP protocol.
The test result feedback module is also a UDP sending module, the flow is similar to that of the UDP receiving module, but the calculation of the IP header checksum and the CRC cyclic redundancy check is added, and the analysis sequence of the UDP sending module is as follows: IP header checking, sending a preamble plus a frame start delimiter, sending an Ethernet frame header, sending an IP header, sending a UDP header, sending UDP data, namely valid data, and sending a CRC check value;
the input effective data is 32-bit data, the GMII interface is an 8-bit data interface, so that the UDP transmission module (namely the test result back transmission module) finishes the function of converting the 32-bit data into the 8-bit data, and the UDP transmission state jump flow chart is shown in figure 6.
The specific implementation process of the test result feedback module is as follows:
firstly, the field synchronous rising edge of the HDMI2 is acquired in a beating mode, the current nixie tube counter value is read when each field synchronous rising edge arrives, the time stamp of the previous frame is refreshed, and the time stamps of all data packets belonging to the same frame are the same. Because the pixel clock and the Ethernet transmit clock are different, an asynchronous FIFO is generated to buffer the pixel data and the time stamp so as not to cause data loss. The network port is returned to the gigabit network, and the HDMI2 receives 1920x1080 pixels per frame, if all the pixels are returned, the bit number is far more than the Ethernet bandwidth, and the FIFO overflows. Therefore, only the nixie tube display part which is necessary for delay calculation, namely the pixel at the left upper corner of the display is returned, two counters are arranged to count the row coordinates and the field coordinates respectively, and the value of the counter is used for screening the return range of the nixie tube at the left upper corner.
The UDP is set to 32 bits of sending data for each reading, wherein the first 8 bits are the RGB pixel information of which the current pixel is arranged in a row and the last 24 bits are 8 bits respectively. One packet returns 400 x 32 bits of data, where the pixel return range is 399x256, and the function is accomplished with two counters set. The last data of each packet is the backhaul timestamp of the frame. The pixel data and the time stamp are sequentially stored into the FIFO by taking the pixel clock as a period, the input and the output of the pixel data and the time stamp are 32 bits, and the UDP transmission data is enabled to be valid only when the data in the FIFO reaches 400 x 32 bits, namely, the transmission of one packet of data is started. In order to facilitate discrimination between each frame and the pixels and the time stamp, at the time of 32-bit data input, the first eight bits of the pixel data are set to the number of lines where the current data is located, i.e., from 0 to 255, and the first eight bits of the time stamp are all set to 1. The UDP Ethernet clock is used for sending 8-bit data each time, and generating a request data input signal when the 32-bit data is sent, and connecting the request data input signal with FIFO read enable to enable the FIFO output to be synchronous with the UDP input, thus completing the process of sending the UDP packet back to the upper computer.
The display mainly comprises the following functional modules:
video information display module: and under the drive of the FPGA, displaying the video with the added image watermark through an HDMI1 interface for acquisition of a system to be tested.
Example two
A video communication system delay test method (namely a video communication system delay test method based on image watermark) using the test apparatus of the first embodiment
The technical problems to be solved by the invention are realized by the following technical scheme:
a video communication system delay test method based on image watermarking includes the following steps:
step one: preprocessing the video information through the testing equipment, adding a digital watermark to each frame of image information in the video information, and driving a display to display the video information with the added image watermark. Wherein the image watermark comprises three anchor points and timestamp information T when the frame image is output to a display 1 。
In this step, the video information is preprocessed, that is, an analog four-bit nixie tube is added to the upper left corner of each frame of image of the video to be transmitted, the area size is 200 x 320, the background is white, three positioning points are included, the size is 40 x 40, the background area of the nixie tube is pure black, and the nixie tube is red, as shown in fig. 2.
The FPGA transmits video information to the display through the HDMI1 interface and drives the display to display the video information, the time stamp of the image sent to the display by the FPGA (namely, the time stamp of the display to display the frame image is driven to be ignored here, the display delay is ignored) is used as the digital watermark of the frame image information, and the digital watermark is displayed at the upper left corner in a nixie tube mode; the design delay test precision is 1ms, and the design delay range is 2.5s, namely 2500ms. The display range of the nixie tube is 0-2500.
Step two: the system to be tested collects the video information of the display and transmits the video information to the testing equipment.
After the system to be tested collects the video information on the display, the video information is transmitted to the receiving module of the testing equipment through the network port.
Step three: the testing equipment acquires video information returned by the system to be tested and records time stamp information T of each received frame of image 2 。
In this step, the timestamp corresponding to each frame of image of the video received by the test device through the HDMI2 interface is the timestamp information T returned by the frame of image 2 。
Step four: the testing equipment processes the video information returned by the system to be tested, and determines a time stamp T corresponding to the digital watermark in each frame of image through a locating point 1 And for time stamp information T 1 Performing recognition recovery;
in this step, the delay test system returns the system under test to the testAnalyzing the transmitted image data to obtain the image data of each frame of video signal, and recovering the time stamp T of the frame of image when the frame of image is displayed according to the image digital watermark information of each frame of image 1 。
The process of identifying the image watermark is as follows: firstly, determining a nixie tube position area through three positioning points, determining the specific position of the nixie tube, then cutting the nixie tube area into four independent nixie tubes, identifying the digital information of each nixie tube by adopting a threading method, and finally obtaining time stamp information T represented by the nixie tube 1 。
Step five: by calculating time stamp information T for each frame of image as received by the test device 2 Timestamp information T corresponding to the digital watermark of the frame image 1 Obtaining the video communication delay of the system to be tested, namely the video communication delay value of the system to be tested is T 2 -T 1 。
The above is only a preferred embodiment of the present invention, and the protection scope of the present invention is not limited to the above examples, and all technical solutions belonging to the concept of the present invention belong to the protection scope of the present invention. It should be noted that modifications and adaptations to the invention without departing from the principles thereof are intended to be within the scope of the invention as set forth in the following claims.

Claims (7)

1. The video communication system delay test method based on the image watermark is characterized by comprising the following steps:
step one: the testing equipment preprocesses the video information; adding a digital watermark to each frame of image information in the video information, and driving a display to display the video information added with the image watermark; the digital watermark comprises a plurality of positioning points and timestamp information T when the frame image is output through an interface 1 ；
Step two: the system to be tested collects video information of the display and transmits the video information to the testing equipment;
step three: the testing equipment acquires video information returned by the system to be tested and records time stamp information T of each received frame of image 2 .
Step four: the testing equipment processes the video information returned by the system to be tested, and determines a time stamp T corresponding to the digital watermark in each frame of image through a locating point 1 And for time stamp information T 1 Performing recognition recovery;
step five: by calculating time stamp information T for each frame of image as received by the test device 2 Timestamp information T corresponding to the digital watermark of the frame image 1 And obtaining the video communication delay of the system to be tested.
2. A video communication system delay test device based on image watermarking, characterized in that: the system comprises an upper computer, an FPGA and a display, wherein the upper computer and the display are respectively in communication connection with the FPGA, and the FPGA is also in communication connection with a system to be tested;
the upper computer is used for sending initial video information, receiving the video information returned by the identification FPGA, and calculating the video communication delay of the system to be tested;
the FPGA is used for receiving initial video information sent by the upper computer, adding watermark information to the video information, then sending the video information to the display, and driving the display to display the video information added with the watermark information; the FPGA is also used for receiving video information returned by the system to be tested and returning the video information to the upper computer;
the display is used for receiving video information sent by the FPGA and displaying the video information for acquisition of a system to be tested;
the upper computer comprises a communication module, an image recognition module and a delay calculation module;
the communication module is used for realizing information transmission between the upper computer and the FPGA;
the image recognition module is used for recognizing watermark information of each frame of image in video information sent back by the FPGA and obtaining a time stamp T in the watermark information of each frame of image 1 ；
The delay calculation module is used for calculating a time stamp T when the FPGA receives one frame of image in the video information returned by the system to be tested 2 And a time stamp T contained in watermark information in the frame image 1 Calculating to obtain video communication delay of the system to be tested;
the FPGA comprises a timer module and an image preprocessing module
The timer module is used for acquiring a time stamp of the current frame image when the current frame image is received or transmitted;
the image preprocessing module is used for adding watermark information to each frame of image in the video information, wherein the watermark information comprises a plurality of positioning points and a time stamp T when the FPGA sends the current frame of image 1 ；
3. The image watermark based video communication system delay test apparatus of claim 2, wherein: the watermark information comprises 3 anchor points.
4. A video communication system delay test apparatus based on image watermarking as claimed in claim 3, characterized in that: the upper computer also comprises a result display module and a communication configuration module; the result display module is used for displaying delay information of the current frame image and video information which is received in real time and returned by the system to be tested through the FPGA; and the communication configuration module is used for starting communication between the upper computer and the FPGA.
5. The image watermark based video communication system delay test apparatus of claim 4, wherein: and the communication module uses a UDP communication protocol as an information transmission protocol of the upper computer and the FPGA.
6. The image watermark based video communication system delay test apparatus of claim 5, wherein: the FPGA further comprises a DDR3 control module, a DDR storage module, a UART serial port module, an ETH network port module, a high-speed display driving module and a test result feedback module;
the DDR3 control module is used for screening out required data information according to a serial port instruction output by the UART serial port module and controlling the high-speed display driving module to display the data information on a display; the DDR3 also determines the burst length and the address maximum value of the DDR memory module;
the DDR storage module comprises an MIG IP core module, a read-write module and a FIFO scheduling module;
the MIG IP core module is used for connecting the peripheral equipment and the FPGA;
the read-write module is used for interaction between the MIG IP core module and the DDR3 read-write command and read-write address;
the FIFO scheduling module is used for converting the input data bit width of the external equipment into MIGIP core bit width and converting DDR3 read data bit width into the input data bit width of the external equipment;
the UART serial port module is used for realizing communication of an upper computer or a system to be tested;
the EHT network port module is used for receiving video information of the upper computer and the system to be tested;
the high-speed display driving module is used for driving the display to display corresponding image or video information according to the serial port instruction of the UART serial port module;
the test result feedback module is used for feeding back the video information fed back by the system to be tested and the time stamp obtained by the timer module when the video information is received to the upper computer.
7. The image watermark based video communication system delay test apparatus of claim 6, wherein: the FPGA is connected with the display through an HDMI1 interface and connected with the system to be tested through an HDMI 2.
CN202211637320.9A 2022-12-16 2022-12-16 Video communication system delay test method and equipment based on image watermark Pending CN116208759A (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118192484A (en) * 2024-01-29 2024-06-14 北京蓝天航空科技股份有限公司 Delay test method for flight simulator, electronic equipment and storage medium

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN118192484A (en) * 2024-01-29 2024-06-14 北京蓝天航空科技股份有限公司 Delay test method for flight simulator, electronic equipment and storage medium

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