JP2004326975A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To improve the security of the information stored in a nonvolatile memory sealed in a semiconductor element chip. <P>SOLUTION: A chip 12 provided with the nonvolatile memory and a chip 13 for making the chip 12 normally operate are provided, and a control signal for controlling the nonvolatile memory to be mounted on the chip 12 is inputted to the chip 12 through the chip 13. The chips 12 and 13 are respectively provided with an inverter circuit for inverting the polarity of an optional control signal among a plurality of control signals inputted from an external circuit. Only when the control signal is inputted to the nonvolatile memory through both inverter circuits of the chips 12 and 13, the control signal becomes a normal signal to the nonvolatile memory. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device having a nonvolatile memory and a method of manufacturing the same, and more particularly, to a semiconductor device capable of maintaining confidentiality of information in the nonvolatile memory when the semiconductor device is removed from a substrate. It is.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, a semiconductor device chip provided with a circuit configuration such as a nonvolatile memory (hereinafter, simply referred to as a chip) is used from a viewpoint of protection from an external environment and a viewpoint of enabling handling when the semiconductor device chip is used. The semiconductor device is sealed with a plastic package or the like to form a semiconductor device.
[0003]
FIG. 5 shows an example of a semiconductor device provided with a nonvolatile memory as a circuit configuration of a semiconductor element chip. A semiconductor device 101 shown in FIG. 5 is a package type semiconductor device in which a chip 103 is sealed in a package 102 made of an epoxy resin. The chip 103 is fixed on a die pad 104 via a silver paste 105, and a pad 106 included in the chip 103 is connected to a lead wire 107 connected to the outside of the package 102 via a gold wire 108.
[0004]
A general manufacturing method of the package type semiconductor device is as follows. First, the silver paste 105 is formed on the fixed surface of the die pad 104, and the chip 103 is further placed on the silver paste 105 and pressed while heating to about 160 to 170 ° C. As a result, the chip 103 is fixed on the die pad 104 by pressure bonding due to thermal solidification of the silver paste 105. Thereafter, the pad 106 provided on the chip 103 and the lead wire 107 are wire-bonded with the gold wire 108. Finally, the package 103 is formed by sealing the chip 103 with an epoxy resin.
[0005]
As a technique for a package-type semiconductor device, for example, a resin-sealed semiconductor device disclosed in Patent Document 1 is cited. In this technique, a heat spreader is mounted under a pellet mounting table (corresponding to a die pad 104) on which a semiconductor pellet (corresponding to a chip 103) is mounted. As a result, thermal resistance is reduced, and a product with high power consumption can be supplied in a plastic package. Also, by making the resin thickness uniform, cracks and warpage of the package are reduced, and high reliability can be obtained.
[0006]
Also, for example, Patent Document 2 discloses a semiconductor device including a plurality of chips. According to this technology, when mounting a plurality of semiconductor elements having different thicknesses at the time of flip-chip mounting, the thickness of the radiation fins is changed according to the thickness of each semiconductor element at a portion where each semiconductor element is mounted. It is possible to form recesses differently so that adhesive connection can be made reliably.
[0007]
By the way, in the conventional semiconductor device 101 shown in FIG. 5, there is a possibility that information in the nonvolatile memory of the chip 103 sealed in the semiconductor device 101 may be analyzed. To analyze the chip 103, the package 102 is first opened so that the chip 103 can be observed.
[0008]
Here, a polyimide film (not shown) is usually applied on the chip 103 in a thickness of 50 to 100 μm in order to prevent malfunction due to α rays. Further, when the chip 103 is sealed, the package 102 is formed by covering the chip 103 with an epoxy resin or the like as described above. Therefore, simply opening the package 102 cannot observe the chip 103 with a microscope, making it impossible to analyze information of the nonvolatile memory.
[0009]
[Patent Document 1]
JP-A-5-212262
[0010]
[Patent Document 2]
JP-A-6-224334
[0011]
[Problems to be solved by the invention]
However, in the above-described conventional configuration, the polyimide film or the epoxy resin that covers (or seals) the chip 103 can be removed by an etchant treatment using fuming nitric acid, sulfuric acid, or the like. Therefore, if the above-mentioned resin or the like is peeled off by the etchant treatment, the chip 103 alone can be obtained. Obviously, the chip 103 can be observed from the surface, or the probe can be directly contacted with the chip 103 to obtain chip characteristics. Circuit analysis becomes possible.
[0012]
Therefore, according to the configuration and the packaging method of the conventional semiconductor device 101, when the resin of the package 102 or the like is peeled off from the chip 103 to form the chip 103 alone, a third party stores information in the nonvolatile memory mounted on the chip. Analysis can be easily performed, and confidentiality cannot be maintained.
[0013]
Here, in the technology of Patent Document 1, although the reliability and performance of the semiconductor device can be improved, no consideration is given to the above-described analysis blocking of the chip 103. Also, in the technique of Patent Document 2 described above, when manufacturing a semiconductor device having a plurality of chips mounted thereon, a semiconductor device can be securely bonded and has no bonding failure, but analysis prevention is not considered at all.
[0014]
The present invention has been made in order to solve the above problems, and has as its object the application information, personal information, transaction information, and the like stored in a non-volatile memory sealed inside a semiconductor element chip. It is an object of the present invention to provide a package type semiconductor device capable of preventing and improving the leakage and falsification of money information and the like and the copying and imitation due to the leakage of application information.
[0015]
[Means for Solving the Problems]
According to another aspect of the present invention, there is provided a semiconductor device in which a semiconductor element chip having a nonvolatile memory is sealed in a package and mounted on an external circuit. Between a memory and an external terminal, a signal switching means for arbitrarily switching the polarity of a control signal for controlling the nonvolatile memory, a memory chip including the nonvolatile memory, and a separate chip from the memory chip And a control chip for operating the memory chip normally.
[0016]
According to the above configuration, the control signal for controlling the nonvolatile memory is input from the external terminal and passes through the signal switching means until the control signal reaches the nonvolatile memory. The polarity of the control signal can be arbitrarily switched while passing through the signal switching means. However, when the control signal is input to the nonvolatile memory, the polarity is appropriate.
[0017]
When a third party who attempts to analyze the semiconductor device illegally opens the package of the semiconductor element chip, the memory chip is separated from the control chip and can be obtained by itself.
[0018]
For this reason, even if a control signal for analysis is input to the pad for signal input of the memory chip, the control signal passes only a part of the signal switching means and is inappropriate when input to the nonvolatile memory. Polarity. As a result, the memory chip alone cannot operate the nonvolatile memory properly, and the security of the nonvolatile memory can be improved.
[0019]
In the semiconductor device, the signal switching means includes a first inverter circuit provided on the memory chip and a second inverter circuit provided on the control chip, and is input from an external circuit. Among the plurality of control signals, an arbitrary control signal whose polarity is inverted by the second inverter circuit, and a control signal whose polarity is inverted by the second inverter circuit, have its polarity inverted by the first inverter circuit. It is possible to adopt a configuration that is inverted again.
[0020]
According to the above configuration, of the plurality of control signals input from the external circuit, an arbitrary control signal is first inverted in polarity by the second inverter circuit, and is inverted in polarity by the second inverter circuit. The polarity of the control signal is inverted again by the first inverter circuit. Therefore, when a control signal having the specified polarity is input to the semiconductor device to the nonvolatile memory, the control signal has the specified polarity even at the time of input to the nonvolatile memory.
[0021]
On the other hand, even when a control signal having the specified polarity is input to the non-volatile memory for a single memory chip, the control signal passes only through the first inverter circuit. Is inverted and input to the nonvolatile memory. For this reason, in the first inverter circuit, the security of the nonvolatile memory can be improved by concealing which control signal is inverted in polarity.
[0022]
According to another embodiment of the present invention, there is provided a semiconductor device comprising: a memory chip having a nonvolatile memory; and a control chip for operating the memory chip normally. A control signal for controlling the nonvolatile memory mounted on the chip is input to the memory chip via the control chip, and only when the control signal is input to the memory chip via the control chip, It is characterized in that it becomes a normal signal to the nonvolatile memory.
[0023]
According to the configuration, when a third party who tries to perform an illegal analysis of the semiconductor device disassembles the semiconductor element and obtains the memory chip by itself, a signal input to the memory chip is performed. Even if a control signal for analysis is input to the pad portion of the non-volatile memory, the control signal is not input to the memory chip via the control chip, so that the signal does not become a normal signal to the non-volatile memory, and the security of the non-volatile memory Can be improved.
[0024]
Further, in the semiconductor device, the memory chip includes a first inverter circuit that inverts the polarity of an arbitrary control signal among a plurality of control signals input to the nonvolatile memory. The chip for use can be configured to include a second inverter circuit that inverts the polarity of the same control signal as the control signal whose polarity is inverted in the first inverter circuit.
[0025]
According to the above configuration, of the plurality of control signals input to the nonvolatile memory, the polarity of an arbitrary control signal is first inverted by the second inverter circuit, and the control signal is inverted by the second inverter circuit. The polarity of the control signal whose polarity has been inverted is inverted again by the first inverter circuit. Therefore, when a control signal having the specified polarity is input to the semiconductor device to the nonvolatile memory, the control signal has the specified polarity even at the time of input to the nonvolatile memory.
[0026]
On the other hand, even when a control signal having the specified polarity is input to the non-volatile memory for a single memory chip, the control signal passes only through the first inverter circuit. Is inverted and input to the nonvolatile memory. For this reason, in the first inverter circuit, the security of the nonvolatile memory can be improved by concealing which control signal is inverted in polarity.
[0027]
Further, in the semiconductor device, the first inverter circuit may be mixedly mounted in another logic circuit in the memory chip.
[0028]
Alternatively, in the semiconductor device, the first inverter circuit may have a configuration in which an uppermost layer is shielded.
[0029]
According to the above configuration, in the first inverter circuit having the function of improving security in the semiconductor device, it is difficult to determine which part of the memory chip is the first inverter circuit, or it is difficult to determine from the outside whether the part is the first inverter circuit. Since it is difficult to distinguish the configuration of the one inverter circuit, the analysis prevention level can be improved.
[0030]
BEST MODE FOR CARRYING OUT THE INVENTION
[Embodiment 1]
An embodiment of the present invention will be described below with reference to FIGS.
[0031]
As shown in FIGS. 1 and 2, the semiconductor device 10 according to the first embodiment includes a semiconductor element chip 12 (hereinafter, simply referred to as a chip) and a chip 13 which are encapsulated in a package 11. It has two chips. At this time, the chip 12 is a memory chip having a nonvolatile memory, and the chip 13 is a control chip provided with a circuit for transmitting a signal for operating the chip 12 normally.
[0032]
As a method of manufacturing the semiconductor device 10, first, the chip 12 is fixed on the die pad 14 via the silver paste 15. Next, the chip 13 is fixed on the same die pad 14 beside the chip 12 via the silver paste 15. In the method of fixing the chips 12 and 13, the chips 12 and 13 are placed and pressed while being heated to about 160 to 170 ° C., so that the chips 12 and 13 are solidified on the die pad 14 by thermal solidification of the silver paste 15. It is fixed by crimping.
[0033]
When the chips 12 and 13 are fixed on the die pad 14, the pad portions 16 of the chip 12 and the lead wires 17 are connected by wire bonding via wires 18 such as gold wires. Further, the pad section 16 of the chip 13 and the pad section 16 and the lead wire 17 of the chip 12 are connected by wire bonding via wires 18 respectively.
[0034]
When the chips 12 and 13 and the lead wires 17 are connected in this manner, finally, the die pad 14 on which the chips 12 and 13 are mounted and the end of each lead wire 17 on the connection side with the chip 12 and 13 are connected by wires. The semiconductor device 10 is completed by sealing the package 18 together with the package 11. At this time, the other end of each lead wire 17 (the side not connected to the pad portion 16 of the chips 12 and 13) is exposed outside the package 11, and is used for mounting the semiconductor device 10 in an external circuit.
[0035]
Incidentally, as the package 11, a plastic package used in a conventional semiconductor device can be preferably used. As a material of the plastic package, an epoxy resin is particularly preferably used, but the present invention is not limited to this.
[0036]
As described above, the semiconductor device 10 according to the present embodiment includes the chip 12 having a nonvolatile memory and the chip 13 provided with a circuit for transmitting a signal for operating the chip 12 normally. I have. That is, signal switching means are dispersedly incorporated in the chips 12 and 13 so that the chip 12 does not operate normally unless the chip 12 receives a signal via the chip 13. The details of the signal switching means will be described below.
[0037]
As a configuration example of the signal switching means, there is a circuit configuration as shown in FIG. First, in a chip 12 on which a flash memory, which is a nonvolatile memory, is mounted, a first inverter circuit 12a is provided on a wiring from a flash memory portion to a pad portion.
[0038]
The first inverter circuit 12a includes an inverting wiring for inverting the polarity of a signal by an inverter between each terminal and an input pad 16 at each of terminals for taking in a signal input from the outside into the flash memory. A pair of a non-inverting wiring and a non-inverting wiring for directly transmitting a signal of the polarity input to the pad 16 to the terminal of the flash memory are provided.
[0039]
In the chip 12, each signal input to the pad 16 is input to the terminal of the flash memory through only one of the inversion wiring and the non-inversion wiring in the first inverter circuit 12a.
[0040]
That is, the chip 12 also has a PLA (Programmable Logic Array: not shown) at the same time, and in the first inverter circuit 12a, each signal input to the pad 16 is transmitted by the security signal given from the PLA. Which of the paired inversion wiring and non-inversion wiring is applied to the terminal of the flash memory can be switched. That is, whether or not the polarity of each of the signals passing through the first inverter circuit 12a is inverted is arbitrarily set by the PLA.
[0041]
Next, in the control chip 13, a second inverter circuit 13 a is connected to the wiring from the input pad connected to the lead wire 17 to the output pad connected to the pad of the chip 12. Is provided. The second inverter circuit 13a has a configuration similar to that of the first inverter circuit 12a provided in the chip 12.
[0042]
That is, also in the second inverter circuit 13a, between each input pad 16 and each output pad 16, an inversion wiring for inverting the polarity of the signal by the inverter and the polarity input to the input pad 16 are provided. And a non-inverting wiring for transmitting the signal as it is to each output pad 16 as a pair.
[0043]
The chip 13 also has a PLA (Programmable Logic Array: not shown) simultaneously mounted thereon, and the second inverter circuit 13a inverts the polarity of each signal passing through the second inverter circuit 13a. Whether or not this is set is arbitrarily set by the PLA.
[0044]
When performing the wire bonding for mounting the chips 12 and 13, a wire is drawn from the lead wire 17 to the input pad 16 of the chip 13, and then the output pad 16 of the chip 13 is connected to the pad of the chip 12. Pull the wire to 16. Regarding the connection between the chip 12 and the chip 13, the polarity inversion setting in the second inverter circuit 13a can be determined with respect to the first inverter circuit 12a by arbitrarily pulling wire bonding between these chips. It is preferable to make it unclear as to whether or not they correspond.
[0045]
The signal switching means including the first inverter circuit 12a and the second inverter circuit 13a is, for example, a signal necessary for operating a flash memory, such as RP (reset), WP (write protect), and CE (chip enable). ), RB (ready busy), OE (output enable), and WE (write enable).
[0046]
Here, for example, in the first inverter circuit 12a, of the signals of RP, WP, CE, RB, OE, and WE, the polarities of the signals of RP and OE are inverted, and the polarities of the other signals are reversed. Set not to be inverted. In this case, also in the second inverter circuit 13a, of the signals of RP, WP, CE, RB, OE, and WE, the polarities of the signals of RP and OE are inverted, and the polarities of the other signals are reversed. Set not to be inverted. Of course, in the first inverter circuit 12a and the second inverter circuit 13a, inverting the polarity of the RP and OE signals is merely an example, and it is possible to arbitrarily set which signal is inverted in polarity. .
[0047]
Therefore, when the signals of RP, WP, CE, RB, OE, and WE are input with the polarities as specified at the time of input from the lead wire 17, the signals of RP, OE are output from the second inverter circuit 13a. The polarity is once inverted, but thereafter, the polarity is inverted again in the first inverter circuit 12a, so that the polarity is returned to the original polarity. In addition, the polarity of signals other than RP and OE is not inverted when passing through either the second inverter circuit 13a or the first inverter circuit 12a.
[0048]
Therefore, when the RP, WP, CE, RB, OE, and WE signals having the specified polarities are input from the lead wire 17, the above signals are input to the flash memory with the specified polarities. As a result, the flash memory operates normally.
[0049]
On the other hand, when the package 11 is opened in the semiconductor device 10 according to the present embodiment in order to illegally analyze the storage contents of the flash memory mounted on the chip 12, Are taken out alone.
[0050]
When the chip 12 becomes a single unit as described above, when the signals of RP, WP, CE, RB, OE, and WE are input to the chip 12 in order to analyze the storage contents of the flash memory mounted on the chip 12, These signals will be input via the pads 16 of the chip 12.
[0051]
In this case, even if the signals of RP, WP, CE, RB, OE, and WE have polarities as specified, some of these signals (RP and OE in the above example) are converted by the first inverter circuit 12a. The polarity is reversed. Therefore, it is not possible to input a signal with an appropriate polarity to all signals of RP, WP, CE, RB, OE, and WE to the flash memory, and the flash memory does not operate normally. It becomes impossible to perform the analysis.
[0052]
As described above, the semiconductor device 10 according to the first embodiment has a configuration in which a plurality of semiconductor element chips are held in the package 11, and the semiconductor element chip controls the chip 12 having the nonvolatile memory and the semiconductor chip. It is divided into a chip 13. Only when the plurality of chips are arranged and each chip is correctly connected, the nonvolatile memory in the chip 12 operates normally and the information in the nonvolatile memory can be read.
[0053]
Further, in this configuration, when the semiconductor element chip is separated from the semiconductor device 10 and the chip 12 and the chip 13 become a single unit, the nonvolatile memory mounted on the chip 12 does not operate normally, and Protection of information in the memory can be improved.
[0054]
In other words, in the chip 12 including the nonvolatile memory, the nonvolatile memory cannot operate normally unless the information of the security signal given from the PLA to the first inverter circuit 12a is understood. Of course, the information of the security signal is known only by the manufacturer, and when the chip 12 is peeled and becomes a single chip, the information stored in the non-volatile memory is decrypted, and even if the probe is executed to perform the falsification, When inputting a signal to the pad 16 of the chip 12, it is not clear what signal should be input. Therefore, in the semiconductor device according to the present embodiment, it is possible to improve fraud prevention at the input level of the security signal.
[0055]
Further, the semiconductor device described above has a two-chip configuration including a memory chip having a nonvolatile memory (that is, chip 12) and a control chip (that is, chip 13) for operating the memory chip normally. However, the semiconductor device of the present invention is not limited to the above-described two-chip configuration, and may be further configured with a multi-chip configuration. That is, chips can be divided according to circuits such as a memory chip, an SRAM, and a logic circuit.
[0056]
[Embodiment 2]
Embodiment 2 of the present invention will be described.
[0057]
In the first embodiment, an inverter circuit is provided in both the memory chip on which the nonvolatile memory is mounted and the control chip, and these inverter circuits convert the polarity of the input signal to form a single memory chip. At this time, the operation of the nonvolatile memory is disabled to improve fraud prevention. On the other hand, the second embodiment proposes a method for further improving the analysis prevention of the nonvolatile memory.
[0058]
For example, in the chip 12, which is a memory chip, the first inverter circuit 12a is mixed and arranged in a logic unit such as an SRAM around the nonvolatile memory circuit. Thus, by mixing the first inverter circuit 12a into the logic unit, it is difficult to determine which part of the chip 12 is the first inverter circuit 12a. Furthermore, the analysis prevention level can be improved by further complicating the configuration of the first inverter circuit 12a, for example, by increasing the input level of the security signal provided from the PLA to the first inverter circuit 12a.
[0059]
Further, in the semiconductor device of the present invention, the uppermost layer of the inverter circuit portion (the first inverter circuit 12a or the second inverter circuit 13a) constituting the security circuit is covered with MR (metal layer: for example, TiN). You can also. In this case, it is difficult to recognize the configuration of the security circuit from the outside, and it is possible to further improve fraud prevention.
[0060]
[Embodiment 3]
Embodiment 3 of the present invention will be described.
[0061]
Embodiments 1 and 2 illustrate a configuration in which the semiconductor device 10 is a package type semiconductor device. On the other hand, the third embodiment exemplifies a configuration in which the present invention is applied to a flip-chip type semiconductor device and the same circuit analysis can be prevented. As an example, the semiconductor device according to the third embodiment has a structure as shown in FIG.
[0062]
The semiconductor device 20 shown in FIG. 4 has a configuration in which a chip 21 and a chip 22 are mounted on a glass epoxy resin substrate 23. Note that the chip 21 is a memory chip on which a nonvolatile memory is mounted, similarly to the chip 12 in the first embodiment. The chip 22 is a control chip for operating the chip 21 normally, similarly to the chip 13 in the first embodiment.
[0063]
In the glass epoxy resin substrate 23, an output wiring (not shown) to the outside is formed by thin copper so as to match the pads of the chips 21 and 22. Gold bumps 24 are formed on the pads of the chip 21 and the chip 22.
[0064]
Next, the chips 21 and 22 and the glass epoxy resin substrate 23 are overlapped with each other via the anisotropic conductive adhesive 25 so that the pad portions of the chips 21 and 22 and the wiring of the glass epoxy resin substrate 23 match. Pressing while heating to about 200 ° C. Thus, the chips 21 and 22 are pressure-fixed on the glass epoxy resin substrate 23 by thermal coagulation of the anisotropic conductive adhesive 25. Thereby, wiring between the chip 21 and the chip 22 is also performed. Finally, the package 21 is formed by sealing the chip 21 and the chip 22 with an epoxy resin.
[0065]
In the semiconductor device having the above-described configuration, if the first and second inverter circuits are provided in the chip 21 and the chip 22, similarly to the semiconductor devices of the first and second embodiments, the chip 21 is peeled off to be a single chip. At this time, information analysis of the non-volatile memory can be prohibited to improve fraud prevention.
[0066]
Even in the case of such a flip-chip configuration, the semiconductor device of the present invention is not limited to the above-described two-chip configuration, but may be a multi-chip configuration.
[0067]
【The invention's effect】
As described above, a semiconductor device according to the present invention includes a semiconductor element chip having a nonvolatile memory encapsulated in a package, and is mounted on an external circuit and used. A signal switching means for arbitrarily switching the polarity of a control signal for controlling the nonvolatile memory, a memory chip provided with the nonvolatile memory, and a memory chip provided separately from the memory chip. This is a configuration in which a control chip for operating the chip normally is distributed and provided.
[0068]
Therefore, when a third party who attempts to perform an unauthorized analysis of the semiconductor device opens the package of the semiconductor element chip, the memory chip is separated from the control chip and obtained as a single unit. Even if a control signal for analysis is input to the signal input pad portion of the memory chip, the control signal passes only a part of the signal switching means, and has an inappropriate polarity at the time of input to the nonvolatile memory. . As a result, the memory chip alone cannot operate the nonvolatile memory normally, and the security of the nonvolatile memory can be improved.
[0069]
In the semiconductor device, the signal switching means includes a first inverter circuit provided on the memory chip and a second inverter circuit provided on the control chip, and is input from an external circuit. Among the plurality of control signals, an arbitrary control signal whose polarity is inverted by the second inverter circuit, and a control signal whose polarity is inverted by the second inverter circuit, have its polarity inverted by the first inverter circuit. It is possible to adopt a configuration that is inverted again.
[0070]
Therefore, even when a control signal having the specified polarity is input to the non-volatile memory for a single memory chip, the control signal passes only through the first inverter circuit. Is inverted and input to the nonvolatile memory. For this reason, in the first inverter circuit, it is possible to improve the security of the nonvolatile memory by concealing which control signal is inverted in polarity.
[0071]
Further, as described above, another semiconductor device of the present invention includes a memory chip including a nonvolatile memory, and a control chip for operating the memory chip normally, and is mounted on the memory chip. A control signal for controlling the nonvolatile memory is input to the memory chip via the control chip, and the control signal is supplied to the nonvolatile memory only when the control signal is input to the memory chip via the control chip. In this configuration, the signal becomes a normal signal.
[0072]
Therefore, when a third party who attempts to analyze the semiconductor device illegally dismantles the semiconductor element and obtains the memory chip alone, the signal input pad portion of the memory chip is Even if a control signal for analysis is input, the control signal is not input to the memory chip via the control chip, so that the signal does not become a normal signal to the nonvolatile memory and the security of the nonvolatile memory is improved. It has the effect of being able to.
[0073]
Further, in the semiconductor device, the memory chip includes a first inverter circuit that inverts the polarity of an arbitrary control signal among a plurality of control signals input to the nonvolatile memory. The chip for use can be configured to include a second inverter circuit that inverts the polarity of the same control signal as the control signal whose polarity is inverted in the first inverter circuit.
[0074]
Therefore, even when a control signal having the specified polarity is input to the non-volatile memory for a single memory chip, the control signal passes only through the first inverter circuit. Is inverted and input to the nonvolatile memory. For this reason, in the first inverter circuit, it is possible to improve the security of the nonvolatile memory by concealing which control signal is inverted in polarity.
[0075]
Further, in the semiconductor device, the first inverter circuit may be mixedly mounted in another logic circuit in the memory chip.
[0076]
Alternatively, in the semiconductor device, the first inverter circuit may have a configuration in which an uppermost layer is shielded.
[0077]
Therefore, in the first inverter circuit having the function of improving security in the semiconductor device, it is difficult to determine which part of the memory chip is the first inverter circuit, or the first inverter circuit is externally provided. This makes it difficult to discern what the configuration is, thereby providing an effect of improving the analysis prevention level.
[Brief description of the drawings]
FIG. 1 illustrates one embodiment of the present invention, and is a cross-sectional view illustrating a schematic configuration of a semiconductor device.
FIG. 2 is a plan view illustrating a schematic configuration of the semiconductor device.
FIG. 3 is a circuit diagram showing an example of a configuration of an inverter circuit provided in a semiconductor element chip in the semiconductor device shown in FIGS.
FIG. 4 illustrates another embodiment of the present invention, and is a cross-sectional view illustrating a schematic configuration of a semiconductor device.
FIG. 5 is a cross-sectional view illustrating a schematic configuration of a conventional semiconductor device.
[Explanation of symbols]
10.20 Semiconductor device
11.26 Package
12.21 chips (memory chips)
13.22 chip (control chip)
12a First inverter circuit
13a Second inverter circuit

Claims (6)

In a semiconductor device in which a semiconductor element chip having a nonvolatile memory is sealed in a package and used by being mounted on an external circuit,
Signal switching means for arbitrarily switching the polarity of a control signal for controlling the nonvolatile memory between the nonvolatile memory and an external terminal; a memory chip provided with the nonvolatile memory; And a control chip for operating the memory chip normally. The signal switching means,
A first inverter circuit provided on the memory chip, and a second inverter circuit provided on the control chip,
Among the plurality of control signals input from the external circuit, an arbitrary control signal whose polarity is inverted by the second inverter circuit and whose control signal is inverted by the second inverter circuit are the first control signal. 2. The semiconductor device according to claim 1, wherein the polarity is inverted again by an inverter circuit. A memory chip having a nonvolatile memory;
A control chip for operating the memory chip normally,
A control signal for controlling the nonvolatile memory mounted on the memory chip is input to the memory chip via the control chip, and the control signal is input to the memory chip via the control chip. Only a normal signal to a nonvolatile memory. The memory chip includes a first inverter circuit that inverts a polarity of an arbitrary control signal among a plurality of control signals input to the nonvolatile memory, and the control chip includes the first inverter circuit. 4. The semiconductor device according to claim 3, further comprising a second inverter circuit for inverting the polarity of a control signal having the same polarity as the control signal whose polarity is inverted by the inverter circuit. 5. The semiconductor device according to claim 2, wherein the first inverter circuit is mounted in another logic circuit in the memory chip. The semiconductor device according to claim 2, wherein the first inverter circuit has a top layer shielded.

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