JP2004325627A - Active matrix substrate and display device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an active matrix substrate capable of improving the aperture rates of pixels without reducing display quality. <P>SOLUTION: The active matrix substrate is provided with a substrate 1 and a thin film transistor and a capacity element 19 which are formed on the main surface of the substrate 1. The thin film transistor has a semiconductor layer including a channel area. The capacity element 19 has a dielectric film 4 for capacity and +- lower capacity electrode 3 and an upper capacity electrode 5 which are arranged so as to be opposed to each other through the dielectric film 4. The substrate has a recessed part 2 on its main surface and the main surface has an upper surface 1a, a base 2a for regulating the recessed part 2 and side faces 2b continued to the base 2a and the upper surface 1a. The capacity element 19 is arranged on the substrate side from the thin film transistor so as to be superposed to a channel area 7c of the thin film transistor when it is observed from a substrate direction and extended from at least a part of the base 2a of the recessed part 2 up to at least a part of the side faces 2b. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to an active matrix substrate, and more particularly, to an active matrix substrate including a thin film transistor and a capacitor.
[0002]
[Prior art]
An active matrix substrate used in an active matrix liquid crystal display device is generally provided with a thin film transistor (TFT) and a capacitor for each pixel. The TFT functions as a switching element, and a display signal is transmitted to the pixel electrode via the TFT in an ON state. The capacitor is provided so that a storage capacitor is added in parallel with the liquid crystal capacitor, prevents an unnecessary signal from leaking to the liquid crystal layer, holds a pixel potential, and prevents deterioration of display quality.
[0003]
Hereinafter, the configuration of the conventional active matrix substrate 1200 will be described with reference to FIGS. FIG. 12 shows a cross-sectional view of the active matrix substrate 1200, and FIG. 13 shows a partial plan view. FIG. 12 corresponds to BB ′ in FIG.
[0004]
In the active matrix substrate 1200, a lower light-shielding film 1103a of a predetermined shape is provided on a quartz substrate 1101, and a TFT semiconductor layer 1107 is provided on the lower light-shielding film 1103a via a first insulating film 1106. The TFT semiconductor layer 1107 includes a channel region 1107c, a source region 1107a, and a drain region 1107b. A gate oxide film 1108 is provided over the TFT semiconductor layer 1107, and a gate electrode 1109 is provided over the gate oxide film 1108. The gate electrode 1109, the source region 1107a, and the drain region 1107b constitute a TFT.
[0005]
In the active matrix substrate 1200, a capacitor for holding a pixel potential is provided adjacent to the TFT. The capacitor element includes a lower capacitor electrode 1103 formed of a part of the same layer as the TFT semiconductor layer 1107, a gate oxide film 1108 on the lower capacitor electrode 1103, and a lower capacitor electrode 1103 with the gate oxide film 1108 interposed therebetween. And an upper capacitor electrode 1105 provided so as to perform the operation.
[0006]
A second insulating film 1110 is provided to cover the gate electrode 1109 and the upper capacitor electrode 1105. Source contact holes 1111 and drain contact holes 1112 are provided in predetermined portions of the second insulating film 1110 and the gate oxide film 1108. A source electrode 1114 and a drain electrode 1115 are provided over the second insulating film 1110. The source electrode 1114 is electrically connected to the source region 1107a of the TFT via the source contact hole 1111. The drain electrode 1115 is electrically connected to the drain region 1107b of the TFT via the drain contact hole 1112. It is connected to the.
[0007]
A third insulating film 1116 is provided over the source electrode 1114 and the drain electrode 1115. In the third insulating film 1116, a pixel contact hole 1117 is provided in a predetermined region on the drain electrode 1115. A transparent pixel electrode 1118 is provided on the third insulating film 1116, and the transparent pixel electrode 1118 is electrically connected to the drain electrode 1115 through the pixel contact hole 1117.
[0008]
In general, when incident light or reflected light from the back surface of the substrate enters the channel region of the TFT semiconductor layer, there is a problem that a leakage current is generated at the time of off due to light excitation, thereby deteriorating the display quality of the liquid crystal display device. In order to improve display quality, high light shielding is required. Further, in order to improve the display quality, it is required to increase the capacitance of the capacitor. On the other hand, in order to satisfy the above requirements, there is a problem that the inter-pixel light-shielding region is enlarged and the pixel aperture ratio is reduced. Therefore, there is a problem that the improvement of the pixel aperture ratio and the improvement of the display quality cannot be achieved at the same time.
[0009]
In order to solve this problem, Patent Document 1 discloses a liquid crystal display device in which a capacitor and a channel region of a TFT semiconductor layer overlap with each other, and a capacitor is provided below the TFT semiconductor layer. In this liquid crystal display device, since the channel region of the TFT semiconductor layer is shielded from light by the capacitive element, the channel region is shielded from light while suppressing a decrease in the pixel aperture ratio, and a reduction in display quality can be suppressed.
[0010]
[Patent Document 1]
JP 2001-66638 A
[0011]
[Problems to be solved by the invention]
However, it is required to increase the pixel aperture ratio without deteriorating the display quality, and the active matrix substrate disclosed in Patent Document 1 cannot sufficiently meet this requirement.
[0012]
In the above, the problem relating to the liquid crystal display device has been described as an example, but the above requirements are not limited to the liquid crystal display device, but are common to other display devices such as organic EL elements.
[0013]
The present invention has been made in view of the above problems, and has as its object to provide an active matrix substrate that can improve the pixel aperture ratio without lowering display quality.
[0014]
[Means for Solving the Problems]
An active matrix substrate of the present invention is an active matrix substrate including a substrate, a thin film transistor provided on a main surface of the substrate, and a capacitor, wherein the thin film transistor has a semiconductor layer including a channel region, The element has a dielectric film for capacitance, a lower capacitance electrode and an upper capacitance electrode arranged to face each other with the dielectric film for capacitance interposed therebetween, and the substrate has a concave portion on the main surface, The main surface has a top surface, a bottom surface that defines the recess, and a side surface that is continuous with the bottom surface and the top surface, and the capacitor element is, when viewed from the substrate direction, the thin film transistor of the thin film transistor. The capacitor is disposed closer to the substrate than the thin film transistor so as to overlap with a channel region, and the capacitor is at least a part of the bottom surface of the recess. And it extends to at least a portion of the side surface, thereby the above problems can be solved.
[0015]
The substrate may be formed of quartz.
[0016]
The substrate may include a plate having no concave portion and an insulating film provided on the plate, and the concave portion may be provided in the insulating film.
[0017]
The channel layer of the thin film transistor may be disposed inside the concave portion, and may be disposed closer to the bottom surface than an upper end of the capacitive element provided on at least a part of the side surface of the concave portion.
[0018]
The capacitive element may extend from at least a part of the bottom surface of the concave portion to at least a part of the upper surface via the side surface.
[0019]
The channel region of the thin film transistor is disposed on the capacitor with an insulating layer interposed therebetween, and a height from the bottom surface of the concave portion to the top surface of the substrate is the capacitance, the semiconductor layer, and the insulating layer. It is preferably larger than the sum of the thicknesses of the layers.
[0020]
It is preferable that the capacitance element is formed on the entire bottom surface and the side surface of the concave portion.
[0021]
It is preferable that at least one of the upper capacitance electrode and the lower capacitance electrode has a light shielding property.
[0022]
At least one of the upper capacitor electrode and the lower capacitor electrode is, for example, tungsten, molybdenum, tantalum, chromium, titanium, tungsten silicide, molybdenum silicide, tantalum silicide, chromium silicide, titanium silicide, tungsten alloy, molybdenum. A single layer or a stack of two or more layers including at least one selected from the group consisting of an alloy, a tantalum alloy, a chromium alloy, a titanium alloy, amorphous silicon doped with impurities, and polycrystalline silicon doped with impurities. Consists of a membrane.
[0023]
The capacitor dielectric film is formed of, for example, one of a silicon oxide film, a silicon nitride film, and a stacked film of a silicon oxide film and a silicon nitride film.
[0024]
In one embodiment, the semiconductor layer includes a source region and a drain region arranged to face each other with the channel region interposed therebetween, and further, between the channel region and the source region, and between the channel region and the channel region. A low-concentration impurity region is provided between the region and the drain region.
[0025]
A display device according to the present invention includes the above-described active matrix substrate and a display medium layer disposed on the active matrix substrate.
[0026]
The display medium layer includes, for example, a liquid crystal material.
[0027]
The display device of the present invention is, for example, a projection type liquid crystal display device.
[0028]
BEST MODE FOR CARRYING OUT THE INVENTION
The active matrix substrate of the present invention includes a substrate, and a thin film transistor and a capacitor provided on a main surface of the substrate. The active matrix substrate is used for manufacturing a display device, and has a plurality of pixels serving as a display unit. The thin film transistor and the capacitor are typically provided for each pixel.
[0029]
The thin film transistor has a semiconductor layer including a channel region. For example, when the active matrix substrate of the present invention is used as an active matrix substrate for a liquid crystal display device, the thin film transistor functions as a switching element, and a display signal is transmitted to the pixel electrode via the thin film transistor in an on state.
[0030]
The capacitive element has a capacitive dielectric film, and a lower capacitive electrode and an upper capacitive electrode arranged to face each other with the capacitive dielectric film interposed therebetween. For example, when the active matrix substrate of the present invention is used as an active matrix substrate for a liquid crystal display device, the capacitor is provided so that a storage capacitor is added in parallel with the liquid crystal capacitor, and unnecessary signals leak to the liquid crystal layer. , The pixel potential is maintained, and a decrease in display quality is prevented. The capacitive element is formed of a region where the upper capacitive electrode, the lower capacitive electrode, and the capacitive dielectric film overlap with the substrate normal.
[0031]
The capacitor is disposed closer to the substrate than the thin film transistor such that a channel region of the thin film transistor overlaps at least a part of the capacitor with respect to a direction substantially parallel to a substrate normal line (when viewed from the substrate direction). You.
[0032]
In general, when light enters a channel region of a thin film transistor, there is a problem that a leak current when the thin film transistor is turned off is increased. Therefore, it is necessary to shield the channel region from light. In the present invention, the capacitor is provided so that the channel region of the thin film transistor overlaps the capacitor. Therefore, even when a light-shielding layer is provided to shield the channel region, the light-shielding layer is disposed so as to overlap with the capacitor, and thus, in the substrate surface, a region where the transmittance is reduced by the capacitor. And the region of the light shielding layer overlap. As a result, an increase in the area where the transmittance is reduced by the capacitive element in the substrate surface can be suppressed, and a decrease in the pixel aperture ratio can be suppressed.
[0033]
It is preferable that at least one of the upper capacitor electrode and the lower capacitor electrode of the capacitor has a light-blocking property, because there is an advantage that it is not necessary to separately provide a light-blocking layer for blocking the channel region.
[0034]
In the active matrix substrate of the present invention, a concave portion is provided on the main surface of the substrate. The recess is defined by a bottom surface and a side surface continuous with the bottom surface. The main surface of the substrate has a bottom surface and side surfaces that define the concave portion, and an upper surface that is continuous with the side surfaces. The capacitive element extends from at least a part of the bottom surface of the concave portion of the substrate to at least a part of the side surface.
[0035]
If the capacitance of the capacitor can be increased, the effect of improving the display quality can be obtained. However, if the capacitance area is increased to increase the capacitance of the capacitor, there is a problem that the pixel aperture ratio decreases. In particular, when the capacitor element includes a light-blocking component, the pixel aperture ratio is significantly reduced.
[0036]
In the present invention, since the concave portion is provided on the main surface of the substrate, and the capacitive element extends from at least a part of the bottom surface of the concave portion to at least a part of the side surface, the capacitive element is provided on the flat substrate surface. Compared with the case, the capacitance area can be increased efficiently while suppressing a decrease in the pixel aperture ratio.
[0037]
INDUSTRIAL APPLICABILITY The active matrix substrate of the present invention can realize higher light shielding than ever before, and is therefore suitably used particularly as a substrate for a liquid crystal element used in a projection type liquid crystal display device. In a liquid crystal element used in a projection-type liquid crystal display device, it is necessary to make the light more intense than in a normal liquid crystal display device. However, since the active matrix substrate of the present invention can realize high light shielding, the above problem can be solved.
[0038]
Hereinafter, embodiments will be described with reference to the drawings. In the following embodiments, an active matrix substrate used for a liquid crystal display device will be described as an example. However, the active matrix substrate of the present invention is not limited to a liquid crystal display device but is used for various display devices such as an organic EL. The following embodiments are exemplifications of the present invention, and the present invention is not limited to the following embodiments.
[0039]
(Embodiment 1)
FIG. 1 is a schematic cross-sectional view of the active matrix substrate 20 according to the first embodiment, and FIGS. 2A and 2B are schematic plan views of the active matrix substrate 20. FIGS. 1 and 2 show a region where a TFT and a capacitor are formed in one pixel. FIG. 1 is a cross-sectional view corresponding to AA ′ in FIGS. 2A and 2B.
[0040]
The active matrix substrate 20 includes an insulating substrate 1 formed of, for example, quartz, and a concave portion 2 is provided on a main surface of the insulating substrate 1. The recess 2 is defined by a bottom surface 2a and a side surface 2b continuous with the bottom surface 2a. That is, the main surface of the substrate 1 has the bottom surface 2a and the side surface 2b, and the upper surface 1a.
[0041]
In a predetermined region of the substrate 1, a lower capacitor electrode 3, a capacitor dielectric film 4, and an upper capacitor electrode 5 are arranged in this order from the substrate 1 side, and the capacitor element 19 is formed by these. . As described above, the overlapping region of the upper capacitor electrode 5, the lower capacitor electrode 3, and the capacitor dielectric film 4 with respect to the substrate normal forms the capacitor element 19. The capacitance element 19 is arranged to extend from at least a part of the bottom surface 2a of the recess 2 to at least a part of the side surface 2b. In this embodiment, as shown in FIG. 1, the lower capacitor electrode 3, the capacitor dielectric film 4, and the upper capacitor electrode 5 all cover the entire bottom surface 2 a and the side surface 2 b of the recess 2, and Since the capacitor element 19 is formed so as to extend to a part, the capacitive element 19 is formed over the entire bottom surface 2 a and side surface 2 b of the recess 2 and a part of the upper surface 1 a of the substrate 1.
[0042]
By forming the concave portion 2 on the main surface of the insulating substrate 1 and forming the capacitive element 19 on the bottom surface 2 a and the side surface 2 b of the concave portion 2, the capacitive element 19 Can be increased by the area of the capacitive element 19 formed on the side surface 2b of the concave portion 2 without increasing the area occupied by. That is, as compared with the case where a capacitor is formed in the same substrate surface as shown in FIG. 12, the capacitance of the capacitor can be efficiently increased while suppressing a decrease in the pixel aperture ratio.
[0043]
In the present embodiment, for example, the lower capacitor electrode 3 is formed of a polycrystalline silicon film doped with an impurity such as phosphorus at a high concentration, and the capacitor dielectric film 4 is formed of SiO 2. ₂ The upper capacitor electrode 5 is formed of a laminated film of a polycrystalline silicon film doped with impurities such as phosphorus at a high concentration and a WSi film.
[0044]
On the upper capacitor electrode 5, for example, SiO ₂ The TFT semiconductor layer 7 is disposed with the first insulating film 6 formed of a film interposed therebetween. The TFT semiconductor layer 7 includes a channel region 7c, a source region 7a, and a drain region 7b. At least the channel region 7c of the TFT semiconductor layer 7 is disposed so as to overlap with the capacitive element 19 in a direction substantially parallel to the substrate normal 1c.
[0045]
In the present embodiment, since the upper capacitor electrode 5 has a light-shielding property, the capacitor element 19 has a light-shielding function. Therefore, by overlapping the channel region 7c with the capacitor 19, the channel region 7c is shielded from light by the capacitor 19. Note that in the present invention, the capacitor does not necessarily have to have a component formed of a light-blocking material, but when the capacitor 19 has a light-blocking function, it is not necessary to provide a separate light-blocking layer. It is more preferable because of its advantages.
[0046]
It is preferable that the channel region 7c be arranged inside the recess 2 and at a position lower than the upper end of the capacitive element 2. Here, that the channel region 7c is arranged inside the concave portion 2 means that the channel region 7c faces the bottom surface 2a of the concave portion 2 and is equal to or less than the height of the upper surface 1a of the substrate 1 from the bottom surface 2a of the concave portion 2. It is shown that it is arranged at the position of. Further, the upper end of the capacitive element 2 refers to the end of the capacitive element 2 which is located at the highest position from the bottom surface 2a of the concave portion 2 toward the upper surface 1a. When the capacitive element 2 has a light shielding property as in the present embodiment, the channel region 7c is disposed inside the concave portion 2 and at a position lower than the upper end portion of the capacitive element 2 so that the bottom surface of the concave portion 2 is formed. The effect that the channel region 7c can be shielded from light by the capacitive element 2 formed on the side surface 2a and the side surface 2b is obtained.
[0047]
On the TFT semiconductor layer 7, a gate oxide film 8, a gate electrode 9, and a second insulating film 10 are formed in this order from the substrate 1 side. A source electrode 14 and a drain electrode 15 are provided on the second insulating film 10, and a third insulating film 16 is provided so as to cover the source electrode 14 and the drain electrode 15. Further, a transparent pixel electrode 18 is formed in a predetermined region on the third insulating film 16.
[0048]
Source contact hole 11 and drain contact hole 12 are formed in second insulating film 10 and gate oxide film 8. Further, a capacitor contact hole 13 is formed in the second insulating film 10, the gate oxide film 8, the first insulating film 6, and the capacitor dielectric film 4. The source electrode 14 is connected to the source region 7a of the TFT via the source contact hole 11. The drain electrode 15 is connected to the drain region 7b of the TFT via the drain contact hole 12 and to the lower capacitor electrode 3 via the capacitor contact hole 13, so that the capacitance element 19 and the drain region 7b are electrically connected. And the capacitive element 19 and the transparent pixel electrode 18 are electrically connected.
[0049]
Next, with reference to FIGS. 3A to 3D and FIGS. 4A and 4B, a method of manufacturing the active matrix substrate 20 will be described.
[0050]
First, an insulating substrate 1 made of quartz is prepared, and a concave portion 2 is formed on a main surface of the substrate 1 by using a photo-etching technique as shown in FIG. The depth of the concave portion 2 (distance h1 from the bottom surface 2a to the upper surface 1a) was, for example, 1 μm. The depth of the concave portion 2 is set to be larger than the sum of the thicknesses of the capacitor element 19, the TFT semiconductor layer 7, and the first insulating film 6 formed in the concave portion 2 in a later step. .
[0051]
Next, as shown in FIG. 3B, after forming a polycrystalline silicon film having a thickness of 100 nm doped with impurities such as phosphorus at a high concentration, the lower capacitor electrode 3 is formed by using a photo-etching technique. I do. The lower capacitor electrode 3 is formed so as to cover the entire bottom surface 2 a and side surface 2 b of the concave portion 2 and further extend to a part of the upper surface 1 a of the substrate 1.
[0052]
Next, as shown in FIG. 3B, a 40 nm-thick SiO ₂ After the capacitor dielectric film 4 is formed, ₂ An oxidation annealing treatment is performed under the conditions of an atmosphere and 900 ° C. By the oxidation annealing treatment, the capacitor dielectric film 4 can be formed into a film having excellent withstand voltage. Subsequently, a laminated film in which a polycrystalline silicon film (thickness: 100 nm) doped with impurities such as phosphorus at a high concentration and a WSi film (thickness: 100 nm) are sequentially laminated on the dielectric film for capacitance 4 is formed. I do. After the film formation, the laminated film is patterned by using a photoetching technique to form the upper capacitor electrode 5.
[0053]
In the present embodiment, a part of the capacitance wiring 5a (FIGS. 2A and 2B) functions as the upper capacitance electrode 5. As shown in FIGS. 2A and 2B, the capacitance wiring 5a is formed in a grid pattern over the entire display area. In the grid-like capacitance wiring 5a, the capacitance wiring 5a extending in one direction is arranged so as to overlap the gate wiring 9a, and the capacitance wiring 5a extending in the other direction is arranged so as to overlap the source wiring. The capacitance wiring 5a is formed so that a voltage can be directly applied from the outside. Note that the shape of the capacitor wiring 5a is not limited to the above, and may be formed linearly over the entire display area.
[0054]
As described above, the capacitive element 19 including the upper capacitive electrode 5, the lower capacitive electrode 3, and the capacitive dielectric film 4 is formed. As shown in FIG. 3B, the capacitive element 19 is formed so as to extend to the entire bottom surface 2a and the side surface 2b of the concave portion 2 and further to a part of the upper surface 1a of the substrate 1.
[0055]
The upper capacitor electrode 5, the lower capacitor electrode 3, and the capacitor dielectric film 4 can also be formed using materials other than those exemplified above. At least one of the upper capacitor electrode 3 and the lower capacitor electrode 5 is made of, for example, tungsten, molybdenum, tantalum, chromium, titanium, tungsten silicide, molybdenum silicide, tantalum silicide, chromium silicide, titanium silicide, tungsten alloy, molybdenum A single layer or a stack of two or more layers including at least one selected from the group consisting of an alloy, a tantalum alloy, a chromium alloy, a titanium alloy, amorphous silicon doped with impurities, and polycrystalline silicon doped with impurities. Consists of a membrane. The capacitor dielectric film 4 is formed of, for example, one of a silicon oxide film, a silicon nitride film, and a stacked film of a silicon oxide film and a silicon nitride film.
[0056]
Next, as shown in FIG. 3C, a 400 nm-thick SiO 2 film is formed on the upper capacitor electrode 5. ₂ A first insulating film 6 made of a film is formed, and after the film formation, an amorphous silicon film having a thickness of 70 nm is formed on the first insulating film 6 by using the LPCVD method. Subsequently, the amorphous silicon film is crystallized by performing a heat treatment at 600 ° C. for 20 hours, and then etched into a predetermined shape to form a TFT semiconductor layer 7. A region of the TFT semiconductor layer 7 which will later become the channel region 7c is formed so as to overlap with the capacitive element 19 in a direction substantially parallel to the substrate normal 1c.
[0057]
As described above, in the present embodiment, the depth h1 of the recess 2 is 1 μm. The thickness of the capacitor 19 is 340 nm (total thickness of the lower capacitor electrode 3 having a thickness of 100 nm, the capacitor dielectric film 4 having a thickness of 40 nm, and the upper capacitor electrode 5 having a thickness of 200 nm). The thickness of the film 6 is set to 400 nm, and the thickness of the TFT semiconductor layer 7 is set to 70 nm. The total thickness of these 810 nm is smaller than the depth h1 (1 μm) of the concave portion 2 and The region that becomes the channel region 7c is disposed inside the concave portion 2. In this embodiment, since the capacitance element 19 is formed so as to cover the entire bottom surface 2a of the concave portion 2 and the entire surface of the side surface 2b, the capacitance element 19 of the bottom surface 2a and the side surface 2b of the concave portion 2 Light incident on the channel region 7c from below or from the side can be blocked with high efficiency.
[0058]
Next, as shown in FIG. 3D, an 80 nm-thick SiO 2 film is formed on the TFT semiconductor layer 7. ₂ A gate oxide film 8 made of a film is formed, and a polycrystalline silicon film (thickness 150 nm) doped with impurities such as phosphorus at a high concentration and a WSi film (thickness 150 nm) are sequentially formed on the gate oxide film 8. A laminated film is formed. After the film formation, the stacked film is patterned using a photoetching technique to form a gate electrode 9. Further, using the gate electrode 9 as a mask, an impurity such as phosphorus is ^Fifteen Atom / cm ² , 75 Kev. Thus, source region 7a and drain region 7b, which are high-concentration impurity regions, and channel region 7c located below gate electrode 9 are formed.
[0059]
FIG. 2B is a plan view corresponding to FIG. 3D.
[0060]
Next, as shown in FIG. 4A, a second insulating film 10 is formed so as to cover the gate electrode 9. After forming the second insulating film 10, a source contact hole 11 and a drain contact hole 12 are formed in the second insulating film 10 and the gate oxide film 8 such that predetermined portions of the source region 7a and the drain region 7b are exposed. . Further, a capacitor contact hole 13 is formed in the second insulating film 10, the gate oxide film 8, the first insulating film 6, and the capacitor dielectric film 4 so that a predetermined portion of the lower capacitor electrode 3 is exposed.
[0061]
After forming the contact holes 11 to 13, a laminated film is formed by sequentially laminating an 80-nm-thick TiW film, a 400-nm-thick Al-Si film, and a 150-nm-thick TiW film. The stacked film is patterned using a photoetching technique to form a source electrode 14 and a drain electrode 15. The source electrode 14 is connected to the source region 7a of the TFT via the source contact hole 11. The drain electrode 15 is connected to the drain region 7 b of the TFT via the drain contact hole 12 and to the lower capacitor electrode 3 via the capacitor contact hole 13. By providing a conductive material to each contact hole, the capacitor 19 and the drain region 7b can be electrically connected, and the capacitor 19 and a transparent pixel electrode 18 described later can be electrically connected.
[0062]
Next, as shown in FIG. 4B, a third insulating film 16 is formed so as to cover the source electrode 14 and the drain electrode 15. After the film formation, a pixel contact hole 17 is formed in the third insulating film 16 so that a predetermined portion of the drain electrode 15 is exposed. Further, an indium tin oxide film (ITO) having a thickness of 120 nm is formed on the third insulating film 16. After the film formation, the above-mentioned ITO is patterned using a photo-etching technique to form a transparent pixel electrode 18 connected to the drain electrode 15.
[0063]
Through the above steps, the active matrix substrate 20 of Embodiment 1 is manufactured. The obtained active matrix substrate 20 is bonded to a counter substrate with a liquid crystal material interposed therebetween using a known method, for example, to form a liquid crystal display element.
[0064]
Hereinafter, Embodiments 2 to 8 will be described. Among the components of the active matrix substrate of the second to eighth embodiments, components having the same functions as those of the active matrix substrate 20 of the first embodiment are denoted by the same reference numerals, and description thereof will be omitted.
[0065]
(Embodiment 2)
Next, an active matrix substrate 30 according to the second embodiment will be described. FIG. 5 is a partial cross-sectional view of the active matrix substrate 30.
[0066]
The active matrix substrate 30 is characterized in that low-concentration impurity regions 7d are formed both between the channel region 7c and the source region 7a of the TFT semiconductor layer 7 and between the channel region 7c and the drain region 7b. This is different from the active matrix substrate 20 of the first embodiment. Since the active matrix substrate 30 is provided with the low-concentration impurity region 7d, a resistance component is added to the TFT, so that an increase in leak current in the off state of the liquid crystal display device can be further suppressed.
[0067]
Hereinafter, a method for manufacturing the active matrix substrate 30 will be described.
[0068]
The gate electrode 9 is manufactured up to the gate electrode 9 by using the same process as the manufacturing method described for the active matrix substrate 20 of the first embodiment.
[0069]
After the formation of the gate electrode 9, an impurity such as phosphorus is implanted in a concentration of 2 × 10 ^Thirteen Atom / cm ² , 75 Kev. After the implantation, a photoresist is formed on the TFT semiconductor layer 7, and impurities such as phosphorus ^Fifteen Atom / cm ² , 75 Kev. By this step, a source region 7a, a drain region 7b, which is a high-concentration impurity region, and a channel region 7c located below the gate electrode 9 are formed. Thus, the low-concentration impurity regions 7d are simultaneously formed both between the channel region 7c and the source region 7a and between the channel region 7c and the drain region 7b.
[0070]
Thereafter, by using the same process as the manufacturing method described for the active matrix substrate 20 of the first embodiment, up to the transparent pixel electrodes 18 are formed, and the active matrix substrate 30 is manufactured.
[0071]
(Embodiment 3)
Next, an active matrix substrate 40 according to the third embodiment will be described. FIG. 6 is a partial sectional view of the active matrix substrate 40.
[0072]
The active matrix substrate 40 is different from the first embodiment in that the quartz substrate 41 does not have the concave portion 2 and the concave portion 2 is provided in an insulating film (fourth insulating film 41 a) provided on the quartz substrate 41. Is different from the active matrix substrate 20 of FIG. In the active matrix substrate 40, since the fourth insulating film 41a is formed on the quartz substrate 501, impurity contamination from the quartz substrate 41 can be prevented.
[0073]
Hereinafter, a method for manufacturing the active matrix substrate 40 will be described.
[0074]
First, a fourth insulating film 41a having a thickness of 1.3 μm is formed on an insulating substrate 41 formed of quartz. Next, the concave portion 2 having a depth of 1 μm is formed in the fourth insulating film 41a by using a photoetching technique. Unlike the active matrix substrate 20 of the first embodiment, in the present embodiment, the recess 2 is not formed in the insulating substrate 41, but is formed in the fourth insulating film 41a formed on the insulating substrate 41.
[0075]
Thereafter, by using the same process as the manufacturing method described for the active matrix substrate 20 according to the first embodiment, up to the transparent pixel electrodes 18 are formed, and the active matrix substrate 40 according to the third embodiment is manufactured.
[0076]
(Embodiment 4)
Next, an active matrix substrate 50 according to the fourth embodiment will be described. FIG. 7 is a partial cross-sectional view of the active matrix substrate 50.
[0077]
The active matrix substrate 50 is such that the quartz substrate 41 does not have the recess 2 and the recess 2 is provided in a further insulating film (fourth insulating film 41a) provided on the quartz substrate 41; The active matrix of the first embodiment is that the low-concentration impurity regions 7d are formed both between the channel region 7c and the source region 7a of the TFT semiconductor layer 7 and between the channel region 7c and the drain region 7b. Different from the substrate 20. The active matrix substrate 50 is a combination of the first, second, and third embodiments, and can simultaneously obtain the effects described in the first, second, and third embodiments.
[0078]
Hereinafter, a method for manufacturing the active matrix substrate 50 will be described.
[0079]
First, a fourth insulating film 41a having a thickness of 1.3 μm is formed on an insulating substrate 41 formed of quartz. Next, the concave portion 2 having a depth of 1 μm is formed in the fourth insulating film 41a by using a photoetching technique. Unlike the active matrix substrate 20 of the first embodiment, in the present embodiment, the recess 2 is not formed in the insulating substrate 41, but is formed in the fourth insulating film 41a formed on the insulating substrate 41.
[0080]
Thereafter, the processes from the lower capacitor electrode 3 to the gate electrode 9 are manufactured using the same process as the manufacturing method described for the active matrix substrate 20 of the first embodiment.
[0081]
After the formation of the gate electrode 9, the gate electrode 9 is used as a mask and impurities such as phosphorus ^Thirteen Atom / cm ² , 75 Kev. After the implantation, a photoresist is formed on the TFT semiconductor layer 7, and impurities such as phosphorus ^Fifteen Atom / cm ² , 75 Kev. By this step, a source region 7a, a drain region 7b, which is a high-concentration impurity region, and a channel region 7c located below the gate electrode 9 are formed. Thus, the low-concentration impurity regions 7d are simultaneously formed both between the channel region 7c and the source region 7a and between the channel region 7c and the drain region 7b.
[0082]
Thereafter, the transparent pixel electrodes 18 are formed using the same process as the manufacturing method described for the active matrix substrate 20 of the first embodiment, and the active matrix substrate 50 of the fourth embodiment is manufactured.
[0083]
(Embodiment 5)
Next, an active matrix substrate 60 according to the fifth embodiment will be described. FIG. 8 is a partial sectional view of the active matrix substrate 60.
[0084]
The active matrix substrate 60 is different from the first embodiment in that the drain electrode 67 and the upper capacitance electrode 65 are connected by the capacitance contact hole 66 and that a part of the capacitance wiring acts as the lower capacitance electrode 63. Is different from the active matrix substrate 20 of FIG. The capacitance wiring is formed in a grid pattern over the entire display area, for example, similarly to the capacitance wiring 5a of the first embodiment. Further, it is formed so that a voltage can be directly applied from the outside. Note that the capacitance wiring may be formed in a linear shape.
[0085]
In the active matrix substrate 60, since the drain electrode 67 and the upper capacitance electrode 65 are connected, it is not necessary to remove a part of the upper capacitance electrode 65 to secure a region for forming the capacitance contact hole 66. Therefore, since the area of the upper capacitance electrode 65 can be made larger, the capacitance area of the capacitance element 19 can be made larger and the capacitance can be increased.
[0086]
Hereinafter, a method for manufacturing the active matrix substrate 60 will be described.
[0087]
By using the same process as the manufacturing method described for the active matrix substrate 20 of the first embodiment, up to the second insulating film 10 is formed. After forming the second insulating film 10, a source contact hole 11 and a drain contact hole 12 are formed as in the first embodiment.
[0088]
In the present embodiment, since the drain electrode 67 and the upper capacitance electrode 65 are connected by the capacitance contact hole 66, the second insulating film 10, the gate oxide film 8, and the second (1) A capacitance contact hole 66 is formed in the insulating film 6. Next, the drain electrode 67 and the source electrode 14 are formed, and the drain electrode 67 and the upper capacitance electrode 65 are connected by the capacitance contact hole 66.
[0089]
Thereafter, the transparent pixel electrodes 18 are formed using the same process as the manufacturing method described for the active matrix substrate 20 of the first embodiment, and the active matrix substrate 60 of the fifth embodiment is manufactured.
[0090]
(Embodiment 6)
Next, an active matrix substrate 70 according to the sixth embodiment will be described. FIG. 9 is a partial sectional view of the active matrix substrate 70.
[0091]
The active matrix substrate 70 is characterized in that a low-concentration impurity region 7d is formed both between the channel region 7c and the source region 7a of the TFT semiconductor layer 7 and between the channel region 7c and the drain region 7b. The active matrix substrate 20 of the first embodiment is different from the active matrix substrate 20 of the first embodiment in that the upper capacitance electrode 67 is connected to the upper capacitance electrode 65 by a capacitance contact hole 66 and that a part of the capacitance wiring acts as the lower capacitance electrode 63. The capacitance wiring is formed in a grid pattern over the entire display area, for example, similarly to the capacitance wiring 5a of the first embodiment. Further, it is formed so that a voltage can be directly applied from the outside. Note that the capacitance wiring may be formed in a linear shape.
[0092]
The active matrix substrate 70 is a combination of the first, second, and fifth embodiments, and can simultaneously obtain the effects described in the first, second, and fifth embodiments.
[0093]
Hereinafter, a method for manufacturing the active matrix substrate 70 will be described.
[0094]
The gate electrode 9 is manufactured up to the gate electrode 9 by using the same process as the manufacturing method described for the active matrix substrate 20 of the first embodiment.
[0095]
After the formation of the gate electrode 9, an impurity such as phosphorus is implanted in a concentration of 2 × 10 ^Thirteen Atom / cm ² , 75 Kev. After the implantation, a photoresist is formed on the TFT semiconductor layer 7, and impurities such as phosphorus ^Fifteen Atom / cm ² , 75 Kev. In this step, a source region 7a, a drain region 7b, which is a high-concentration impurity region, and a channel region 7c located below the gate electrode 9 are formed. As a result, the low-concentration impurity regions 7d are simultaneously formed both between the channel region 7c and the source region 7a and between the channel region 7c and the drain region 7b.
[0096]
Subsequently, the processes up to the second insulating film 10 are formed using the same process as the manufacturing method described for the active matrix substrate 20 of the first embodiment. After forming the second insulating film 10, a source contact hole 11 and a drain contact hole 12 are formed as in the first embodiment.
[0097]
In the present embodiment, since the drain electrode 67 and the upper capacitance electrode 65 are connected by the capacitance contact hole 66, the second insulating film 10, the gate oxide film 8 and the second oxide film 8 are formed so that a predetermined region of the upper capacitance electrode 65 is exposed. (1) A capacitance contact hole 66 is formed in the insulating film 6. Next, the drain electrode 67 and the source electrode 14 are formed, and the drain electrode 67 and the upper capacitance electrode 65 are connected by the capacitance contact hole 66.
[0098]
Thereafter, the transparent pixel electrode 18 is formed using the same process as the manufacturing method described for the active matrix substrate 20 of the first embodiment, and the active matrix substrate 70 is manufactured.
[0099]
(Embodiment 7)
Next, an active matrix substrate 80 according to the seventh embodiment will be described. FIG. 10 is a partial cross-sectional view of the active matrix substrate 80.
[0100]
The active matrix substrate 80 is such that the quartz substrate 41 does not have the recess 2 and the recess 2 is provided in a further insulating film (fourth insulating film 41 a) provided on the quartz substrate 41; The active matrix substrate 20 of the first embodiment differs from the active matrix substrate 20 of the first embodiment in that the drain electrode 67 and the upper capacitance electrode 65 are connected by the capacitance contact hole 66 and that a part of the capacitance wiring acts as the lower capacitance electrode 63. different. The capacitance wiring is formed in a grid pattern over the entire display area, for example, similarly to the capacitance wiring 5a of the first embodiment. Further, it is formed so that a voltage can be directly applied from the outside. Note that the capacitor wiring may be formed in a linear shape.
[0101]
The active matrix substrate 80 is a combination of the first, third, and fifth embodiments, and can simultaneously obtain the effects described in the first, third, and fifth embodiments.
[0102]
The active matrix substrate 80 is manufactured by combining the manufacturing methods described in the first, third, and fifth embodiments.
[0103]
(Embodiment 8)
Next, an active matrix substrate 90 according to the eighth embodiment will be described. FIG. 11 is a partial cross-sectional view of the active matrix substrate 90.
[0104]
The active matrix substrate 90 is characterized in that low-concentration impurity regions 7d are formed both between the channel region 7c and the source region 7a of the TFT semiconductor layer 7 and between the channel region 7c and the drain region 7b. The point that the substrate 41 does not have the concave portion 2 and the concave portion 2 is provided in a further insulating film (fourth insulating film 41a) provided on the quartz substrate 41, and that the drain electrode 67 and the upper capacitance electrode The active matrix substrate 20 of the first embodiment is different from the active matrix substrate 20 of the first embodiment in that the capacitor 65 is connected to a capacitor contact hole 66 and that a part of the capacitor wiring acts as the lower capacitor electrode 63. The capacitance wiring is formed in a grid pattern over the entire display area, for example, similarly to the capacitance wiring 5a of the first embodiment. Further, it is formed so that a voltage can be directly applied from the outside. Note that the capacitance wiring may be formed in a linear shape.
[0105]
The active matrix substrate 80 is a combination of the first, second, third and fifth embodiments, and can simultaneously obtain the effects described in the first, second, third and fifth embodiments.
[0106]
The active matrix substrate 80 is manufactured by combining the manufacturing methods described in the first, second, third and fifth embodiments.
[0107]
【The invention's effect】
According to the present invention, there is provided an active matrix substrate capable of improving a pixel aperture ratio without deteriorating display quality. By using the active matrix substrate of the present invention, a display device with high display quality can be configured.
[Brief description of the drawings]
FIG. 1 is a schematic cross-sectional view of an active matrix substrate according to a first embodiment of the present invention, and corresponds to AA ′ in FIGS. 2 (a) and (b).
FIGS. 2A and 2B are schematic plan views of the active matrix substrate according to the first embodiment.
FIGS. 3A to 3D are views for explaining a method of manufacturing the active matrix substrate according to the first embodiment.
FIGS. 4A and 4B are diagrams illustrating a method for manufacturing the active matrix substrate according to the first embodiment.
FIG. 5 is a sectional view of an active matrix substrate according to a second embodiment.
FIG. 6 is a cross-sectional view of an active matrix substrate according to a third embodiment.
FIG. 7 is a sectional view of an active matrix substrate according to a fourth embodiment.
FIG. 8 is a sectional view of an active matrix substrate according to a fifth embodiment.
FIG. 9 is a sectional view of an active matrix substrate according to a sixth embodiment.
FIG. 10 is a sectional view of an active matrix substrate according to a seventh embodiment.
FIG. 11 is a sectional view of an active matrix substrate according to an eighth embodiment.
FIG. 12 is a cross-sectional view of a conventional active matrix substrate, and corresponds to BB ′ in FIG.
FIG. 13 is a partial plan view of a conventional active matrix substrate.
[Explanation of symbols]
1 substrate
1a Top surface
2 recess
2a bottom
2b side view
3 Lower capacitance electrode
4 Capacitive dielectric film
5 Upper capacitance electrode
5a Capacity wiring
6 First insulating film
7 TFT semiconductor layer
7a Source area
7b Drain region
7c channel region
8 Gate oxide film
9 Gate electrode
10 Second insulating film
11 Source contact hole
12 Drain contact hole
13 Capacitance contact hole
14 Source electrode
15 Drain electrode
16 Third insulating film
17 Pixel contact hole
18 Transparent pixel electrode
19 Capacitance element
20 Active matrix substrate
30 Active matrix substrate
40 Active matrix substrate
41 quartz substrate
41a fourth insulating film
50 Active matrix substrate
60 Active matrix substrate
63 Lower capacitance electrode
65 Upper capacitance electrode
66 capacity contact hole
67 Drain electrode
70 Active matrix substrate
80 Active matrix substrate
90 Active matrix substrate
1101 Quartz substrate
1103 Lower capacitance electrode
1103a Lower light shielding film
1105 Upper capacitance electrode
1106 First insulating film
1107 TFT semiconductor layer
1107a Source area
1107b Drain region
1107c Channel region
1108 Gate oxide film
1109 Gate electrode
1110 Second insulating film
1111 Source contact hole
1112 Drain contact hole
1114 Source electrode
1115 Drain electrode
1116 Third insulating film
1117 Pixel contact hole
1118 Transparent pixel electrode
1200 active matrix substrate

Claims (14)

A substrate, an active matrix substrate including a thin film transistor and a capacitor provided on a main surface of the substrate,
The thin film transistor has a semiconductor layer including a channel region,
The capacitive element has a capacitive dielectric film, and a lower capacitive electrode and an upper capacitive electrode that are arranged to face each other with the capacitive dielectric film interposed therebetween,
The substrate has a concave portion on the main surface, the main surface has an upper surface, a bottom surface defining the concave portion, and a side surface continuous with the bottom surface and the upper surface,
The capacitance element is disposed closer to the substrate than the thin film transistor so as to overlap the channel region of the thin film transistor when viewed from the substrate direction,
The active matrix substrate, wherein the capacitance element extends from at least a part of the bottom surface of the recess to at least a part of the side surface. The active matrix substrate according to claim 1, wherein the substrate is formed of quartz. The active matrix substrate according to claim 1, wherein the substrate includes a plate not having the concave portion, and an insulating film provided on the plate, and the concave portion is provided in the insulating film. 2. The channel layer of the thin film transistor is disposed inside the concave portion, and is disposed closer to the bottom surface than an upper end of the capacitive element provided on at least a part of the side surface of the concave portion. 4. The active matrix substrate according to any one of 1. to 3., The active matrix substrate according to claim 1, wherein the capacitance element extends from at least a part of the bottom surface of the recess to at least a part of the top surface via the side surface. The channel region of the thin film transistor is disposed on the capacitor via an insulating layer,
The height from the bottom surface of the concave portion to the upper surface of the substrate is larger than the sum of the thicknesses of the capacitor, the semiconductor layer, and the insulating layer. Active matrix substrate. The active matrix substrate according to claim 1, wherein the capacitive element is formed on the entire bottom surface and the side surface of the concave portion. The active matrix substrate according to claim 1, wherein at least one of the upper capacitance electrode and the lower capacitance electrode has a light shielding property. At least one of the upper capacitor electrode and the lower capacitor electrode is tungsten, molybdenum, tantalum, chromium, titanium, tungsten silicide, molybdenum silicide, tantalum silicide, chromium silicide, titanium silicide, tungsten alloy, molybdenum alloy, A single layer containing at least one selected from the group consisting of a tantalum alloy, a chromium alloy, a titanium alloy, an impurity-doped amorphous silicon, and an impurity-doped polycrystalline silicon; The active matrix substrate according to claim 1, wherein the active matrix substrate is configured. 10. The active device according to claim 1, wherein the capacitor dielectric film is formed of any one of a silicon oxide film, a silicon nitride film, and a stacked film of a silicon oxide film and a silicon nitride film. Matrix substrate. The semiconductor layer includes a source region and a drain region that are arranged to face each other with the channel region interposed therebetween, and further, between the channel region and the source region, and between the channel region and the drain region. 11. The active matrix substrate according to claim 1, further comprising a low-concentration impurity region. A display device comprising: the active matrix substrate according to claim 1; and a display medium layer disposed on the active matrix substrate. The display device according to claim 12, wherein the display medium layer includes a liquid crystal material. 14. The display device according to claim 13, which is a projection type liquid crystal display device.

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