CN110993657A - Display panel, device and preparation method of display panel - Google Patents
Display panel, device and preparation method of display panel Download PDFInfo
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1248—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition or shape of the interlayer dielectric specially adapted to the circuit arrangement
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10K—ORGANIC ELECTRIC SOLID-STATE DEVICES
- H10K59/00—Integrated devices, or assemblies of multiple devices, comprising at least one organic light-emitting element covered by group H10K50/00
- H10K59/10—OLED displays
- H10K59/12—Active-matrix OLED [AMOLED] displays
- H10K59/1201—Manufacture or treatment
Abstract
The embodiment of the invention relates to the technical field of display, and discloses a display panel, a device and a preparation method of the display panel, wherein the display panel comprises a substrate, a functional layer, a first dielectric layer, a barrier film and an interlayer dielectric film which are sequentially stacked, the etching rate of the barrier film under a first etching condition is smaller than that of the interlayer dielectric film, the etching rate of the functional layer under the first etching condition is smaller than that of the first dielectric layer, and the etching rate of the barrier film under a second etching condition is larger than that of the first dielectric layer; the first through hole extends from the interlayer dielectric film to the functional layer and penetrates through the interlayer dielectric film and the barrier film; the second through hole extends from the interlayer dielectric film to the barrier film and penetrates through the interlayer dielectric film; and the first metal film is arranged in the second through hole. The display panel, the device and the preparation method of the display panel can ensure that the display panel has uniform capacitance.
Description
Technical Field
The embodiment of the invention relates to the technical field of display, in particular to a display panel, a device and a preparation method of the display panel.
Background
AMOLED (Active Matrix Organic Light Emitting Diode Display, Active Matrix driving Organic Light Emitting Diode Display) has the advantages of low manufacturing cost, high response speed, power saving, direct current driving for portable devices, large working temperature range, and the like, and thus is expected to become a next-generation novel flat panel Display replacing LCD (Liquid Crystal Display). Particularly, the flexible AMOLED is increasingly gaining attention in the market due to its advantages of being light and thin, being bendable or foldable, being capable of changing shape at will, and the like. A capacitor is usually required in the AMOLED to maintain the picture on. With the increase of PPI requirement of display panel and the reduction of refresh frequency requirement, the display panel is required to have uniform capacitance.
The quality of the display panel manufactured by the prior art needs to be improved.
Disclosure of Invention
An object of embodiments of the present invention is to provide a display panel, a device and a method for manufacturing the display panel, which can ensure that the display panel has a uniform capacitance value.
To solve the above technical problem, an embodiment of the present invention provides a display panel including:
the substrate, the functional layer, the first dielectric layer, the barrier film and the interlayer dielectric film are stacked, the etching rate of the barrier film under a first etching condition is smaller than that of the interlayer dielectric film, the etching rate of the functional layer under the first etching condition is smaller than that of the first dielectric layer, and the etching rate of the barrier film under a second etching condition is larger than that of the first dielectric layer; the first through hole extends from the interlayer dielectric film to the functional layer and penetrates through the interlayer dielectric film and the barrier film; the second through hole extends from the interlayer dielectric film to the barrier film and penetrates through the interlayer dielectric film; a first metal film disposed within the second via.
In addition, the first dielectric layer comprises a gate insulating film and a capacitor dielectric film positioned on one side of the gate insulating film far away from the functional layer, the barrier film is arranged between the capacitor dielectric film and the interlayer dielectric film, and the etching rate of the barrier film under the second etching condition is greater than that of the capacitor dielectric film. By the method, the capacitance of the display panel can be improved, and the performance of the capacitor structure is improved.
In addition, the display panel further comprises a second metal film, the second metal film and the capacitor dielectric film are arranged on the same layer, part of the capacitor dielectric film is arranged between the first metal film and the second metal film, and the orthographic projection of the second metal film on the substrate is overlapped with the orthographic projection of the first metal film on the substrate.
In addition, the functional layer structure further comprises a second dielectric layer arranged between the substrate and the functional layer, the orthographic projection of the functional layer on the substrate is positioned in the orthographic projection of the second dielectric layer on the substrate, and the orthographic projection of the second through hole on the substrate is independent of the orthographic projection of the functional layer on the substrate. With such an arrangement, the structure of the functional layer is not damaged in the process of forming the second through hole, thereby improving the reliability of the functional layer.
Correspondingly, the embodiment of the invention also provides a display device which comprises the display panel
Correspondingly, the embodiment of the invention also provides a preparation method of the display panel, which comprises the following steps: providing a substrate; forming a functional layer, a first dielectric layer, a barrier film and an interlayer dielectric film which are stacked on the substrate, wherein the etching rate of the barrier film under a first etching condition is less than that of the interlayer dielectric film, the etching rate of the functional layer under the first etching condition is less than that of the first dielectric layer, and the etching rate of the barrier film under a second etching condition is greater than that of the first dielectric layer; carrying out initial etching treatment on the interlayer dielectric film and the first dielectric layer which are opposite to the functional layer until the interlayer dielectric film and the first dielectric layer penetrate through the barrier film so as to form a first pre-through hole; etching the bottom of the first pre-through hole to form a first through hole extending from the interlayer dielectric film to the functional layer; performing the etching treatment on the interlayer dielectric film and the capacitance region of the barrier film which is not etched to form a second through hole extending from the interlayer dielectric film to the barrier film; and forming a metal layer in the second through hole.
In addition, before the initial etching treatment is carried out on the interlayer dielectric film and the barrier film which are opposite to the functional layer, the method further comprises the following steps: forming a patterned mask layer on the interlayer dielectric film, wherein the mask layer is internally provided with a first groove and a second groove, the depth of the first groove is smaller than the thickness of the mask layer, and the second groove penetrates through the mask layer; the method for forming the pre-through hole comprises the following steps of performing initial etching treatment on the interlayer dielectric film and the barrier film opposite to the functional layer until the interlayer dielectric film and the barrier film penetrate through the barrier film to form a first pre-through hole, and specifically comprises the following steps: and carrying out initial etching treatment on the interlayer dielectric film and the barrier film along the second groove by taking the mask layer as a mask to form a first pre-through hole penetrating through the barrier film.
In addition, after the forming of the first pre-via penetrating the barrier film and before the etching process is performed on the bottom of the first pre-via, the method further includes: thinning the mask layer to enable the first groove to penetrate through the mask layer; the process steps for forming the first via and the second via include: and etching the interlayer dielectric film along the first groove by taking the mask layer as a mask to expose the barrier film to form the second through hole, and simultaneously etching the bottom of the first pre-through hole to expose the functional layer to form the first through hole.
In addition, thinning the mask layer to make the first groove penetrate through the mask layer specifically includes: and in the process of forming the first pre-through hole or after forming the first pre-through hole, performing thinning treatment on the mask layer by adopting an ashing process, wherein the mask layer is made of photoresist.
In addition, the initial etching treatment specifically includes: etching the interlayer dielectric film along the second groove by using the mask layer as a mask through a first etching process until the barrier film is exposed; and etching the barrier film by using a second etching process until the barrier film is penetrated.
Compared with the prior art, the technical scheme provided by the embodiment of the invention has the following advantages:
under the first etching condition, the etching rate of the functional layer is less than that of the first dielectric layer, namely, the functional layer has higher etching selection ratio relative to the first dielectric layer, so that etching can be stopped at the functional layer, and a first through hole which extends from the interlayer dielectric film to the functional layer and penetrates through the interlayer dielectric film and the barrier film is formed; the barrier film is arranged between the functional layer and the interlayer dielectric film, and because the etching rate of the barrier film is lower than that of the interlayer dielectric film under the first etching condition, namely, the barrier film has higher etching selection ratio relative to the interlayer dielectric film, so that a second through hole which extends from the interlayer dielectric film to the barrier film and penetrates through the interlayer dielectric film can be formed when the interlayer dielectric film is etched, the structure effectively avoids the situation that the barrier film is not arranged between the functional layer and the interlayer dielectric film, the etching amount of the second through hole can not be ensured when the second through hole is etched, the etching of the second through hole can not effectively stay at a fixed depth, so that the barrier film can block the continuous etching when the interlayer dielectric film is etched to form the second through hole, the second through hole has a fixed depth, and the uniformity of the thickness of the first metal film arranged in the second through hole is ensured, i.e. uniformity of the capacitance value is ensured.
Drawings
One or more embodiments are illustrated by way of example in the accompanying drawings, which correspond to the figures in which like reference numerals refer to similar elements and which are not to scale unless otherwise specified.
Fig. 1 is a schematic structural diagram of a display panel according to a first embodiment of the present invention;
fig. 2 is a flowchart of a method of manufacturing a display panel according to a third embodiment of the present invention;
fig. 3 is a flowchart of a method of manufacturing a display panel according to a fourth embodiment of the present invention;
fig. 4 is a schematic structural diagram of a process of forming a display panel according to a fourth embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention more apparent, embodiments of the present invention will be described in detail below with reference to the accompanying drawings. However, it will be appreciated by those of ordinary skill in the art that numerous technical details are set forth in order to provide a better understanding of the present invention in its various embodiments. However, the technical solution claimed in the present invention can be implemented without these technical details and various changes and modifications based on the following embodiments.
The first embodiment of the present invention relates to a display panel 100, which is specifically configured as shown in fig. 1, and includes:
the substrate 1, the functional layer 2, the first dielectric layer 3, the barrier film 301 and the interlayer dielectric film 4 are sequentially stacked, the etching rate of the barrier film 301 under a first etching condition is smaller than that of the interlayer dielectric film 4, the etching rate of the functional layer 2 under the first etching condition is smaller than that of the first dielectric layer 3, and the etching rate of the barrier film 301 under a second etching condition is larger than that of the first dielectric layer 3; a first through hole 10, wherein the first through hole 10 extends from the interlayer dielectric film 4 to the functional layer 2, and the first through hole 10 penetrates through the interlayer dielectric film 4 and the barrier film 301; a second via 20, the second via 20 extending from the interlayer dielectric film 4 to the barrier film 301, and the second via 20 penetrating through the interlayer dielectric film 4; a first metal film 5, the first metal film 5 being disposed within the second via 20.
Specifically, the substrate 1 may be a glass substrate, CPI (transparent polyimide), PI (polyimide), PET (high temperature polyester), PEN (polyethylene naphthalate), or the like, and the material of the substrate 1 is not specifically limited in this embodiment, and different materials may be selected according to actual requirements to manufacture the substrate 1.
In practical applications, the display panel 100 may be used for a full-screen, wherein the first through hole 10 may be disposed in the array region, the second through hole 20 may be disposed in the bending region, and the bending region is disposed around the array region, so that the bending region disposed around the array region can be bent toward the reverse direction of the display surface, thereby forming the full-screen, and the functional layer 2 is not disposed in the bending region, so that the structure of the functional layer 2 is not damaged in the process of forming the second through hole 20.
It can be understood that the display panel 100 may also be used for a flexible display screen, and the first through hole 10 and the second through hole 20 may be both disposed in the array region, and the second through hole is disposed in an area of the first dielectric layer 3 that is not covered by the functional layer 2, so that the flexible display screen can perform flexible display such as curling and folding on the premise of ensuring the reliability of the functional layer 2.
It should be noted that the first etching condition in this embodiment may be to etch the interlayer dielectric film 4 and the first dielectric layer 3 by using carbon tetrafluoride and oxygen as etching gases; the second etching condition may be to etch the barrier film 301 using chlorine gas as an etching gas.
Compared with the prior art, in the embodiment of the invention, under the first etching condition, the etching rate of the functional layer 2 is lower than that of the first dielectric layer 3, that is, the functional layer 2 has higher etching selectivity ratio relative to the first dielectric layer 3, so that etching can stay in the functional layer 2, and a first through hole 10 which extends from the interlayer dielectric film 4 to the functional layer 2 and penetrates through the interlayer dielectric film 4 and the barrier film 301 is formed; the barrier film 301 is arranged between the functional layer 2 and the interlayer dielectric film 4, because under the first etching condition, the etching rate of the barrier film 301 is less than that of the interlayer dielectric film 4, that is, the barrier film 301 has higher etching selection ratio relative to the interlayer dielectric film 4, so that a second through hole which extends from the interlayer dielectric film 4 to the barrier film 301 and penetrates through the interlayer dielectric film 4 can be formed when the interlayer dielectric film 4 is etched, through the arrangement of the structure, the situation that the etching amount of the second through hole 20 cannot be ensured and the etching of the second through hole 20 cannot effectively stay at a fixed depth because the barrier film 301 is not arranged between the functional layer 2 and the interlayer dielectric film 4 is effectively avoided, so that the barrier film 301 can block the continuous etching when the interlayer dielectric film 4 is etched to form the second through hole 20, and the second through hole 20 has a fixed depth is avoided, uniformity of the thickness of the first metal film 5 disposed in the second via hole 20, that is, uniformity of the capacitance value of the display panel 100 is ensured.
The following describes the implementation details of the display panel 100 of the present embodiment in detail, and the following is only provided for the convenience of understanding and is not necessary for implementing the present embodiment.
In this embodiment, as shown in fig. 1, the first dielectric layer 3 includes a gate insulating film 31 and a capacitor dielectric film 32 located on a side of the gate insulating film 31 away from the functional layer 2, the barrier film 301 is disposed between the capacitor dielectric film 32 and the interlayer dielectric film 4, and an etching rate of the barrier film 301 under the second etching condition is greater than an etching rate of the capacitor dielectric film 32. With such a configuration, the capacitance value of the display panel 100 can be further increased. Specifically, since the etching rate of the barrier film 301 under the second etching condition is greater than that of the capacitor dielectric film 32, which indicates that the capacitor dielectric film 32 has a high selectivity ratio, that is, the etching rate of the material used for etching the barrier film 301 to the capacitor dielectric film 32 is extremely low, the etching can be stopped at the capacitor dielectric film 32, so that the first dielectric layer 3 and the interlayer dielectric film 4 can be etched simultaneously in the subsequent process to form the first through hole 10 and the second through hole 20, and thus the requirements of different depths of the first through hole and the second through hole can be met; meanwhile, the capacitance of the display panel 100 can be increased due to the capacitor dielectric film 32, and the performance of the capacitor structure can be improved.
It is understood that the material of the gate insulating film 31 may be silicon oxide, the thickness of the gate insulating film 31 ranges from 110 nm to 130 nm, preferably 120 nm, and the thickness of the gate insulating film 31 needs to meet the sub-threshold swing (usually about 0.3) required by the display panel 100; the material of the capacitor dielectric film 32 may be silicon nitride, and since the sum of the thickness of the capacitor dielectric film 32 and the thickness of the barrier film 301 determines the pixel capacitance of the display panel 100, the thickness of the capacitor dielectric film 32 may be set according to actual requirements, which is not specifically limited in this embodiment. Specifically, K-d-K1-K2/(K1-d- (K1-K2) d1) and d-d 1+ d2, where K is the dielectric constant of the entire capacitive medium of the display panel 100, K1 is the dielectric constant of the barrier film 301, d1 is the thickness of the first barrier film 301, K2 is the dielectric constant of the gate insulating film 31, and d2 is the thickness of the gate insulating film 31, and the thickness of the barrier film 301 can be calculated from the dielectric constant of the entire capacitive medium of the device. The gate insulating film 31 may be made of silicon oxide or the like, and the capacitor dielectric film 32 may be made of silicon nitride or the like.
Specifically, the display panel 100 further includes a second metal film 6, the second metal film 6 and the capacitor dielectric film 32 are disposed on the same layer, a portion of the capacitor dielectric film 32 is disposed between the first metal film 5 and the second metal film 6, and an orthographic projection of the second metal film 6 on the substrate 1 overlaps an orthographic projection of the first metal film 5 on the substrate 1. That is, the second metal film 6 is disposed on the side of the gate insulating film 31 away from the substrate 1, and the second metal film 6, the capacitance dielectric film 32, the barrier film 301 and the first metal 5 together form a capacitance of the display panel 100, and the capacitance dielectric film 32 and the barrier film 301 are dielectric layers of the capacitance.
It can be understood that the display panel 100 further includes a second dielectric layer 7 disposed between the substrate 1 and the functional layer 2, in this embodiment, an orthographic projection of the functional layer 2 on the substrate 1 is located in an orthographic projection of the second dielectric layer 7 on the substrate 1, and an orthographic projection of the second through hole 20 on the substrate 1 is independent from an orthographic projection of the functional layer 2 on the substrate 1, that is, the functional layer 2 is a patterned layer having a predetermined pattern, the functional layer 2 does not completely cover the second dielectric layer 7, and the second through hole 20 is disposed in an area of the second dielectric layer 7 not covered by the functional layer 2, so that in a process of forming the second through hole 20, a structure of the functional layer 2 is not damaged, a function of the functional layer 2 is not affected, and reliability of the functional layer 2 is improved. The functional layer 2 may be a PSI (active layer), the thickness of the functional layer 2 is 0.1 to 0.3 micrometers, and the first metal film 5 is further disposed in the first via hole 10, that is, the first via hole is used to connect the functional layer 2 and the first metal film 5. It is to be noted that the functional layer 2 and the gate insulating film 31 are provided in the same layer in this embodiment, and a part of the gate insulating film 31 is provided between the functional layer 2 and the second metal film 6. With this structure, the gate insulating film 31 can be used as an insulating layer between the second metal film 6 (gate electrode) and the functional layer 2 (active layer), thereby reducing leakage current and improving the stability of the display panel 100.
In addition, the second dielectric layer 7 is a laminated structure of a silicon oxide layer and a silicon nitride layer, the thickness of the silicon nitride layer is generally 40 to 60 nanometers, preferably 50 nanometers, and the thickness of the silicon oxide layer is generally 240 to 250 nanometers, preferably 250 nanometers, it can be understood that, by arranging the second dielectric layer 7 between the substrate 1 and the functional layer 2, external water and oxygen can be isolated from entering the functional layer 2, so that the reliability of the display panel 100 is improved, in addition, since a laser process is required when the functional layer 2 is prepared, the substrate 1 can be prevented from being damaged when the functional layer 2 is formed by arranging the second dielectric layer 7 on the substrate 1 and arranging the functional layer 2 on the second dielectric layer 7, so that the reliability of the display panel 100 is further improved.
It should be noted that the barrier film 301 in this embodiment is made of a material with a high dielectric constant, and may be an oxide or a nitride, specifically, the barrier film 301 may be made of a heavy metal oxide, a heavy metal nitride, or alumina; preferably, the barrier film 301 is made of zirconium oxide or hafnium oxide. By forming the barrier film 301 from the above-described material, the barrier film 301 can have a high dielectric constant, which is also referred to as a dielectric constant or a relative permittivity, which is a ratio of capacitance when the same substance is used as a dielectric and a vacuum in the same capacitor, and indicates a relative capacity of the dielectric to store electrostatic energy in an electric field, that is, the capacitance of a capacitor formed using the material is increased as the dielectric constant of the material is increased, and thus, the capacitance of the capacitor can be effectively increased by forming the barrier film 301 from a heavy metal oxide, a heavy metal nitride, or alumina. It is to be understood that the barrier film 301 is not limited to any particular material, and those skilled in the art can select the above-mentioned materials or other materials capable of providing the barrier film 301 with a high dielectric constant according to actual needs.
Specifically, the interlayer dielectric layer 4 includes a silicon oxide layer 41 and a silicon nitride layer 42. The interlayer dielectric layer 4 is used for isolating the first metal film 5 and the second metal film 6 in other regions of the display panel 100, so as to perform an insulating function, reduce the parasitic capacitance of the display panel 100, and avoid the phenomena of overall power consumption increase and signal delay of the display panel 100 caused by the overlarge parasitic capacitance.
A second embodiment of the present invention relates to a display device including the display panel described above. The display device has uniform capacitance.
A third embodiment of the present invention relates to a method for manufacturing a display panel, and a specific flow of the present embodiment is shown in fig. 2, including:
s301: a substrate is provided.
In step S301, the substrate may be a glass substrate, or may be made of a flexible material, for example: the polymer material is formed of polymer materials such as imide (PI), Polycarbonate (PC), Polyethersulfone (PES), polyethylene terephthalate (PET), polyethylene naphthalate (PEN), Polyarylate (PAR), or glass Fiber Reinforced Plastic (FRP). The substrate may be transparent, translucent, or opaque to provide support for the formation of various film layers disposed thereon. The material of the substrate is not particularly limited in this embodiment.
S302: a functional layer, a first dielectric layer, a barrier film and an interlayer dielectric film are sequentially stacked on a substrate.
In step S302, specifically, the etching rate of the barrier film under the first etching condition is less than the etching rate of the interlayer dielectric film, the etching rate of the functional layer under the first etching condition is less than the etching rate of the first dielectric layer, the etching rate of the barrier film under the second etching condition is greater than the etching rate of the first dielectric layer, the material of the barrier film may be one of HfO2, TiO2, HfZrO, HfSiNO, Ta2O5, ZrO2, ZrSiO2, Al2O3, SrTiO3, or BaSrTiO, or any combination thereof, the thickness of the barrier film ranges from 300 angstroms to 900 angstroms, the specific thickness depends on the capacitance requirement of the device, the forming process of the barrier film may be ALD (atomic layer deposition) or CVD (chemical vapor deposition), and the like, and the material of the interlayer dielectric film may be silicon oxide, silicon nitride, and the like.
It is understood that a second dielectric layer is also formed on the substrate, and the second dielectric layer is disposed between the substrate and the functional layer. The second dielectric layer is a laminated structure of a silicon oxide layer and a silicon nitride layer, the thickness of the silicon nitride layer is generally 40-60 nanometers, preferably 50 nanometers, the thickness of the silicon oxide layer is generally 240-250 nanometers, preferably 250 nanometers, it can be understood that the second dielectric layer is arranged between the substrate and the functional layer, external water and oxygen can be isolated from entering the functional layer, and the reliability of the display panel is improved.
S303: and carrying out initial etching treatment on the interlayer dielectric film and the barrier film which are opposite to the functional layer until the barrier film penetrates through the barrier film so as to form a first pre-through hole.
In step S303, specifically, since the interlayer dielectric film is usually made of silicon nitride and silicon oxide, the interlayer dielectric film is etched by using carbon tetrafluoride and oxygen (a first etching process), and the etching may stay on the barrier film with a high selectivity ratio, and then the etching of the barrier film is performed by using chlorine (a second etching process) until the etching penetrates through the barrier film and stays on the first dielectric layer with a high selectivity ratio, so as to form the first pre-via.
S304: etching the bottom of the first pre-through hole to form a first through hole extending from the interlayer dielectric film to the functional layer; and etching the interlayer dielectric film and the capacitance region of the barrier film which is not etched to form a second through hole extending from the interlayer dielectric film to the barrier film.
In step S304, specifically, after the first pre-via is formed, since the material of the first dielectric layer is the same as the material of the interlayer dielectric film, carbon tetrafluoride and oxygen may be used to simultaneously etch the bottom of the first pre-via (i.e., the surface of the first dielectric layer) and the capacitor region where the interlayer dielectric film is not etched, the etching of the capacitor region where the interlayer dielectric film is not etched remains on the barrier film, and the etching of the first pre-via remains on the functional layer, so as to form the first via and the second via with different depths.
S305: a metal film is formed in the second via hole.
In step S305, specifically, a metal film may be deposited in the second through hole by physical vapor deposition, in this embodiment, the metal film may be a single-layer structure made of molybdenum or a composite structure made of titanium-aluminum-titanium, the thickness of the metal film of the single-layer molybdenum structure is 200 nm to 300 nm, and the electrode plate in this thickness range can effectively reduce the overall thickness of the capacitor, so as to reduce the overall thickness of the display panel and improve the bending performance of the display panel; the thickness of the metal film of the laminated titanium-aluminum-titanium structure is 700 nanometers to 800 nanometers, and the metal film of the structure has high resistivity and strong conductivity and can release the stored charges of the capacitor more quickly.
Compared with the prior art, the etching rate of the functional layer is lower than that of the first dielectric layer under the first etching condition, namely, the functional layer has higher etching selectivity ratio relative to the first dielectric layer, so that etching can stay at the functional layer, and a first through hole which extends from the interlayer dielectric film to the functional layer and penetrates through the interlayer dielectric film and the barrier film is formed; the barrier film is arranged between the functional layer and the interlayer dielectric film, and because the etching rate of the barrier film is lower than that of the interlayer dielectric film under the first etching condition, namely, the barrier film has higher etching selection ratio relative to the interlayer dielectric film, so that a second through hole which extends from the interlayer dielectric film to the barrier film and penetrates through the interlayer dielectric film can be formed when the interlayer dielectric film is etched, the structure effectively avoids the situation that the barrier film is not arranged between the functional layer and the interlayer dielectric film, the etching amount of the second through hole can not be ensured when the second through hole is etched, the etching of the second through hole can not effectively stay at a fixed depth, so that the barrier film can block the continuous etching when the interlayer dielectric film is etched to form the second through hole, the second through hole has a fixed depth, and the uniformity of the thickness of the first metal film arranged in the second through hole is ensured, i.e. uniformity of the capacitance value is ensured.
A fourth embodiment of the present invention relates to a method for manufacturing a display panel, and the present embodiment is further improved on the basis of the third embodiment, and the specific improvements are as follows: in this embodiment, before performing the initial etching process on the interlayer dielectric film and the barrier film facing the functional layer, the method further includes: and forming a patterned mask layer on the interlayer dielectric film, wherein the mask layer is internally provided with a first groove and a second groove, the bottom of the first groove is positioned in the mask layer, and the second groove penetrates through the mask layer.
As shown in fig. 3, a specific flow of the present embodiment includes:
s401: a substrate is provided.
S402: a functional layer, a first dielectric layer, a barrier film and an interlayer dielectric film are sequentially stacked on a substrate.
S403: and forming a mask layer with a first groove and a second groove on the interlayer dielectric film.
In step S403, specifically, the bottom of the first groove is located in the mask layer, and the second groove penetrates through the mask layer, in other words, the first groove does not penetrate through the mask layer, and the second groove penetrates through the mask layer.
In practical application, a whole photoresist layer (which may be a photoresist) may be formed on an interlayer dielectric layer, and then, a semi-permeable mask is used to perform a half exposure process on the photoresist layer at a first position, perform a full exposure process on the photoresist layer at a second position, and perform a development process on the photoresist layer, so that the first groove is formed at the first position and the second groove is formed at the second position, that is, a mask layer is formed.
S404: and taking the mask layer as a mask, and carrying out initial etching treatment on the interlayer dielectric film and the barrier film along the second groove to form a first pre-through hole penetrating through the barrier film.
Regarding step S404, specifically, the initial etching process in this embodiment may be: etching the interlayer dielectric film along the second groove by using the mask layer as a mask through a first etching process until the barrier film is exposed; and etching the barrier film by using a second etching process until the barrier film is penetrated. It is worth mentioning that the first etching process can be to etch the interlayer dielectric film by using carbon tetrafluoride and oxygen as etching gases; the second etching process may be to etch the barrier film using chlorine gas as an etching gas.
S405: and thinning the mask layer to enable the first groove to penetrate through the mask layer.
In step S405, specifically, the bottom of the first groove after the thinning process extends to the interlayer dielectric layer, in this step, the thinning process may be performed on the mask layer for a short time Asher (i.e., ashing process), and specifically, the gas after the thinning process may be oxygen, so as to remove the photoresist on the surface of the first groove, and make the first groove penetrate through the mask layer. Of course, the thinning process may be performed in other manners as long as the entire surface of the mask layer can be thinned so that the first groove penetrates through the mask layer, and a specific manner is not limited.
S406: and etching the interlayer dielectric film along the first groove by taking the mask layer as a mask so as to expose the barrier film to form a second through hole, and simultaneously etching the bottom of the first pre-through hole so as to expose the functional layer to form a first through hole.
S407: a metal film is formed in the second via hole.
Steps S401 to S402 and S407 of the present embodiment are similar to steps S301 to S302 and S305 of the third embodiment, and are not repeated herein to avoid redundancy.
For convenience of understanding, the formation of the first through hole and the second through hole in the present embodiment will be specifically described below:
as shown in fig. 4(a), a second dielectric layer 7, a functional layer 2, a first dielectric layer 3, a barrier film 301, and an interlayer dielectric film 4 are formed on a substrate 1 in this order; as shown in fig. 4(b), a mask layer 8 having a first recess 81 and a second recess 82 is formed on the interlayer dielectric film 4, the bottom of the first recess 81 is located in the mask layer 8, and the second recess 82 penetrates through the mask layer 8; as shown in fig. 4(c), the interlayer dielectric film 4 is etched using carbon tetrafluoride and oxygen, and the etching process is effectively stopped at the barrier film 301 using the barrier film 301 as an etching barrier; as shown in fig. 4(d), etching of the barrier film 301 is performed using chlorine gas, the etching is stopped at the first dielectric layer 3, and a first pre-via 101 is formed; as shown in fig. 4(e), the first groove 81 is thinned, so that the first groove 81 penetrates through the mask layer 8; as shown in fig. 4(f), carbon tetrafluoride and oxygen are used to simultaneously etch the first pre-via 101 and the dielectric layer in the capacitor area, and the functional layer 2 and the barrier film 301 which are stopped at a high selectivity are etched to form a first via 10 and a second via 20; as shown in fig. 4 g, PVD (physical vapor deposition) deposition of the metal film 9 is performed to form a capacitor structure.
Compared with the prior art, the etching rate of the functional layer is lower than that of the first dielectric layer under the first etching condition, namely, the functional layer has higher etching selectivity ratio relative to the first dielectric layer, so that etching can stay at the functional layer, and a first through hole which extends from the interlayer dielectric film to the functional layer and penetrates through the interlayer dielectric film and the barrier film is formed; the barrier film is arranged between the functional layer and the interlayer dielectric film, and because the etching rate of the barrier film is lower than that of the interlayer dielectric film under the first etching condition, namely, the barrier film has higher etching selection ratio relative to the interlayer dielectric film, so that a second through hole which extends from the interlayer dielectric film to the barrier film and penetrates through the interlayer dielectric film can be formed when the interlayer dielectric film is etched, the structure effectively avoids the situation that the barrier film is not arranged between the functional layer and the interlayer dielectric film, the etching amount of the second through hole can not be ensured when the second through hole is etched, the etching of the second through hole can not effectively stay at a fixed depth, so that the barrier film can block the continuous etching when the interlayer dielectric film is etched to form the second through hole, the second through hole has a fixed depth, and the uniformity of the thickness of the first metal film arranged in the second through hole is ensured, i.e. uniformity of the capacitance value is ensured.
The steps of the above methods are divided for clarity, and the implementation may be combined into one step or split some steps, and the steps are divided into multiple steps, so long as the same logical relationship is included, which are all within the protection scope of the present patent; it is within the scope of the patent to add insignificant modifications to the algorithms or processes or to introduce insignificant design changes to the core design without changing the algorithms or processes.
It will be understood by those of ordinary skill in the art that the foregoing embodiments are specific examples for carrying out the invention, and that various changes in form and details may be made therein without departing from the spirit and scope of the invention in practice.
Claims (10)
1. A display panel, comprising:
the substrate, the functional layer, the first dielectric layer, the barrier film and the interlayer dielectric film are stacked, the etching rate of the barrier film under a first etching condition is smaller than that of the interlayer dielectric film, the etching rate of the functional layer under the first etching condition is smaller than that of the first dielectric layer, and the etching rate of the barrier film under a second etching condition is larger than that of the first dielectric layer;
the first through hole extends from the interlayer dielectric film to the functional layer and penetrates through the interlayer dielectric film and the barrier film;
the second through hole extends from the interlayer dielectric film to the barrier film and penetrates through the interlayer dielectric film;
a first metal film disposed within the second via.
2. The display panel according to claim 1, wherein the first dielectric layer comprises a gate insulating film and a capacitor dielectric film located on a side of the gate insulating film away from the functional layer, wherein the barrier film is disposed between the capacitor dielectric film and the interlayer dielectric film, and an etching rate of the barrier film under the second etching condition is greater than an etching rate of the capacitor dielectric film.
3. The display panel according to claim 2, wherein the display panel further comprises a second metal film, the second metal film is disposed on the same layer as the capacitor dielectric film, and a portion of the capacitor dielectric film is disposed between the first metal film and the second metal film, and an orthographic projection of the second metal film on the substrate overlaps an orthographic projection of the first metal film on the substrate.
4. The display panel according to claim 1, further comprising a second dielectric layer disposed between the substrate and the functional layer, wherein an orthogonal projection of the functional layer on the substrate is located within an orthogonal projection of the second dielectric layer on the substrate, and an orthogonal projection of the second via on the substrate is independent of an orthogonal projection of the functional layer on the substrate.
5. A display device characterized by comprising the display panel according to any one of claims 1 to 4.
6. A method for manufacturing a display panel, comprising:
providing a substrate;
forming a functional layer, a first dielectric layer, a barrier film and an interlayer dielectric film which are stacked on the substrate, wherein the etching rate of the barrier film under a first etching condition is less than that of the interlayer dielectric film, the etching rate of the functional layer under the first etching condition is less than that of the first dielectric layer, and the etching rate of the barrier film under a second etching condition is greater than that of the first dielectric layer;
carrying out initial etching treatment on the interlayer dielectric film and the barrier film which are opposite to the functional layer until the barrier film penetrates through the barrier film so as to form a first pre-through hole;
etching the bottom of the first pre-through hole to form a first through hole extending from the interlayer dielectric film to the functional layer; performing the etching treatment on the capacitance area of the interlayer dielectric film which is not etched to form a second through hole extending from the interlayer dielectric film to the barrier film;
and forming a metal film in the second through hole.
7. The method for manufacturing a display panel according to claim 6, further comprising, before the initial etching treatment of the interlayer dielectric film and the barrier film facing the functional layer:
forming a patterned mask layer on the interlayer dielectric film, wherein the mask layer is internally provided with a first groove and a second groove, the depth of the first groove is smaller than the thickness of the mask layer, and the second groove penetrates through the mask layer;
the method for forming the pre-through hole comprises the following steps of performing initial etching treatment on the interlayer dielectric film and the barrier film opposite to the functional layer until the interlayer dielectric film and the barrier film penetrate through the barrier film to form a first pre-through hole, and specifically comprises the following steps:
and carrying out initial etching treatment on the interlayer dielectric film and the barrier film along the second groove by taking the mask layer as a mask to form a first pre-through hole penetrating through the barrier film.
8. The method for manufacturing a display panel according to claim 7, further comprising, after the forming of the first pre-via penetrating the barrier film and before etching a bottom of the first pre-via:
thinning the mask layer to enable the first groove to penetrate through the mask layer;
the process steps for forming the first via and the second via include:
and etching the interlayer dielectric film along the first groove by taking the mask layer as a mask to expose the barrier film to form the second through hole, and simultaneously etching the bottom of the first pre-through hole to expose the functional layer to form the first through hole.
9. The method according to claim 8, wherein the thinning the mask layer to make the first groove penetrate through the mask layer specifically comprises:
and in the process of forming the first pre-through hole or after forming the first pre-through hole, performing thinning treatment on the mask layer by adopting an ashing process, wherein the mask layer is made of photoresist.
10. The method according to claim 7, wherein the initial etching process specifically comprises:
etching the interlayer dielectric film along the second groove by using the mask layer as a mask through a first etching process until the barrier film is exposed; and etching the barrier film by using a second etching process until the barrier film is penetrated.
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