JP2004320213A - Image ring bridge system and image ring bridge apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an image ring bridge system and an image ring bridge apparatus for providing higher processing capability by removing restrictions of an implemented CL packet at present, which realizes 15 image processing chips at maximum, eight consecutive image processes, and single a GuBus only. <P>SOLUTION: The image ring bridge system has two sets of image rings, a bridge circuit transferring data between them, uses particular data in data packets for an index, temporarily stores partial data in the data packets, replaces the data with other preset data, transmits the resultant data to the second image ring, uses the particular data in the returned data packets circulated through the second image ring for the index again, rewrites part of the data packets by the temporarily stored data, and transmits the resultant data to the first image ring. The circuit discriminates the transfer depends on a result of comparison of a packet identifier with preset values. When the packet identifier is coincident with any of a plurality of the preset values, the circuit transmits the packets to the second image ring and when dissident, the circuit transmits the packets to the first image ring. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image ring bridge system and an image ring bridge device, and more particularly to a data transfer unit that handles tiled image data as a packet and transfers the packet (data packet) between a plurality of processing blocks via an image ring. And an apparatus.
[0002]
[Prior art]
2. Description of the Related Art Conventionally, as shown in Japanese Patent Application No. 2001-024168, there has been proposed a controller for a multifunction peripheral that performs image processing and data transfer by transferring data packets via an image ring.
[0003]
[Problems to be solved by the invention]
However, in the above method, only a single ChipID can be stored in a single data packet, and the data packet transmitted from the system control unit is continuously image-processed by a plurality of image processing blocks. I could not do it.
[0004]
In addition, Process Instruction, which is an indicator of the image data processing method, is limited to eight entries, and eight or more processes cannot be performed continuously.
[0005]
Furthermore, since the ChipID is composed of 4 bits and the system control unit reserves 0, there is a restriction that the image processing unit can connect up to 15 at the maximum.
[0006]
There is a restriction that these data packet fields cannot be easily changed to ensure compatibility.
[0007]
Further, in the conventional method, only one set of image rings is provided in the system, and there is a possibility that the image rings limit the system performance when transferring a large amount of data.
[0008]
The present invention has been made in view of the above-mentioned problems, and the presently proposed and implemented CL packet can realize only an image processing chip of up to 15 chips, image processing of 8 consecutive images, and a single GuBus. It is an object of the present invention to provide an image ring bridge system and an image ring bridge device which can realize higher processing performance by removing restrictions such as the above and dispersing GuBus image transfer.
[0009]
[Means for Solving the Problems]
In order to solve the above problems, the present invention has the following configurations.
[0010]
A data packet including at least one packet identifier unique to each packet set, image data, an image data processing method indicator, ChipID,
Ring-shaped first data packet transfer means for transferring the data packet,
Ring-shaped second data packet transfer means for transferring the data packet,
The first data packet transfer means, and a data packet routing means connected to the second data packet transfer means,
In the above function packet routing means,
A data packet transfer path for outputting a data packet input from the first data packet transfer means to the first data packet transfer means,
A packet identification information register for storing at least one pair of information equivalent to the packet identifier,
Comparing means for comparing the packet identification information register with the packet identifier of the input data packet;
A first register group capable of setting a plurality of sets of information equivalent to ChipID in the data packet and an indicator of an image data processing method;
A second register group capable of holding information equivalent to the ChipID in the data packet and an indicator of the image data processing method;
In the register specified by the packet identifier of the data packet input from the first image ring, an indicator of the image data processing method of the data packet input from the first image ring is set based on the result of the comparison means. Means to write,
Means for transferring a data packet input from the first image ring to the second image ring,
Means for changing the ChipID and the indicator of the image data processing method to the value read from the first register group at the time of the transfer;
Means for transferring a data packet input from the second image ring to the first image ring,
Means for changing the indicator of the image data processing method in the data packet to the indicator of the image data processing method read from the second register group, based on the content of the packet identifier,
By having.
[0011]
In the result of the packet identifier comparison means, if the packet identifier matches the value set in advance, after temporarily storing the original image data processing indicator, the image data indicator and the ChipID are changed, and the data packet is changed. Send to the second image ring. On the other hand, if they do not match, the data packet is sent to the first image ring without changing the content. The data packet input from the second image ring transmits the temporarily stored image data processing indicator and the data packet in which the ChipID is inserted to the first image ring based on the packet identifier.
[0012]
The above configuration will be described again in the following (1) to (4).
[0013]
(1) a data packet including at least one packet identifier unique to each packet set, image data, an indicator of a processing method for the image data, and a ChipID for designating a processing unit on which the image data is processed;
Ring-shaped first data packet transfer means for transferring the data packet,
Ring-shaped second data packet transfer means for transferring the data packet,
The first data packet transfer means, and an image ring bridge connected to the second data packet transfer means,
In the above image ring bridge,
A data packet transfer path for outputting a data packet input from the first data packet transfer means to the first data packet transfer means,
A packet identification information register for storing at least one set of information equivalent to the packet identifier;
Comparing means for comparing the packet identification information register with the packet identifier of the input data packet;
A first register group capable of setting a plurality of sets of information equivalent to ChipID in the data packet and an indicator of an image data processing method;
A second register group capable of holding information equivalent to the ChipID in the data packet and an indicator of the image data processing method;
In the register specified by the packet identifier of the data packet input from the first image ring, an indicator of the image data processing method of the data packet input from the first image ring is set based on the result of the comparison means. Means to write,
Means for transferring a data packet input from the first image ring to the second image ring,
Means for changing the ChipID and the indicator of the image data processing method to the value read from the first register group at the time of the transfer;
Means for transferring a data packet input from the second image ring to the first image ring,
Means for changing the indicator of the image data processing method in the data packet to the indicator of the image data processing method read from the second register group, based on the content of the packet identifier,
An image ring bridge system comprising:
[0014]
(2) An image ring bridge device wherein the means described in (1) is integrated on a single semiconductor substrate.
[0015]
(3) The image ring bridge system according to (1), wherein the image data in the data packet is rectangular data.
[0016]
(4) An image ring bridge device wherein the means described in (2) above is integrated on a single semiconductor substrate.
[0017]
By the above means, a means for enabling a plurality of image rings to be mounted in the system is provided.
[0018]
BEST MODE FOR CARRYING OUT THE INVENTION
Hereinafter, the device of the present invention and its operation will be described in detail.
[0019]
<overall structure>
FIG. 3 shows a block diagram of a controller according to the present invention.
[0020]
The Controller Unit 2000 is a controller for connecting to a scanner 2070 as an image input device and a printer 2095 as an image output device, and connecting to a LAN 2011 to input and output image information and device information and to develop an image of PDL data. . 2150 is a system control unit. Reference numerals 2149 and 2151 denote image processing units, and 2008 denotes an image ring. The system processing unit 2150 and the image processing units 2149 and 2151 are connected in a ring by a series of image rings 1 (2008). I have. 2002 is a RAM, and 2003 is a ROM.
[0021]
FIG. 3 shows an example in which a general-purpose PCI bus 2143, a disk controller 2144, an Ethernet (R) PHY / PMD 2146, and a UI 2012 are connected to the system control unit 2150.
[0022]
The printer 2095 is connected to the image processing unit 1 (2149).
[0023]
The scanner 2070 and the image memory 2 (2155) are connected to the image processing unit 2151.
[0024]
An HDD 2004 is a hard disk drive that stores system software and image data. It is connected to one PCI bus 2143 via a disk controller 2144.
[0025]
FIG. 4 shows details of the system control unit 2150.
[0026]
The CPU 2001 is a processor that controls the entire system. In this embodiment, an example using two CPUs will be described. These two CPUs are connected to a common CPU bus 2126 and further to a system bus bridge 2007.
[0027]
The system bus bridge 2007 is a bus switch, and includes a CPU bus 2126, a RAM controller 2124, a ROM controller 2125, an IO bus 1 (2127), an IO bus 2 (2129), an image ring interface 1 (2147), and an image ring interface 2 ( 2148) is connected.
[0028]
A RAM 2002 is a system work memory for the operation of the CPU 2001, and is also an image memory for temporarily storing image data. It is controlled by the RAM controller 2124.
[0029]
The ROM 2003 is a boot ROM, and stores a system boot program. It is controlled by the ROM controller 2125.
[0030]
The IO bus 1 (2127) is a type of internal IO bus, and is connected to a controller of a USB bus which is a standard bus, a USB interface 2138, a general-purpose serial port 2139, an interrupt controller 2140, and a GPIO interface 2141. IO bus 1 (2127) includes a bus arbiter (not shown).
[0031]
An operation unit interface 2006 includes an operation unit (UI) 2012 and an interface unit, and outputs image data to be displayed on the operation unit 2012 to the operation unit 2012. In addition, it plays a role of transmitting information input by the user of the system from the operation unit 2012 to the CPU 2001.
[0032]
The IO bus 2 (2129) is a kind of internal IO bus, and the general-purpose bus interfaces 1 and 2 (2142) and the LAN controller 2010 are connected. IO bus 2 (2129) includes a bus arbiter (not shown).
[0033]
The general-purpose bus interface 2142 is a bus bridge composed of two identical bus interfaces and supporting a standard IO bus. In this embodiment, an example in which the PCI bus 2143 is adopted has been described.
[0034]
A packet transfer means (hereinafter, image ring) interface 1 (2147) and an image ring interface 2 (2148) connect the system bus bridge 2007 and the image ring 1 (2008) for transferring image data at high speed, and convert the tiled data. Is a DMA controller that transfers data between the RAM 2002 and the image processing unit 2149.
[0035]
The image ring 1 (2008) is configured by a combination of a series of unidirectional connection paths (first packet transfer means, second packet transfer means, third packet transfer means).
[0036]
[Entire system]
FIG. 2 shows a configuration diagram of the entire network system of the present invention.
[0037]
Reference numeral 1001 denotes an apparatus according to the present invention, which includes a scanner and a printer, and allows an image read from the scanner to flow to a local area network 1010 (hereinafter, LAN) and prints out an image received from the LAN 1010 by the printer. Further, the image read from the scanner can be transmitted to the PSTN or ISDN 1030 by a facsimile transmission unit (not shown), or the image received from the PSTN or ISDN 1030 can be printed out by a printer. A database server 1002 manages a binary image and a multi-valued image read by the apparatus 1001 of the present invention as a database.
[0038]
Reference numeral 1003 denotes a database client of the database server 1002, which can browse / search image data stored in the database 1002.
[0039]
An email server 1004 can receive an image read by the apparatus 1001 of the present invention as an email attachment. Reference numeral 1005 denotes an e-mail client, which can receive and browse the e-mail received by the e-mail server 1004, and transmit e-mail.
[0040]
Reference numeral 1006 denotes a WWW server that provides an HTML document to the LAN, and the apparatus 1001 of the present invention can print out an HTML document provided by the WWW server 1006.
[0041]
The DNS server 1007 connects the LAN 1010 with the Internet / intranet 1012 via the router 1011. The above-described database server 1002, WWW server 1006, e-mail server 1004, and devices similar to the device 1001 of the present invention are connected to the Internet / intranet 1012 as 1020, 1021, 1022, and 1023, respectively. On the other hand, the apparatus 1001 of the present invention can transmit and receive to and from the FAX apparatus 1031 via the PSTN or ISDN 1030.
[0042]
A printer 1040 is also connected to the LAN 1010, and is configured to be able to print out an image read by the apparatus 1001 of the present invention.
[0043]
[Rectangle data (packet) format]
In the System Controller Unit 2000 according to the present invention, image data, commands from the CPU 2001, and interrupt information issued from each block are transferred in a packetized format.
[0044]
In this embodiment, three different types of packets are used: a data packet shown in FIG. 5, a command packet shown in FIG. 6, and an interrupt packet shown in FIG.
[0045]
Data packet (Fig. 5)
In the present embodiment, an example has been described in which the image Data is handled by being divided into image data 3002 of 32 pixels × 32 pixels in tile units.
[0046]
The necessary header information 3001 and additional image information 3003 are added to the image data 3002 in tile units to form a data packet.
[0047]
Hereinafter, information included in the header information 3001 will be described.
[0048]
The type of the packet is distinguished by the PckType 3004 in the header information 3001.
[0049]
The Chip ID 3005 indicates the ID of a chip that is a target for transmitting a packet.
[0050]
DataType 3006 indicates the type of data.
[0051]
Page ID 3007 indicates a page, and Job ID stores Job ID 3008 for management by software.
[0052]
The tile number is a combination of tile coordinates 3009 in the Y direction and tile coordinates 3010 in the X direction, and is represented by YnXn.
[0053]
Data packets may be compressed image data or uncompressed. In this embodiment, the case of no compression is shown.
[0054]
The distinction between the compressed case and the uncompressed case is indicated by CompressFlag 3017.
[0055]
The Process Instruction 3011 is set left-justified in the processing order, and each processing unit shifts the Process Instruction 3011 to the left by 8 bits after processing. The Process Instruction 3011 stores eight sets of a Unit ID 3019 and a Mode 3020. The Unit ID 3019 specifies each processing unit, and the Mode 3020 specifies the operation mode in each processing unit. Thus, one packet can be processed continuously by eight Units.
[0056]
Packet Byte Length 3012 indicates the total number of bytes of the packet.
[0057]
Image Data Byte Length 3015 indicates the number of bytes of the image data, Z Data Byte Length 3016 indicates the number of bytes of the image additional information, and Image Data Offset 3013 and Z Data Offset 3014 indicate the offset of each data from the head of the packet.
[0058]
Packet Table (Fig. 8)
Each Packet is managed by a Packet Table 6001.
[0059]
The components of the Packet Table 6001 are as follows. When 0 bits are added to the value of the Table by 5 bits, respectively, the first Address 6002 of the Packet and the Byte Length 6005 of the Packet are obtained.
[0060]
Packet Address Pointer (27 bits) + 5b00000 = Packet Top Address 6002
Packet Length (11 bits) + 5b00000 = Packet Length 6005 of Packet
It is assumed that the Packet Table 6001 and the Chain Table 6010 are not divided.
[0061]
Packet Table 6001 is always arranged in the scanning direction, and Yn / Xn = 000/00000 / 0011,000 / 002. . . . It is arranged in the order. The Entry of the Packet Table 6001 uniquely indicates one Tile. Further, the entry next to Yn / Xmax is Yn + 1 / X ₀ It becomes.
[0062]
If the Packet is exactly the same Data as the immediately preceding Packet, the Packet is not written in the Memory, and the same Packet AddressPointer and Packet Length as the first Entry are stored in the Entry of the Packet Table 6001. One Packet Data is indicated by two Table Entries. In this case, the Repeat Flag 6003 of the second Table Entry is set.
[0063]
When the packet is divided into a plurality of pieces by the Chain DMA, the Divide Flag 6004 is set, and the Chain Table number 6006 of the Chain Block including the head of the Packet is set.
[0064]
The Entry of the Chain Table 6010 is composed of a Chain Block Address 6011 and a Chain Block Length 6012, and 0 is stored in both the Address and the Length in the last Entry of the Table.
[0065]
Command Packet Format (Fig. 6)
This Packet Format can also access the image memory 1 (2123).
[0066]
The ChipID 4004 stores an ID representing the image processing unit 2149 to which the command packet is to be transmitted.
[0067]
Page ID 4007 and Job ID 4008 store a Page ID and a Job ID for management by software.
[0068]
PacketID 4009 is represented in one dimension. Only X-coordinate of Data Packet is used.
[0069]
The packet byte length 4010 is fixed at 128 bytes.
[0070]
The packet data section 4002 can store a maximum of 12 commands using a set of an address 4011 and data 4012 as one command. The type of command, write or read, is indicated by CmdType 4005, and the number of commands is indicated by Cmdnum 4006.
[0071]
Interrupt Packet Format (Fig. 7)
This Packet Format is for notifying an interrupt from the image processing unit 2149 to the CPU 2001.
[0072]
The packet byte length 5006 is fixed at 128 bytes.
[0073]
The packet data section 5002 stores status information 5007 of each internal module of the image processing section 2149.
[0074]
The ID representing the system control unit 2150 that is the destination of the Interrupt Packet is stored in the ChipID 5004, and the ID representing the image processing unit 2149 that is the source of the Interrupt Packet is stored in the IntChipID 5005.
[0075]
[Explanation of data flow]
Hereinafter, transfer of a data packet according to the present invention will be described with reference to FIG.
[0076]
First, the CPU 2001 sets the Page ID and Job ID of a page to be transferred from the first image ring to the second image ring of the data packet according to the present invention in the Page ID and Job ID register 5003.
[0077]
Subsequently, a value obtained by combining the above-described Page ID and Job ID is set as Index, a new Chip ID and Process Instruction are determined, and the new Chip ID and Process Instruction are set in the first register group 5021 using a command packet.
[0078]
If necessary, a plurality of sets of the above-described Page ID, Job ID, Chip ID, and Process Instruction are repeatedly set.
[0079]
After that, a data packet including the set PageID and JobID is transmitted to the image ring 1 using the image ring interface DMAC.
[0080]
The data packet sent to the image ring is first received by the TileIn block 5001. The received data packets are sequentially stored in data packet buffers 5104 to 5120. When all the contents of the data packet are completed, the Page ID 5107 and the Job ID 5108 are compared with the Page ID and the Job ID stored in the Job ID register 5003.
[0081]
If they do not match, the Miss signal 5025 is asserted, and the buffered data packet is output from the ImageData + Padding block 5102 to the image ring 1 (2008).
[0082]
If there is a match, the image ring bridge according to the invention will function, the operation of which is described below.
[0083]
The Page ID 5107 and the Job ID 5108 are compared with the Page ID and the Job ID stored in the Job ID register 5003, and if they match, the Hit signal 5023 is asserted.
[0084]
At the same time, the PageID and JobID in the input data packet are combined into an Index, and one of the entries of a register group (second register group) 5026 capable of storing a plurality of sets of ChipID and ProcessID is selected.
[0085]
In this embodiment, this register is configured using a dual-port SRAM.
[0086]
At the same time as the entry in the second register group 5026 is selected by the Index, the Chip ID and the Process Instruction of the input data packet are stored in the second register group 5026 by the Hit signal 5023.
[0087]
At the same time, the stored ChipID and ProcessInstruction are read from the first register group 5021 as the Index by combining the PageID and the JobID. The read ChipID and ProcessInstruction are stored in the output buffer 5027 for the image ring 2 (2009). Data other than ChipID and ProcessInstructin are copied from the input data buffers 5104 to 5120 of the image ring 1.
[0088]
Then, the TileOut block 5029 outputs the image signal to the image ring 2 (2009) in response to the asserted Hit signal 5023.
[0089]
The image processing unit 2149 shown in FIG. 3 is connected to the image ring 2 (2009), and performs image processing on the transmitted data packet. This processing is equivalent to that of Japanese Patent Application No. 2001-024168.
[0090]
The image data processed by the image processing unit connected to the image ring 2 (2009) is input to the TileIn block 5030 of the image ring 2 (2009).
[0091]
The Page ID and Job ID of the data packet returned after circling the image ring are not changed.
[0092]
The contents of the input data packet, except for the ChipID and ProcessInstruction, are copied to the data packet transfer buffer 5030 for the image ring 1.
[0093]
At the same time, the value obtained by combining the Page ID and the Job ID is set to Index, and the Chip ID and Process Instruction stored when the data packet is transferred from the image ring 1 (2008) to the image ring 2 (2009) are read from the second register group 5026. , Data packet transfer buffer 5030 for image ring 1 (2008).
[0094]
When the ChipID and ProcessInstruction are written to the data packet transfer buffer 5030, the TileIn block 5030 asserts the trans signal 5031.
[0095]
The ImageData + Padding block 5102 outputs the contents of the data packet transfer buffer 5030 to the image ring 1 (2008) by asserting the trans signal 5031.
[0096]
With the above means and operations, it is possible to mount a plurality of image rings in the system.
[0097]
【The invention's effect】
As described above, according to the present invention,
In the result of the packet identifier (PageID, JobID) comparing means, if the packet identifier matches any one of a plurality of preset values, the original image data processing indicator is temporarily stored, and then the image data indicator ( ProcessInstruction) and the ChipID are changed, and the data packet is transmitted to the second image ring. On the other hand, if they do not match, the data packet is sent to the first image ring without changing the content. The data packet input from the second image ring is a data packet in which the temporarily stored image data processing indicator (ProcessInstruction) and the ChipID are inserted based on the packet identifier (PageID, JobID) in the first image ring. Send out.
[0098]
By the above means, it is possible to implement a plurality of image rings in the system, to change the ChipID of a data packet in a transfer path, and to transfer a single data packet to a plurality of The processing block has the effect of enabling continuous image processing.
ProcessInstruction, which is an indicator of the image data processing method, has the effect that it is possible to extend in the transfer path and to perform eight or more processes in succession.
[0099]
It is possible to change / return the ChipID in the transfer path, and there is an effect that 15 or more chips can be provided in the system.
[0100]
It is possible to provide an image ring in the system, which has the effect of reducing the possibility that the image ring will limit system performance when transferring large amounts of data.
[Brief description of the drawings]
FIG. 1 best illustrates an image ring bridge according to the present invention.
FIG. 2 is a diagram showing an environment to which the present invention is applied;
FIG. 3 is a diagram showing a system controller to which the present invention is applied.
FIG. 4 is a diagram of a system control unit used in the present invention.
FIG. 5 is a diagram showing a data packet format.
FIG. 6 is a diagram showing a command packet format.
FIG. 7 is a diagram showing an interrupt packet format.
FIG. 8 is a diagram showing a packet table format / chain table format.
[Explanation of symbols]
1001, 1023 The device of the present invention
1002, 1020 database server
1003 Database client
1004, 1022 Email server
1005 Email Client
1006, 1021 WWW server
1007 DNS server
1010 LAN
1011 router
1012 Internet / Intranet
1030 PSTN or ISDN
1031 FAX machine
1040 Printer
2000 Controller Unit
2001 CPU
2002 RAM
2003 ROM
2004 HDD (Hard Disk Drive)
2006 Operation unit interface
2007 System Bus Bridge
2008 Image Ring 1
2009 Image Ring 2
2010 LAN controller
2011 LAN
2012 UI (operation unit)
2070 Scanner (scanner)
2095 Printer
2123 Image memory 1
2124 RAM controller
2125 ROM controller
2126 CPU bus
2127 IO Bus 1
2129 IO Bus 2
2138 USB interface
2139 General-purpose serial port
2140 Interrupt Controller
2141 GPIO interface
2142 General-purpose bus interface
2145 MAC circuit
2147 Image Ring Interface 1
2148 Image Ring Interface 2
2143 General-purpose PCI bus
2144 Disk Controller
2146 PHY / PMD
2149, 2151 Image processing unit
2150 System control unit
2155 Image memory 2
3001 Header information
3002 Tile unit image data
3003 Image additional information
3004 PckType
3005 ChipID
3006 DataType
3007 PageID
3008 JobID
3009 Tile coordinate in Y direction
3010 Tile coordinates in X direction
3011 Process Instruction
3012 Packet Byte Length
3013 Image Data Offset
3014 Z Data Offset
3015 Image Data Byte Length
3016 Z Data Byte Length
3017 Compress Flag
3019 UnitID
3020 Mode
4002 Packet data section
4004 ChipID
4005 CmdType
4006 Cmdnum
4007 PageID
4008 JobID
4009 PacketID
4010 packet byte length
4011 address
4012 data
5001 TileIN block
5002 Packet data section
5003 PageID, JobID register
5004 ChipID
5005 IntChipID
5006 packet byte length
5007 Status information
5021 First register group
5023 Hit signal
5025 Miss signal
5026 Second register group
5027 output buffer
5029 TileOut block
5030 TileIn block
5031 trans signal
5104-5106 Data packet buffer
5107 Data packet buffer (PageID)
5108 Data packet buffer (JobID)
5109-5120 Data packet buffer
6001 Packet Table
6002 Start Address of Packet
6003 Repeat Flag
6004 Divide Flag
Byte Length of 6005 Packet
6006 Chain Table number
6010 Chain Table
6011 Chain Block Address
6012 Chain Block Length

Claims (4)

A data packet including at least one packet identifier unique to each packet set, image data, an indicator of a processing method for the image data, and a ChipID for designating a processing unit on which the image data is processed;
Ring-shaped first data packet transfer means for transferring the data packet,
Ring-shaped second data packet transfer means for transferring the data packet,
The first data packet transfer means, and an image ring bridge connected to the second data packet transfer means,
In the above image ring bridge,
A data packet transfer path for outputting a data packet input from the first data packet transfer means to the first data packet transfer means,
A packet identification information register for storing at least one set of information equivalent to the packet identifier;
Comparing means for comparing the packet identification information register with the packet identifier of the input data packet;
A first register group capable of setting a plurality of sets of information equivalent to ChipID in the data packet and an indicator of an image data processing method;
A second register group capable of holding information equivalent to the ChipID in the data packet and an indicator of the image data processing method;
In the register specified by the packet identifier of the data packet input from the first image ring, an indicator of the image data processing method of the data packet input from the first image ring is set based on the result of the comparison means. Means to write,
Means for transferring a data packet input from the first image ring to the second image ring,
Means for changing the ChipID and the indicator of the image data processing method to the value read from the first register group at the time of the transfer;
Means for transferring a data packet input from the second image ring to the first image ring,
Means for changing the indicator of the image data processing method in the data packet to the indicator of the image data processing method read from the second register group, based on the content of the packet identifier,
An image ring bridge system comprising: An image ring bridge device, wherein the means according to claim 1 is integrated on a single semiconductor substrate. 2. The image ring bridge system according to claim 1, wherein the image data in the data packet is rectangular data. An image ring bridge device, wherein the means according to claim 2 is integrated on a single semiconductor substrate.

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