JP2004320049A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a WCSP type semiconductor device in which impedance matching is designed between a circuit element provided in a semiconductor chip and re-wiring that is a signal line electrically connected to the element. <P>SOLUTION: The device is packaged in an outside dimension equal to a semiconductor chip 15 having a circuit element, and has a plurality of electrode pads 20 (20a, 20b) provided on the semiconductor chip; an insulating layer 32 provided on the semiconductor chip such that surfaces of the electrode pads 20 are partially exposed; a plurality of outer terminals 45 provided each on an upperside of the insulating layer and on positions different from those directly over the electrode pads; and a plurality of wiring 35 including first wiring 35a that is a ground line and second wiring 35b that is a signal line, which are provided on the insulating layer for electrically connecting between respective electrode pads and respective outer-terminals, wherein the second wiring is provided between two first wiring, and the first wiring is in a mesh pattern. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a semiconductor device having a package structure, and particularly to a semiconductor device having a WCSP type.

  With the increasing demand for higher integration of semiconductor devices mounted on electronic devices and higher frequencies of transmission signals, CSP (CSP), a semiconductor device packaged with an outer size almost the same as the outer size of a semiconductor chip. Chip Size Package) is attracting attention.

  In recent years, in particular, for the purpose of reducing the manufacturing cost and the like, the technical development of a WCSP (Waferlevel Chip Size Package), which is a CSP singulated by dicing, by completing the external terminal forming process in a wafer state, is being advanced. Have been.

  Some WCSPs have a structure in which electrode pads on a semiconductor chip and external terminals are electrically connected via wiring (rewiring) that relocates the external terminals to desired positions.

  In the WCSP having such rewiring, the degree of freedom in wiring design is improved by the rewiring.

  In the case of transmitting a high-frequency signal using the WCSP having the above-described rewiring, between a circuit element included in a semiconductor chip and a signal line electrically connected to the circuit element via an electrode pad, that is, a rewiring. It is desirable to match the impedance of both.

  By overcoming the impedance mismatch between the two, the attenuation of the transmission signal due to the reflection of the transmission signal generated near the junction between the electrode pad and the signal line can be suppressed.

  However, despite the fact that the characteristic impedance of the signal line in the WCSP is sufficiently larger than the impedance of the circuit element, an effective method for reducing the characteristic impedance of the signal line and achieving impedance matching between the two has been proposed. Not been.

  SUMMARY OF THE INVENTION An object of the present invention is to achieve impedance matching between the impedance of a circuit element and the characteristic impedance of a signal line electrically connected to the circuit element, thereby reducing reflections and the like that become conspicuous as the transmission signal becomes higher in frequency. An object of the present invention is to provide a semiconductor device having excellent high-frequency characteristics in which generation is suppressed.

  Therefore, the semiconductor device of the present invention has the following structural features.

  That is, the semiconductor device of the present invention has a configuration in which a semiconductor chip including circuit elements is packaged, and the outer dimensions of the packaging are substantially the same as the outer dimensions of the semiconductor chip. Have. A plurality of electrode pads are formed on the semiconductor chip, and a plurality of electrode pads are formed on an insulating film provided so as to expose a part of the surface of the electrode pad and at a position different from the position immediately above the electrode pad. External terminals for external connection are formed. Each of the electrode pads and each of the external terminals are electrically connected via a wiring provided on the insulating film. The wiring includes first and second wirings, the first wiring being a ground line, that is, a GND line, and the second wiring transmitting an electric signal having a voltage based on the ground voltage. Acts as a signal line. The first wiring is provided at a position sandwiching the second wiring.

  According to this configuration, since the signal line is provided at a position sandwiched by the first wiring, that is, the GND line, electromagnetic coupling between the GND line and the signal line is enhanced. As a result, the capacitance between the GND line and the signal line increases, and the inductance of the signal line decreases, so that the characteristic impedance of the signal line can be reduced as compared with the related art.

  Note that the first wiring is a mesh wiring.

  According to this configuration, since the first wiring is formed in a mesh shape, the area occupied by the first wiring itself can be reduced. Desired interaction can be suppressed.

  Further, unlike the configuration in which the first and second external terminals are provided on the same insulating layer described above, the first external terminal is provided above the lamination of the first and second insulating layers provided on the semiconductor chip. In the case where the second external terminal is provided above the second insulating layer, the connection between the first electrode pad and the first external terminal is extended over the second insulating layer. The first wiring which is a ground line, that is, a GND line, and the connection between the second electrode pad and the second external terminal is a second wiring which is a signal line and extends on the first insulating layer. And the first wiring covers the second wiring from above.

  According to this configuration, since the structure of the first and second wirings is a microstrip line structure, the characteristic impedance of the signal line can be reduced as compared with the related art, and the GND line is arranged farther from the semiconductor chip. Therefore, occurrence of undesired interaction between the GND line and the circuit element in the semiconductor chip can be suppressed.

  According to the semiconductor device of the present invention, the characteristic impedance of the signal line and the impedance of the circuit element can be more matched than before.

  Therefore, transmission of a high-frequency signal can be efficiently realized, and a semiconductor device having higher-frequency characteristics than a conventional device can be obtained.

  Hereinafter, an embodiment of the present invention will be described with reference to FIGS. Each drawing schematically shows a configuration example of a semiconductor device according to the present invention. Further, the drawings merely schematically show the shapes, sizes, and arrangements of the components to the extent that the present invention can be understood, and the present invention is not limited to these illustrated examples. Also, for the sake of simplicity of the drawing, hatching (oblique lines) showing a cross section is omitted except for a part. In the following description, specific materials and conditions may be used, but these materials and conditions are merely one of preferred examples, and are not limited thereto. Further, in each of the drawings, the same components are denoted by the same reference numerals, and the duplicate description thereof may be omitted.

  In each of the embodiments described below, each CSP obtained by cutting out a CSP in a wafer state by dicing will be referred to as a WCSP, and the WCSP will be described as an example of a semiconductor device.

<First embodiment>
A semiconductor device according to a first embodiment of the present invention will be described with reference to FIGS. FIG. 1 is a plan view schematically showing a WCSP 10, which is a semiconductor device according to this embodiment. FIG. 2A is an enlarged view of a region A surrounded by a broken line in the plan view shown in FIG. 1 and showing each component in detail (in each of the following embodiments, FIG. Are omitted, and description will be made with reference to the figure corresponding to this enlarged schematic view.) FIG. 2B is a view of a cut (cross section) obtained by cutting FIG. 2A along the broken line II ′ as viewed in the direction of arrow I in the figure. FIG. 2C is a view in which a cut (cross section) obtained by cutting FIG. 2A along the broken line portion PP ′ is viewed from the direction of arrow P in the figure (the following embodiment). The same applies to the embodiment.) In FIGS. 1 and 2A, for the sake of convenience, the illustration of a sealing film 50 such as an organic resin film included in the WCSP 10 is omitted, and in FIG. The illustration is omitted.

  The electrode pads 20 made of aluminum (Al) are arranged at predetermined intervals along the outer periphery of the semiconductor chip 15 on the semiconductor chip 15 provided in the WCSP 10 as a semiconductor device. In the example shown in FIG. 1, since the planar shape of the WCSP 10 is a square, the electrode pads 20 are arranged linearly along each side of the square. The number and positions of the electrode pads 20 are not limited to this, and, for example, only one set may be opposed to the semiconductor chip 15.

As shown in FIGS. 2A and 2B, insulating layers such as a passivation film 25 and a protective film 30 are formed on a semiconductor chip 15 having circuit elements so that the surfaces of the electrode pads 20 are exposed. (Here, this insulating layer is also referred to as a first insulating layer.) 32 is sequentially provided. The passivation film 25 is formed of, for example, a silicon oxide film (SiO ₂ ), and the protective film 30 is formed of a low-hardness film material such as a polyimide resin. And the peeling due to stress between the sealing film 50 and the semiconductor chip 15 are suppressed.

  As shown in FIG. 2A, each electrode pad 20 (20a, 20b) is electrically connected to a corresponding post section 40 (40a, 40b) via a dedicated wiring 35 (35a, 35b). Are individually connected. The wiring 35 extends on the protective film 30 toward the center of the semiconductor chip 15 and is formed of copper (Cu).

  More specifically, each of the wirings 35 in this embodiment is connected to the electrode pad 20 corresponding to the wiring 35, and is formed on a surface of each of the wirings 35 extending on the first insulating layer 32. Is a configuration in which the post part 40 is formed.

  Thus, the solder balls (bumps) (not shown), which are external terminals for connecting to the mounting substrate, formed on the post portions 40 by the wirings 35, are substantially horizontal regardless of the positions of the electrode pads 20. It can be arranged at a desired position above, that is, at a shifted position above the semiconductor chip 15 from a position immediately above the electrode pad 20. Therefore, the wiring 35 functions as a rewiring that enables the rearrangement of the external terminals (hereinafter, the wiring 35 may be referred to as a rewiring).

  As shown in FIGS. 2B and 2C, a sealing film 50 such as an epoxy resin is provided on the upper surface side of the semiconductor chip 15 so as to cover the passivation film 25 and the protection film 30 and the like. The posts (40a, 40b) are formed so as to expose the surfaces thereof. The posts (40a, 40b) are connected to solder balls 45 as external terminals, which are bumps for connection to a printed circuit board (not shown).

  According to the connection structure of the wiring 35 shown in FIG. 2A, each of the two first wirings 35a, 35a establishes a connection between the first electrode pad 20a, 20a and the first post part 40a, 40a, respectively. Is going. Further, the second wiring 35b connects between the second electrode pad 20b and the second post part 40b. Since the first wirings 35a and 35a are supplied with a ground (GND) potential, they are also referred to as a GND line or a GND layer. The second wiring 35b is also referred to as a signal line or a signal layer because an electric signal of a voltage based on the GND potential, that is, a high-frequency signal (a fluctuating potential signal) is supplied to the second wiring 35b. In this configuration example, the high frequency means the frequency of a signal transmitted through a signal line having a length that does not become extremely short with respect to the effective wavelength of the operating frequency of the semiconductor chip.

  In this case, the second wiring 35b is arranged on the upper surface of the protective film 30 between the pair of first wirings 35a, 35a so as not to be in contact with each other.

  As described above, in the connection structure of these wirings illustrated in FIG. 2A, when the first and second wirings are viewed in a plan view, the two first wirings sandwich the second wiring from both sides. It has a coplanar line structure.

  In this coplanar line structure, since the signal line 35b is provided at a position interposed between the GND lines 35a, electromagnetic coupling between the GND line 35a and the signal line 35b is enhanced. As a result, the capacitance between the GND line 35a and the signal line 35b increases, and the inductance of the signal line decreases, so that the characteristic impedance of the signal line 35b can be reduced as compared with the related art.

  Therefore, according to the inventor of the present invention, the matching between the reduced characteristic impedance of the signal line 35b and the impedance of the circuit element is performed in particular by considering the arrangement position of the GND line 35a which is the rewiring. I found that I could take it.

The matching between the characteristic impedance of the signal line 35b and the impedance of the circuit element mainly depends on the width of the GND line 35a (indicated by A in FIG. 2C) and the width of the signal line 35b (in FIG. 2C). shown by B.), the thickness of the GND line 35a shown in d ₁ (FIG. 2 (C).), the thickness of the signal line 35b (FIG. 2 (C) shown by d _2.), and GND line 35a The horizontal distance from the signal line 35b (indicated by C in FIG. 2C), the resistivity ρ of the wiring 35 (here, copper (Cu) is used as a material for forming the wiring 35), and a semiconductor The dielectric constant ε of the dielectric layer around the conductive part (the wiring 35, the electrode pad 20, the post part 40) on the chip 15 (here, the signal line 35b and the GND have a large effect on the characteristic impedance of the signal line 35b) The dielectric constant ε) of the epoxy resin 50 between the lines 35a and the surrounding dielectric Layer (in this case, the epoxy resin 50) thickness (in FIG. 2 (C) shown by d _3.) By adjusting the can take. Further, when the material of the wiring 35 is a magnetic material, it is desirable to consider the magnetic permeability.

  In the configuration example shown in FIGS. 2A to 2C, the first and second electrode pads 20a, 20b, 20a are linearly juxtaposed, and each of the wirings 35a, 35b, 35a is connected to these electrodes. In the direction orthogonal to the arrangement direction of the pads, linearly extends from directly above the electrode pads to the respective post portions 40a, 40b, 40a. Therefore, the width of the signal line 35b (indicated by B in FIG. 2C) here is the contact of the signal line 35b with the second electrode pad 20b of the signal line 35b when viewed in plan in FIG. 2A. The signal line portion (the portion indicated by L in FIG. 2B) between the portion 351 (see FIG. 2B) and the contact portion 352 (see FIG. 2B) with the external terminal 40b is an electrode pad. Are shown in the array direction. Similarly, the width of the GND line 35a (indicated by A in FIG. 2C) indicates the width of the GND line portion corresponding to L in FIG. 2B in the arrangement direction of the electrode pads.

Therefore, for example, when it is desired to set the characteristic impedance of the signal line 35b to about 50 [Ω], which is substantially the same as the impedance of the circuit element included in the semiconductor chip 15, for example, A = 200 [μm] and B = 40 [ μm], d ₁ = 5 [μm], d ₂ = 5 [μm], C = 23 [μm], ρ = 1.67 × 10 ⁻⁶ [Ωcm (20 ° C.)], ε ≒ 4 [F / m] ] And d ₃ = 90 [μm].

  As described above, the width of the GND line and the signal line and the interval between the GND line and the signal line are determined by the resistivity of the material forming the GND line and the signal line and the dielectric constant of the dielectric layer filling the gap between the GND line and the signal line. The value depends on.

  With the above-described setting conditions, the characteristic impedance of the signal line 35b can be set to about 50 [Ω]. Therefore, the impedance mismatch between the signal line 35b and the circuit element included in the semiconductor chip 15 can be achieved. Can be overcome.

  That is, in this embodiment, a function for reducing the characteristic impedance of the signal line is further added to the wiring provided to rearrange the external terminals.

  As is clear from the above description, in this embodiment, the matching between the characteristic impedance of the signal line 35b and the impedance of the circuit element included in the semiconductor chip 15 is realized.

  Therefore, transmission of a high-frequency signal can be efficiently realized, and a semiconductor device having higher-frequency characteristics than a conventional device can be obtained.

<Second embodiment>
A semiconductor device according to a second embodiment of the present invention will be described with reference to FIG.

  In this embodiment, the first point is that the width (= A) of the GND line 35a and the interval (= C) between the GND line 35a and the signal line 35b are set to be narrower than those in the first embodiment. This is the main difference from the embodiment. In addition, the same components as those already described in the first embodiment are denoted by the same reference numerals, and specific description thereof may be omitted (the following embodiments are also described). Similar).

  A passive element such as a coil or a capacitor is formed on the upper portion of the semiconductor chip 15 to which a high-frequency signal is transmitted (not shown). Such a passive element may be affected by an electromagnetic field radiated when a current flows through the post section 40 or the wiring 35, and may make the operation of the integrated circuit included in the semiconductor chip 15 unstable.

  Therefore, as shown in FIGS. 3A and 3C, in this embodiment, of the rewiring in the first embodiment, the width (= B) of the signal line 35b, the GND line 35a and the signal The interval (= C) between the lines 35b is the same or almost the same as that in the first embodiment, but the GND line 35a has a width that is significantly wider than the width (= B) of the signal line 35b. Is set so as to further narrow the width (= A).

  However, the electromagnetic coupling between the GND line 35a and the signal line 35b is weakened by reducing the width (= A) of the GND line 35a. Therefore, the charge capacity between the GND line 35a and the signal line 35b decreases, and the inductance increases.

  As a result, the characteristic impedance of the signal line 35b is increased by reducing the width (= A) of the GND line 35a because the characteristic impedance of the signal line is the square root of the value obtained by dividing the inductance by the capacitance.

  Therefore, in this embodiment, the interval (= C) between the GND line 35a and the signal line 35b is set to be narrower than that in the first embodiment, thereby suppressing an increase in the characteristic impedance of the signal line 35b. I do.

Therefore, for example, when it is desired to set the characteristic impedance of the signal line 35b to about 50 [Ω], which is almost the same as the impedance of the circuit element included in the semiconductor chip 15, for example, A = 100 μm, B = 40 μm, and d ₁ = 5 [μm], d ₂ = 5 [μm], C = 22 μm, ρ = 1.67 × 10 ⁻⁶ [Ωcm (20 ° C.)], ε ≒ 4 [F / m], and d ₃ = 90 [μm] What is necessary is just to set.

  With the above setting conditions, it is possible to overcome the impedance mismatch between the signal line 35b and the circuit element included in the semiconductor chip 15.

  As is apparent from the above description, in this embodiment, the same effect as in the first embodiment can be obtained.

  Further, in this embodiment, an undesired interaction between the GND line 35a, which is a rewiring, and the integrated circuit provided on the semiconductor chip 15 is suppressed, and a more reliable semiconductor device is obtained. be able to.

<Third embodiment>
A semiconductor device according to a third embodiment of the present invention will be described with reference to FIG.

  This embodiment is different from the first embodiment in that two GND lines 35a and 35a are further provided so as to surround a signal line 35b.

  In order to further reduce the transmission loss of high-frequency signals, not only the signal lines 35b but also conductive portions formed on the semiconductor chip 15 (for example, the electrode pads 20, the post portions 40 and the solder balls (external terminals) It is desirable to match the characteristic impedance of each component of (45) with the impedance of the circuit element.

  Therefore, as shown in FIG. 4A, in this embodiment, in the first embodiment, two GND lines 35a, 35a located at positions sandwiching the signal line 35b from both sides in a two-dimensional arrangement relationship. The end not connected to the first electrode pad 20a, that is, the end connected to the first post portions 40a, 40a is connected to the signal line 35b and the second post portion 40b connected to the signal line 35b. Are connected so as to surround them to form a connection wiring.

  Therefore, for example, when it is desired to set the characteristic impedance of the signal line 35b to about 50 [Ω], which is almost the same as the impedance of the circuit element included in the semiconductor chip 15, for example, as in the first embodiment, The setting condition of the portion is determined (see FIG. 4C), and further, the GND line 35a is formed in a U-shaped integrated structure from one electrode pad 20a to the other electrode pad 20a, and the GND line 35a is formed. At 35a, a signal line 35b and a second post 40b connected to the signal line 35b are provided so as to surround in a U-shape. Further, each of the first post portions 40a can be connected in the middle of the U-shaped GND line 35a.

  As a result, as shown in FIGS. 4A and 4B, as compared to the first embodiment, the GND line 35a extends over a wider area near the second post portion 40b connected to the signal line 35b. Be placed.

  As described above, by setting the width and the interval between the GND line 35a and the signal line 35b to be the same as the above-described setting conditions, it is possible to overcome the impedance mismatch between the signal line 35b and the circuit element included in the semiconductor chip 15. Can be.

  As is apparent from the above description, in this embodiment, the same effect as in the first embodiment can be obtained.

  Further, in this embodiment, since the characteristic impedance of the post portion 40 is reduced as compared with the first embodiment, a more reliable semiconductor device in which transmission loss of a high-frequency signal is further suppressed can be obtained. .

<Fourth embodiment>
A semiconductor device according to a fourth embodiment of the present invention will be described with reference to FIG.

  In this embodiment, the main difference from the second embodiment is that the GND line 35a is provided so as to surround the signal line 35b, as in the third embodiment. .

  Therefore, for example, when it is desired to set the characteristic impedance of the signal line 35b to about 50 [Ω], which is almost the same as the impedance of the circuit element included in the semiconductor chip 15, for example, as in the second embodiment, The setting conditions of the portion are determined (see FIG. 5C), and further, the GND line 35a is formed in a U-shaped integral structure from one electrode pad 20a to the other electrode pad 20a. At 35a, a signal line 35b and a second post 40b connected to the signal line 35b are provided so as to surround the signal line 35b in a U-shape. Further, each of the first post portions 40a can be connected in the middle of the U-shaped GND line 35a.

  As a result, as shown in FIGS. 5A and 5B, as compared to the second embodiment, the GND line 35a extends over a wider area near the second post portion 40b connected to the signal line 35b. Be placed.

  As described above, by setting the width and the interval between the GND line 35a and the signal line 35b to be the same as the above-described setting conditions, it is possible to overcome the impedance mismatch between the signal line 35b and the circuit element included in the semiconductor chip 15. Can be.

  As is clear from the above description, in this embodiment, the same effect as in the second embodiment can be obtained.

  Further, in this embodiment, since the characteristic impedance of the post portion 40 is reduced as compared with the second embodiment, a more reliable semiconductor device in which transmission loss of a high-frequency signal is further suppressed can be obtained. .

<Fifth embodiment>
A semiconductor device according to a fifth embodiment of the present invention will be described with reference to FIG.

  In this embodiment, while the width (= A) of the GND line 35a is set to be narrow, the interval (= C) between the GND line 35a and the signal line 35b is not narrowed, and the GND line 35a is not narrowed. The fourth embodiment is characterized in that the signal line 35b and the signal line 35b are embedded in a dielectric layer having a higher dielectric constant than the sealing film 50 (here, an epoxy resin (dielectric constant ε ≒ 4 [F / m])). This is the main difference from the form.

  Thus, in this embodiment, the GND line 35a and the signal line 35b are embedded in a dielectric layer 55 made of a phenol resin (dielectric constant ε ≒ 4.5 to 5 [F / m]) (FIG. 6 (A)-(C)).

  By embedding the dielectric layer 55 between the GND line 35a and the signal line 35b, the electromagnetic coupling between them is strengthened as compared with the case where the dielectric layer 55 is embedded in the epoxy resin 50 therebetween.

  Therefore, by using the dielectric layer 55, the characteristic impedance of the signal line 35b that is increased by reducing the width (= A) of the GND line 35a can be reduced.

  In this embodiment, the dielectric layer 55 is provided so as to cover the entire surface of the semiconductor chip 15 except for the region of the post part 40. However, at least one of the GND lines 35a located at the position sandwiching the signal line 35b. What is necessary is just to be provided so as to embed between the GND line 35a and the signal line 35b over the other GND line 35a. This is because the increase in the capacitance between the GND line 35a and the signal line 35b can be remarkably realized at least by strengthening the electromagnetic coupling therebetween. As a result, the characteristic impedance of the signal line 35b can be effectively reduced.

Therefore, for example, when it is desired to set the characteristic impedance of the signal line 35b to about 50 [Ω], which is almost the same as the impedance of the circuit element included in the semiconductor chip 15, for example, A = 100 μm, B = 40 μm, and d ₁ = 5 [μm], d ₂ = 5 [μm], C = 23 μm, ρ = 1.67 × 10 ⁻⁶ [Ωcm (20 ° C.)] and ε ≒ 4.5-5 [F / m] and d ₃ = What is necessary is just to set it as 90 [micrometer].

  With the above-described setting conditions, it is possible to overcome the impedance mismatch between the signal line 35b and the circuit element included in the semiconductor chip 15.

  As is clear from the above description, in this embodiment, the same effect as in the fourth embodiment can be obtained.

<Sixth Embodiment>
A semiconductor device according to a sixth embodiment of the present invention will be described with reference to FIG.

  The main difference between the third embodiment and the third embodiment is that the GND lines 35a are provided in a mesh shape.

  As shown in FIG. 7A, the occupation area of the GND line 35a itself can be reduced by forming the GND line 35a in a mesh shape, so that the GND line 35a, which is a rewiring, and the semiconductor chip 15 are connected to each other as described above. Unwanted interaction with the integrated circuit provided can be suppressed.

Therefore, for example, when it is desired to set the characteristic impedance of the signal line 35b to about 50 [Ω] which is substantially the same as the impedance of the circuit element included in the semiconductor chip 15, for example, A = 20 μm (mesh width), B = 40 μm, d ₁ = 5 [μm], d ₂ = 5 [μm], C = 22 μm, ρ = 1.67 × 10 ⁻⁶ [Ωcm (20 ° C.)], ε ≒ 4 [F / m] and d _What is necessary is just to set so that ₃ = 90 [μm].

  With the above setting conditions, it is possible to overcome the impedance mismatch between the signal line 35b and the circuit element included in the semiconductor chip 15.

  As is clear from the above description, in this embodiment, the same effect as in the third embodiment can be obtained.

  Further, in the present embodiment, since the GND lines 35a are meshed, undesired interaction between the GND lines 35a, which are rewirings, and the integrated circuit provided on the semiconductor chip 15 is suppressed. Thus, a more reliable semiconductor device can be obtained.

<Seventh embodiment>
A semiconductor device according to a seventh embodiment of the present invention will be described with reference to FIG. FIG. 8D is a view of a cut (cross section) obtained by cutting FIG. 8A along the broken line QQ ′ line as viewed in the direction of arrow P in the figure.

  Therefore, as shown in FIG. 8A, in the wiring structure of this embodiment, the GND line 35a connects the signal line 35b to, for example, a dielectric layer formed of a polyimide film (here, this dielectric layer The body layer is also referred to as a second insulating layer.) A microstrip line structure is provided at a position to cover the body layer via a layer 60.

  More specifically, as shown in FIGS. 8A to 8D, a first insulating layer 32 and a second insulating layer 60 on the first insulating layer 32 are provided on the semiconductor chip 15. . The upper surface of the first electrode pad 20a is exposed from the first and second insulating layers (32, 60), and the second electrode pad 20b is exposed from the first insulating layer 32. Then, the solder balls 45, which are formed on the first and second post portions (40a, 40b) and are external terminals for connecting to the mounting board, are connected to the first and second electrode pads (20a, 20b), respectively. It is arranged at a shifted position above the semiconductor chip 15 from directly above. At this time, the second post portion 40b is provided on the signal line 35b located on the first insulating layer 32. The side surface of the second post portion 40b is covered with the second insulating layer 60 and the resin seal 50. Further, the first post portion 40a is provided on the GND line 35a located on the second insulating layer 60. The side surface of the first post portion 40a is covered with a sealing film 50. The first and second post portions (40a, 40b) are led out to the surface of the sealing film 50 and connected to the solder balls 45 as external terminals, as already described in the first to sixth embodiments. It is connected.

  In this configuration example, the signal line 35b connected to the second electrode pad 20b extends on the protective film 30, and thus on the first insulating layer 32, toward the center of the semiconductor chip 15, and is electrically connected to the second post portion 40b. Connected.

  On the other hand, the GND line 35a connected to the first electrode pad 20a extends from the first electrode pad 20a in the vertical direction of the first electrode pad 20a and then exposes the surface of the second post portion 40b. It is provided continuously over the dielectric layer 60 covering the semiconductor chip 15 and is electrically connected to the first post part 40a.

  As described above, the microstrip line structure provided so that the signal line 35b and the GND line 35a overlap with each other is provided at a position where the signal line 35b is sandwiched between the GND lines 35a, similarly to the coplanar line structure. Therefore, electromagnetic coupling between the GND line 35a and the signal line 35b is strengthened. As a result, the capacitance between the GND line 35a and the signal line 35b increases, and the inductance of the signal line decreases, so that the characteristic impedance of the signal line 35b can be reduced as compared with the related art.

  Further, in the microstrip line structure, the GND line 35a is arranged at a position further away from the semiconductor chip 15 than in the coplanar line structure.

  Therefore, undesired interaction between the GND line 35a and the integrated circuit provided on the semiconductor chip 15 can be more effectively suppressed.

  In this embodiment, the second insulating layer, that is, the dielectric layer 60 is provided so as to cover the entire surface of the semiconductor chip 15 except for the region of the second post portion 40b, but at least at a position covering the signal line 35b. It is sufficient if provided. This is because the increase in the capacitance between the GND line 35a and the signal line 35b can be remarkably realized at least by strengthening the electromagnetic coupling therebetween. As a result, the characteristic impedance of the signal line 35b can be effectively reduced. Further, as described in the first embodiment, two GND lines 35a are provided on both sides of the signal line 35b so as to extend along the signal line 35b and reach the dielectric layer 60. May be provided continuously.

More specifically, matching between the characteristic impedance of the signal line 35b and the impedance of the circuit element included in the semiconductor chip 15 is mainly based on the width of the GND line 35a (indicated by A in FIGS. 8C and 8D). , the width of the signal line 35b (shown in FIG. 8 (C) in B.), the thickness of the GND line 35a (in Fig. (C) shown by d _1.), the thickness of the signal line 35b (in Fig. (C) indicated by d _2.),. indicated by the vertical distance between the GND line 35a and the signal line 35b (FIG. 8 (C) and (D) in C '), the resistivity of the wiring 35 (the wiring 35a, 35b) [rho (Here, Cu) and the dielectric constant ε of the dielectric layer around the conductive portion (electrode pad 20, post portion 40) on the semiconductor chip 15 (here, the influence on the characteristic impedance of the signal line 35b is large). , Dielectric constant ε of polyimide film 60 between signal line 35b and GND line 35a) And, the dielectric layer of the surrounding (in this case, the polyimide film 60) the thickness (shown by d ₄ in FIG. (C).) Adjust the can take. Further, when the material of the wiring 35 is a magnetic material, it is desirable to consider the magnetic permeability.

Therefore, for example, when it is desired to set the characteristic impedance of the signal line 35b to about 50 [Ω], which is almost the same as the impedance of the circuit element included in the semiconductor chip 15, for example, A = 400 μm, B = 40 μm, and d ₁ = 5 μm, d ₂ = 5 μm, C ′ = 33 μm, ρ = 1.67 × 10 ⁻⁶ [Ωcm (20 ° C.)], ε ≒ 3.3 [F / m], and d ₄ = 38 [Μm] may be set.

  With the above-described setting conditions, the characteristic impedance of the signal line 35b can be set to about 50 [Ω]. Therefore, the impedance mismatch between the signal line 35b and the circuit element included in the semiconductor chip 15 can be achieved. Can be overcome.

  As is clear from the above description, in this embodiment, the matching between the characteristic impedance of the signal line 35b and the impedance of the circuit element included in the semiconductor chip 15 is realized. Therefore, transmission of a high-frequency signal can be efficiently realized, and a semiconductor device having higher-frequency characteristics than a conventional device can be obtained.

<Eighth Embodiment>
With reference to FIG. 9, a semiconductor device according to an eighth embodiment of the present invention will be described.

  In this embodiment, a dielectric layer 65 having a higher dielectric constant than the dielectric layer 60 is used as the second insulating layer instead of the dielectric layer 60 in the seventh embodiment. This is the main difference from the seventh embodiment.

  In this embodiment, a phenol resin (dielectric constant ε ≒) is used as the dielectric layer 65 instead of the dielectric layer 60 (polyimide film (dielectric constant ε ≒ 3.3 [F / m])) in the seventh embodiment. 4.5 to 5 [F / m]).

Therefore, for example, when it is desired to set the characteristic impedance of the signal line 35b to about 50 [Ω], which is almost the same as the impedance of the circuit element included in the semiconductor chip 15, for example, A = 400 μm, B = 40 μm, and d ₁ = 5 μm, d ₂ = 5 μm, C ′ = 35 μm, ρ = 1.67 × 10 ⁻⁶ [Ωcm (20 ° C.)], ε ≒ 4.5-5 [F / m] and d ₄ = 38 [μm].

  With the above-described setting conditions, the same effects as in the seventh embodiment can be obtained.

  Further, in this embodiment, a dielectric layer having a higher dielectric constant than that of the seventh embodiment, that is, a second insulating layer 65 is interposed between the signal line 35b and the GND line 35a.

  As a result, the vertical interval (C 'in the figure) between the signal line 35b and the GND line 35a can be further increased as compared with the seventh embodiment.

  Therefore, an undesired interaction between the GND line 35a, which is a rewiring, and the integrated circuit provided on the semiconductor chip 15 is suppressed, and a more reliable semiconductor device can be obtained.

  As described above, the present invention is not limited to only the combinations of the above-described embodiments. Therefore, the present invention can be applied by combining suitable conditions at any suitable stage.

  Further, in each of the above-described embodiments, by providing the signal line 35b such that the signal line length of the signal line 35b is equal to or less than ４ of the effective wavelength of the operating frequency of the semiconductor chip, the transmission signal is reduced. Can be more effectively suppressed from being attenuated due to reflection or the like.

FIG. 1 is a schematic plan view showing a semiconductor device according to a first embodiment of the present invention. 1A to 1C are a schematic plan view and a schematic cross-sectional view showing a part of a semiconductor device according to a first embodiment of the present invention. FIGS. 4A to 4C are a schematic plan view and a schematic cross-sectional view showing a part of a semiconductor device according to a second embodiment of the present invention. (A) to (C) are a schematic plan view and a schematic cross-sectional view showing a part of a semiconductor device according to a third embodiment of the present invention. (A) to (C) are a schematic plan view and a schematic cross-sectional view showing a part of a semiconductor device according to a fourth embodiment of the present invention. FIGS. 11A to 11C are a schematic plan view and a schematic sectional view showing a part of a semiconductor device according to a fifth embodiment of the present invention. FIGS. 21A to 21C are a schematic plan view and a schematic cross-sectional view showing a part of a semiconductor device according to a sixth embodiment of the present invention. (A) to (D) are a schematic plan view and a schematic sectional view showing a part of a semiconductor device according to a seventh embodiment of the present invention. (A) to (D) are a schematic plan view and a schematic sectional view showing a part of a semiconductor device according to an eighth embodiment of the present invention.

Explanation of reference numerals

10 WCSP
DESCRIPTION OF SYMBOLS 15 ... Semiconductor chip 20 ... Electrode pad 20a ... First electrode pad 20b ... Second electrode pad 25 ... Passivation film 30 ... Protective film 32 ... First insulating layer 35 ... Wiring 35a ... GND line (first wiring)
35b ... signal line (second wiring)
40 post part 40a first post part 40b second post part 45 solder ball (external terminal)
50 ... sealing film 55 ... dielectric layer 60, 65 ... dielectric layer (second insulating layer)
351,352 ... contact part

Claims (9)

In a semiconductor device packaged with the same outer dimensions as the outer dimensions of a semiconductor chip having circuit elements,
A plurality of electrode pads provided on the semiconductor chip,
An insulating layer provided on the semiconductor chip so as to expose a part of the surface of the electrode pad,
Above the insulating layer, a plurality of external terminals provided at positions different from immediately above the electrode pad,
A plurality of electrode pads provided on the insulating layer for electrically connecting each of the electrode pads to each of the external terminals, the first pad being a ground line and the second line being a signal line; With the wiring of
The second wiring is provided between the two first wirings, and is provided.
The semiconductor device according to claim 1, wherein the first wiring is a mesh wiring. In a semiconductor device packaged with the same outer dimensions as the outer dimensions of a semiconductor chip having circuit elements,
A plurality of electrode pads including first and second electrode pads provided on the semiconductor chip;
A first insulating layer provided on the semiconductor chip so as to expose a part of the surface of the first and second electrode pads, and an upper side of the first insulating layer so as to expose a part of the first electrode pad; A second insulating layer provided on the
A first external terminal provided at a position above the second insulating layer and at a position different from immediately above the first and second electrode pads;
A second external terminal provided at a position above the second insulating layer and at a position different from immediately above the first and second electrode pads;
A first wiring which is provided on the second insulating layer for electrically connecting the first electrode pad and the first external terminal, and serves as a ground line;
A second wiring that is provided on the first insulating layer for electrically connecting the second electrode pad and the second external terminal, and that serves as a signal line;
The semiconductor device, wherein the first wiring is a mesh wiring and is provided so as to cover the second wiring from above. In a semiconductor device packaged with the same outer dimensions as the outer dimensions of a semiconductor chip having circuit elements,
A plurality of electrode pads provided on the semiconductor chip,
An insulating layer provided on the semiconductor chip so as to expose a part of the surface of the electrode pad,
Above the insulating layer, a plurality of external terminals provided at positions different from immediately above the electrode pad,
A plurality of electrode pads provided on the insulating layer for electrically connecting each of the electrode pads to each of the external terminals, the first pad being a ground line and the second line being a signal line; With the wiring of
The second wiring is provided between the two first wirings, and is provided.
The first wiring is provided so that the characteristic impedance of the second wiring can be matched with the impedance of the circuit element to which the second wiring is connected via the electrode pad. Semiconductor device. In a semiconductor device packaged with the same outer dimensions as the outer dimensions of a semiconductor chip having circuit elements,
A plurality of electrode pads including first and second electrode pads provided on the semiconductor chip;
A first insulating layer provided on the semiconductor chip to expose a part of the surface of the first and second electrode pads, and an upper side of the first insulating layer to expose a part of the first electrode pad; A second insulating layer provided on the
A first external terminal provided at a position above the second insulating layer and at a position different from immediately above the first and second electrode pads;
A second external terminal provided at a position above the second insulating layer and at a position different from immediately above the first and second electrode pads;
A first wiring which is provided on the second insulating layer for electrically connecting the first electrode pad and the first external terminal, and serves as a ground line;
A second wiring that is provided on the first insulating layer for electrically connecting the second electrode pad and the second external terminal, and that serves as a signal line;
The first wiring is provided so as to cover the second wiring from above,
The first wiring is provided so that characteristic impedance of the second wiring and impedance of the circuit element to which the second wiring is connected via the electrode pad can be matched. Semiconductor device.   3. The semiconductor device according to claim 1, wherein the first wiring has an impedance matching between a characteristic impedance of the second wiring and an impedance of the circuit element to which the second wiring is connected via the electrode pad. 4. A semiconductor device characterized by being provided so that   6. The semiconductor device according to claim 3, wherein the width of each of the first and second wirings and the distance between the first and second wirings are such that the impedance matching can be achieved. 7. A semiconductor device which is set to a value dependent on the resistivity of a material forming the first and second wirings and the dielectric constant of a dielectric layer provided between the first and second wirings.   6. The semiconductor device according to claim 3, wherein a thickness of each of the first and second wirings is different from a material of the first and second wirings so as to achieve the impedance matching. 7. A semiconductor device characterized by being set to a value that depends on the magnetic permeability and the dielectric constant of a dielectric layer provided between the first and second wirings. In a semiconductor device packaged according to the external dimensions of a semiconductor chip having circuit elements,
A plurality of electrode pads including first and second electrode pads provided on the semiconductor chip;
A first insulating layer provided on the semiconductor chip so as to expose a part of the surface of the first and second electrode pads, and an upper side of the first insulating layer so as to expose a part of the first electrode pad; A second insulating layer provided on the
A first external terminal provided at a position above the second insulating layer and at a position different from immediately above the first and second electrode pads;
A second external terminal provided at a position above the second insulating layer and at a position different from immediately above the first and second electrode pads;
A first wiring which is provided on the second insulating layer for electrically connecting the first electrode pad and the first external terminal, and serves as a ground line;
A second wiring that is provided on the first insulating layer for electrically connecting the second electrode pad and the second external terminal, and that serves as a signal line;
The semiconductor device according to claim 1, wherein the first wiring is provided in a partial region corresponding to the second wiring and a peripheral portion thereof so as to cover the second wiring from above. The semiconductor device according to claim 8,
A semiconductor device, wherein a flat surface is formed by a side surface of a semiconductor chip having a circuit element and a side surface of a sealing resin for packaging.

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